Abstract: The present invention provides an ionization detector having a base having an enclosed chamber. The enclosed chamber has a first end and a second end. The detector also includes a first outlet which is a source of an excitable medium. A second outlet is provided which functions a source of an analyte that is transported by a carrier gas. An ionization source for creating a discharge from said excitable medium is also provided. The collector electrode generates a time dependent current based on its interaction with ionized analytes from which the analyte may be detected.

Abstract: A semiconductor device testing apparatus 1A includes a tester unit 16 that generates an operational pulse signal, an optical sensor 10 that outputs a detection signal as a response to the operational pulse signal, a pulse generator 17 that generates a reference signal containing a plurality of harmonics for the operational pulse signal in synchronization with the operational pulse signal, a spectrum analyzer 13 that receives the detection signal and acquires a phase and amplitude of the detection signal at a detection frequency, a spectrum analyzer 14 that receives the reference signal and acquires a phase of the reference signal at a detection frequency, and an analysis control unit 18 that acquires a time waveform of the detection signal based on the phase and the amplitude of the detection signal acquired by the spectrum analyzer 13 and the phase of the reference signal. acquired by the spectrum analyzer 14.

Abstract: A street light cable anti-theft system includes a front-end control device, a signal control device and an information processing terminal. The front-end control device is disposed within a street light control box for applying a voltage signal to a street light cable when a street light is switched off. The signal control device is installed on a lighting pole of a last street light of a public lighting circuit for detecting a voltage signal of the street light cable, determining a state of the street light cable based on the obtained voltage signal, and sending the state signal to the information processing terminal. The information processing terminal is adapted for receiving and processing the state signal sent by the signal control device. The anti-theft system has some advantages of timely obtaining the information of the cable, low maintenance cost, not being affected by power failure and high reliability.

Abstract: A direct-current regulator includes: a fuse, a high-side switch, and a low-side switch connected in series between a high potential side input voltage terminal and a low potential side input voltage terminal; and a control unit configured to control the high-side switch and the low-side switch, wherein the fuse is formed on a silicon substrate on which the high-side switch is formed, and the fuse includes: two electrodes separately formed on the silicon substrate; a plurality of band-shaped polysilicon films formed between the two electrodes; and a linking part of a polysilicon film provided so as to connect the neighboring band-shaped polysilicon films at intermediate portions.

Abstract: An arc fault circuit interrupter test circuit is disclosed. The test circuit incorporates a controller along with at least one power transistor, a current sense circuit and a voltage sense circuit. When the power transistor is operated, the current flowing through the transistor is sensed, and if the current is not at least equal to a threshold value, the voltage at which the power transistor is operated is increased.

Abstract: Provided is a method for adapting the sensitivity of a sensor system, in particular of a capacitive sensor system, which provides a sensor signal, wherein a first lower threshold value is adapted, if the sensor signal fulfills a first switching threshold criterion, a first upper threshold value is adapted, if the sensor signal fulfills a second switching threshold criterion, and at least one switching threshold value is adapted such that the switching threshold value has a predetermined first distance from the first upper threshold value and/or a predetermined second distance from the first lower threshold value.

Abstract: An information processing system includes a cable and a first information processing apparatus. The cable connects information processing apparatuses to each other. The cable includes one or more first core wires through which information is transmitted, and one or more second core wires having a shape or component associated with preset information. The first information processing apparatus measures a first parameter that is related to the second core wires and changes with the shape or component, and to identify the cable using the measured first parameter.

Abstract: A remote monitoring system is presented. The system includes a sensor unit disposed in the electrical device, and configured to obtain measurement characteristics in response to a measurand of the electrical device, obtain reference characteristics insensitive to the measurand of the electrical device, and communicate the measurement characteristics and the reference characteristics using time varying electromagnetic fields.

Abstract: Provided is a device for performing at least one of detection and emission of electromagnetic waves, including a plurality of antennas, in which a first antenna includes a first radiating element and a first electronic element electrically connected to the first radiating element, and is sensitive to a first frequency band, and in which a second antenna includes a second radiating element and a second electronic element electrically connected to the second radiating element, and is sensitive to a second frequency band. At least a part of the second radiating element is arranged inside the first radiating element.

Abstract: The invention provides a capacitive sensor circuit in which a capacitance to be sensed is selectively coupled into a ring oscillator circuit. The ring oscillator frequency is measured with the capacitance coupled and not coupled, and a capacitance is derived from the change in ring oscillator frequency.

Abstract: An amplifying circuit comprises a differential input stage having a first input terminal, a second input terminal, and an intermediate node, wherein the differential input stage is configured to generate a differential current flowing through the intermediate node in response to an input voltage difference between the first and second input terminals. The amplifying circuit further comprises a first current source coupled to the intermediate node, which is configured to provide a first bias current which allows the differential current to vary within a predetermined range. The amplifying circuit further comprises an output terminal coupled to the intermediate node, and a second current source coupled to the intermediate node and configured to provide a second bias current. The second bias current compensates the differential current and the first bias current and produces an output current flowing through the output terminal in a predetermined direction. A measurement device is also described.

Abstract: The current sensing circuit comprises a first input terminal and a second input terminal for introducing a subject current that flows in a current path; a shunt resistor coupled in the current path for converting the subject current into an output voltage difference across the shunt resistor; an amplifier having a first input node coupled to the first input terminal, a second input node coupled to the second input terminal, an output node, and a feedback path comprising an over-current protection device, wherein the feedback path is coupled between the output node and the first input terminal; and an output terminal coupled to the second input terminal and the shunt resistor to output the output voltage difference. The current sensing circuit has a relatively large current measuring range and a small burden voltage. A measurement device is also described.

Abstract: The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.

Abstract: One embodiment includes a method for protecting from the accidental application of an electrical potential to an incorrect pin of a multipin electrical connector during testing. A sleeve is fitted around a pin that is not to have potential applied to it such that the pin is protected from accidental application of potential during testing.

Abstract: An integrated circuit test socket includes a highly conductive compliant material that is cut and installed into the test socket. The conductive material draws electrical charge away from the test socket, leading to more accurate testing. The test socket base is grounded, and a ground current runs through the base and into conductive strips. The configuration forms an electromagnetic impulse shield, protecting the chip from electromagnetic interference. The compliance of the shield material allows the shield to be sealed when activated, ensuring that the electromagnetic impulse shield is complete around the semi-conductor chip.

Abstract: An inspection apparatus capable of reducing the effect of noises is provided. An inspection apparatus according to the present invention includes a work table 26 on which an object, a fixed body 28 disposed above the work table 26, a probe assembly that holds a probe stylus 38a, a support base member 40 supported on the fixed body 28, a suspension mechanism 46 that supports the probe assembly 38 above the work table 26, and a signal circuit substrate 54 including therein an IC chip 54a that generates an inspection signal supplied to the probe stylus 38a, the signal circuit substrate 54 being supported by the suspension mechanism 46 below the suspension mechanism 46, in which the probe assembly 38 and the support base member 40 are electrically isolated from each other.

Abstract: A probe apparatus 10 that maintains a contact state between each of probes 15 of a probe card 17 and each of corresponding electrodes of semiconductor devices formed on a wafer W by maintaining a decompressed state of a sealed space S between the wafer W and the probe card 17 includes an ejector 23 configured to decompress the sealed space S. Further, the ejector 23 includes a suction port 29; a decompression chamber 31 communicating with the suction port 29; an exhaust port 34 communicating with the decompression chamber 31; and a nozzle 32 through which air is discharged toward the decompression chamber 31 at a high velocity. Furthermore, the nozzle 32 is configured to directly confront the exhaust port 34, and the suction port 29 communicates with the sealed space S.

Abstract: The present invention relates to a probe apparatus for testing the quality of semiconductor chips, wherein the probe apparatus for testing chips has superior reliability and durability. The probe apparatus of the present invention comprises: a printed circuit board having a center with a through-hole; a pin holder which is attached to the front surface of the printed circuit board and which has a plurality of pinholes; a plurality of probe pins, each of which has an L-shape with a horizontal end connected to one side end of a circuit pattern formed on the printed circuit board, and a vertical end exposed outwardly from the upper surface of the pinhole; and a back cover attached to the back surface of the printed circuit board.

Abstract: The invention relates to a cable interface (1) for operatively connecting a plurality of coaxial cables (11). A main body (2) has a first side face and an opposing second side face (3, 4) with a plurality of blind holes (5) arranged in a pattern in the first side face (3). An internal conductor opening (7) is formed at the bottom (6) of each blind hole (5) and arranged substantially coaxial with the blind hole (5), which is likewise coated with an electrically conductive material and is used for operatively connecting an internal conductor (17) of the coaxial cable (11). The blind holes (5) cooperate with at least one first bore (8), which extends from the second side face (4) into the main body (2) and is coated with an electrically conductive material.

Abstract: A test carrier includes a base member that holds a die and a cover member. The base member includes a board having a wiring line that is electrically connected to the die. The wiring line includes a wiring line and a resistive portion having a resistance value that is higher than the resistance value of the wiring line.

Abstract: An electronic device testing apparatus includes a housing unit which disassembles an empty test carrier and assembles the test carrier while housing an untested die in the test carrier, a test unit which tests the die housed in the test carrier, and a retrieving unit which disassembles the test carrier, retrieves the tested die from the test carrier, and reassembles the empty test carrier.

Abstract: A test carrier includes a base member and a cover member. The base member includes a multi-layer board including a wiring line that is electrically connected to a die and a base film that supports the multi-layer board. The cover member includes a frame-shaped cover frame having an opening formed therein. The size of the multi-layer board is larger than the size of the die and is smaller than the size of the opening in a direction along a surface that is opposite to the die.

Abstract: A testing assembly for testing a plurality of semiconductor devices comprising a carrier assembly adapted to hold the plurality of semiconductor devices at predetermined locations therein that is operably connectable with a plurality of different socket assemblies. A universal socket assembly is also described.

Abstract: A method of testing semiconductor devices includes placing a plurality of semiconductor devices in a carrier assembly and performing at least one testing operation on the plurality of semiconductor devices while they remain inside the carrier assembly.

Abstract: Provided is an electrical test socket that is arranged between a terminal of a test target device and a pad of test equipment in order to electrically connect the terminal and the pad, the electrical test socket including: a socket body including a central hole at a center thereof in order to house the test target device inside; a pin connection member comprising a plurality of conductive pins that are arranged on locations corresponding to the terminal of the test target device housed in the central hole of the socket body, and whose upper end contacts the terminal of the test target device, and a housing having penetration holes into which the conductive pins are inserted to support the conductive pins; and a sheet-type connection member in which a plurality of conductive parts are arranged on locations corresponding to the conductive pins, wherein the plurality of conductive parts are arranged on a bottom portion of the pin connection member, exhibit conductivity only in a thickness direction, and are elas

Abstract: A wafer probing system includes a plurality of contacting pins connected to a test head. The system further includes a probe card electrically connectable with the test head, where the probe card includes a circuit board having a plurality of contact pads on opposite sides of the circuit board.

Abstract: Methods and structures for extracting at least one electric parametric value from a back contact solar cell having dual level metallization are provided.

Abstract: The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.

Abstract: An adjustable resistor device includes a first pin, a second pin, a resistance-adjusting branch circuit, and a resistance display circuit. The first and second pins are configured to connect to an external circuit. The resistance-adjusting branch circuit is connected between the first pin and the second pin, and provides resistors for testing the external circuit. The resistance display circuit displays a resistance of the resistance display circuit.

Abstract: A device for detecting a fault attack, including: a circuit for detecting an interruption of a power supply; a circuit for comparing the duration of said interruption with a first threshold; and a counter of the number of successive interruptions of the power supply having a duration which does not exceed the first threshold.

Abstract: A system and method for locating inter-turn short circuits or ground faults in a rotor winding of an electrical generator. The method analyzes data from a Recurrent Surge Oscillograph (RSO) test, identifies a spike or anomaly in a reflected RSO signal, determines an elapsed time between a transmitted signal and the anomaly in the reflected signal, calculates a distance along the winding conductor to the inter-turn short circuit or ground fault based on the elapsed time, and uses a geometric model of the winding conductor to identify a location of the fault based on the distance. The location of the inter-turn short circuit or ground fault specifies a coil number, a turn number within the coil and a position within the turn.

Abstract: A method and apparatus are provided for off-line testing of a multi-phase alternating current machine. A method includes determining, at a first rotor position, a physical stator quantity of each stator winding by applying a test signal to each stator winding, and determining a first joint physical stator quantity by summing the determined physical stator quantities of the stator windings. A method includes determining, at a second rotor position, a physical stator quantity of each stator winding by applying a test signal to each stator winding, determining a second joint physical stator quantity by summing the determined physical stator quantities of the stator windings, comparing the second joint physical stator quantity with a previously determined first joint physical stator quantity, and determining a fault condition of said multi-phase alternating current machine if the first joint physical stator quantity differs from the second joint physical stator quantity.

Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.

Abstract: A locking system for an integrated circuit (IC) chip can include an arrangement of one or more antifuse devices in a signal path of the IC chip. The antifuse devices can be configured to operate in a first state, corresponding to a normally open switch, to inhibit normal operation of the IC chip, and to transition from the first state to a permanent second state, corresponding to a closed switch, in response to a program signal applied to at least one terminal of the IC chip to enable the normal operation of the IC chip.

Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit.

Abstract: An antifuse apparatus can include a cantilever extending from a first electrode portion to terminate in a distal end. A second electrode portion can be spaced apart from the cantilever by an air gap. In response to a program voltage across the first and second electrode portions, the cantilever can be adapted to move from an unprogrammed condition, corresponding to an open circuit condition where the cantilever is spaced apart from the second electrode portion, to at least one permanent programmed condition, corresponding to a short circuit condition between the first and second electrode portions where the cantilever engages the second electrode portion.

Abstract: An output driver circuit may include a electrically conductive medium, an output logic inverter having a first switch adapted to couple a first positive supply voltage to the electrically conductive medium and a second switch adapted to couple a ground supply voltage to the conductive medium. A first biasing network includes a first input that is coupled to the conductive medium, a second input that receives a clock signal, and a first output that is adapted to couple a second positive supply voltage to each input of the first and the second switch. Based on the second switch coupling the conductive medium to the ground supply voltage and the received clock signal generating a logic low, the biasing network reverse biases the first switch by coupling the second positive supply voltage to the respective input of the first switch causing a leakage current reduction in the first switch.

Abstract: A high voltage input/output (IO) circuit designed using low voltage devices. The IO circuit receives a first bias voltage and a second bias voltage. The IO circuit includes a pre-reverse switch, a main-driver and a post-reverse switch. The pre-reverse switch includes a first capacitor and a second capacitor. The main-driver includes a first parasitic capacitance and a second parasitic capacitance. The post-reverse switch includes a third capacitor and a fourth capacitor. The first capacitor and the third capacitor counter an effect of coupling by the first parasitic capacitance on the first bias voltage and the second capacitor and the fourth capacitor counter an effect of coupling by the second parasitic capacitance on the second bias voltage.

Abstract: An encoder is configured for detection of rotational movement of a rotatable shaft in relation to a part of a machine, and a method is provided for generating a reference signal by an encoder.

Abstract: A sampling device comprising a first input port and a second input port, wherein an input-signal is fed to the first input port and wherein an optical clock signal is fed to the second input port. The sampling device comprises a plurality of track and hold units, wherein each of the plurality of track and hold units is connected to the first input port. The plurality of the track and hold units is further connected to the second input port through an optical waveguide in such a manner that the plurality of tack and hold units operate in a time-interleaved mode.

Abstract: An electronic device for compensating for process variation is provided. The electronic device includes a first circuit configured to consume a current supplied to the first circuit, and a second circuit configured to control the current supplied to the first circuit. The second circuit is configured to generate a signal for controlling the current supplied to the circuit based on a frequency of a pulse signal generated using a second component that is of a same kind as a first component of the first circuit.

Abstract: A high voltage semiconductor device, particularly a device including a number of high breakdown voltage transistors having a common drain, first well, and insulating structure between the gate and the drain as well as method for using the same is provided in this disclosure. The high breakdown voltage transistors in the device together are in an elliptical shape. A second well region, gate structure, and a source region are partially overlapping discontinuous elliptical rings having at least two discontinuities or openings in a top view. The respective discontinuities or openings define each of the high breakdown voltage transistors.

Abstract: A main rectifying/smoothing circuit is connected to one end of a secondary winding of a transformer and a plurality of rectifying/smoothing circuits are connected to a plurality of central taps of the secondary winding. The rectifying/smoothing circuits are each equipped with a switch. In a preliminary driving period, a DSP, which controls the switches, reads forward drop voltages of first to third diode loads and sets feedback gains corresponding to the forward drop voltages. The DSP controls the switches based on the set feedback gains and begins rated driving.

Abstract: Frequency multipliers include a pair of transistors each connected to a common impedance through a respective collector impedance formed from a transmission line. Each transmission line has a length between about one quarter and about one eighth of a wavelength of an input signal frequency and is tuned to produce a large impedance at a collector of the respective transistor at the input signal frequency. The output frequency between the collector impedances and the common impedance is an even integer multiple of the input frequency.

Abstract: An apparatus comprises a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal. The apparatus also comprises a digital loop filter configured to generate a fine tuning signal based on the phase difference signal. The apparatus further comprises a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal. The apparatus additionally comprises a divider configured to generate a divider frequency based on a divider control signal and the output signal. The phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal.

Abstract: A method and apparatus is provided for outputting a reset signal during power-up until two conditions are satisfied. In one embodiment, the method and apparatus includes a voltage detector that provides a first output (“VO1”) when an output voltage of a regulator (“VREG”) exceeds a threshold voltage, thereby satisfying a first condition, a comparator receiving a first input voltage and a second input voltage, the comparator providing a second output (“VO2”) when the first input voltage exceeds the second input voltage, thereby satisfying a second condition, and a release circuit that outputs the reset signal unless the voltage detector provides VO1 while the comparator provides VO2.

Abstract: A timing adjustment circuit includes a voltage-controlled delay line, a phase detector, a control voltage generation circuit, and a startup circuit. The voltage-controlled delay line receives an input clock signal and generates multi-phase clocks, a delay amount of each of the multi-phase clocks is changed according to a control voltage. The phase detector detects a phase difference between a first clock and a second clock, the first clock is a reference, the second clock is generated from the voltage-controlled delay line. The control voltage generation circuit generates the control voltage on the basis of the detected phase difference. The startup circuit operates for a certain period after activation, and continuously changes the control voltage between a first voltage and a second voltage.

Abstract: Locked state detection circuits, devices, systems, and methods for detecting a locked or synchronized state of a clock synchronization circuit are described. Detection of a locked state includes a circuit including a phase detector configured to generate a delay adjustment signal in response to comparison of a forward path signal indicative of an external clock signal and a feedback path signal indicative of an output clock signal. The circuit further includes a trend detector operably coupled to the delay adjustment signal and configured to generate a locked signal indicative of an in-phase steady-state between the external clock signal and the output clock signal.

Abstract: A voltage controlled oscillator (VCO) includes a sensing circuit, where the sensing circuit is configured to generate a plurality of compensation control signals. The VCO further includes a voltage-to-current converter comprising a plurality of current sources which are configured to generate a current signal in response to the plurality of compensation control signals. Additionally, the VCO includes a plurality of switching circuits, each of the plurality of switching circuits being configured to selectively enable or disable a corresponding one of the plurality of current sources in response to a corresponding one of the plurality of compensation control signals. Furthermore, the VCO includes a current controlled oscillator configured to generate an oscillating signal in response to the current signal.