Abstract: A lighting and/or signaling device and a light ray guide (N) formed by a guide plate comprising a light entry face, a light exit face and a reflection face having an elliptical profile toward the rear adapted to assure reflection of light rays entering the guide plate through the light entry face toward a focus point (F) located at the level of the light exit face of the guide plate.

Abstract: A display device includes a display element, a planar light source device disposed on an opposite side of a display surface of the display element, a protective plate disposed on a display surface side of the display element, and a black frame member covering a peripheral edge part on a front surface of the protective plate, sandwiching the protective plate from both sides in a thickness direction, and having a decorated front surface.

Abstract: An LED light device with special effects utilizes persistence of vision theory to cause an LED(s) or LED array to change faster than the human eye response time of 1/16 to 1/24 second to display a special message, time, drawing, light patterns, or color changes. In addition, the light device may be provided with a sealed-unit arranged to receive a variety of eye-catching shades.

Abstract: A solid state lamp, such as one that can replace an incandescent light bulb, has a base portion having an electrical connector for connection to a source of power, such as an Edison-type connector for connection to the mains voltage. An AC/DC converter in the base converts the mains voltage to a suitable light emitting diode (LED) drive voltage. A plurality of receptacles on the base connects to electrodes of plug-in modules. Each plug-in module supports a plurality of low power LEDs connected in series. The strings of LEDs on different modules are connected in parallel when connected to the receptacles. The modules and base are configured to allow a user to operate the lamp with different combinations of modules to generate a desired light output from the lamp. For example, the user can recreate the lumens equivalent of a 20W, 40W, or 60W bulb by using one, two, or three modules.

Abstract: A power conversion system is presented. The system includes a power source coupled to a power converter and a controller. The controller is configured to determine a value of at least one parameter corresponding to the power source. Additionally, the controller is configured to provide a first portion of the at least one parameter to the power converter and modify an operating frequency of the power converter, duty ratio of the power converter, or a combination thereof. Furthermore, the controller is configured to obtain an electrical quantity at an output of the power converter based on the modified operating frequency, the modified duty ratio, or a combination thereof. Also, the controller is configured to deliver a combination of the electrical quantity obtained at the output of the power converter and a second portion of the at least one parameter to a load. Method for converting power is also presented.

Abstract: An apparatus comprises a bridge coupled between a bias voltage and ground, wherein the bridge comprises a first switch and a second switch connected in series and coupled between the bias voltage and ground and a third switch and a fourth switch connected in series and coupled between the bias voltage and ground, a resonant device coupled to the bridge, wherein the resonant device comprises a fixed capacitance, a gate capacitance and a magnetizing inductance, a transformer coupled to the resonant device, wherein the transformer comprises a primary winding and a plurality of secondary windings.

Abstract: The invention discloses a bidirectional dc-dc converter system and circuit thereof. In boost mode, topology is combined with interleaved two-phase boost converter for providing a higher step-up voltage gain. In buck mode, topology is combined with interleaved two-phase buck converter in order to get a higher step-down conversion ratio. The main objectives of the invention are aimed to both store energy in the blocking capacitors (C1&C2) for increasing voltage conversion ratio and reduce voltage stresses of active switches simultaneously. As a result, the invention topology possesses a nice low switch voltage stress characteristic. This will allow one to choose lower voltage rating MOSFETs to reduce both switching and conduction losses, and overall efficiency can be enhanced. In addition, due to charge balance of the blocking capacitor, the converter features both automatic uniform current sharing characteristic of interleaved phases and without adding extra circuitry or using complex control methods.

Abstract: Disclosed is an apparatus for supplying power to a device. The apparatus includes a transformer configured to output a predetermined voltage to a device varying in load; a switch configured to switch on and off the voltage output from the transformer in accordance with pulse width modulation (PWM) signals; a PWM signal supplier configured to supply the PWM signal to the switch; a feedback circuit which detects the output from the transformer and applies a control signal to the PWM signal supplier; and an output voltage controller which detects a load current of the device, and adjusts the control signal of the feedback circuit by adjusting the output detected by the feedback circuit in accordance with the detected load current.

Abstract: Disclosed are an electronic apparatus and a power controlling method thereof, the electronic apparatus including a system portion configured to operate with a received voltage, and a power supply including a pulse width modulation (PWM) generator to generate a PWM signal, a converter to transfer voltage from a primary side to a secondary side in accordance with an output voltage of the PWM generator, and an output portion to supply voltage at the secondary side as standby voltage to the system portion, the PWM generator receives feedback on the standby voltage at the secondary side of the converter, the PWM signal is turned on/off in accordance with levels of the standby voltage at the secondary side, and voltage being supplied to components, except, when the PWM signal is turned off, voltage at the secondary side is only supplied to a component that monitors the feedback of the standby voltage.

Abstract: A multiple output DC-DC converter comprises a transformer, a primary circuit, a plurality of secondary circuits, and a controller. The transformer has a primary and at least one secondary winding. The primary circuit connects to a DC power supply source and includes the primary winding of the transformer and a primary switch connected in series. The plurality of secondary circuits includes the at least one secondary winding of the transformer, wherein each secondary circuit provides a DC power supply output, and at least one of the secondary circuits has a secondary switch. The controller monitors an output signal of each secondary circuit and controls operation of the primary and secondary switches based on the monitored signals. The controller co-ordinates operation of the secondary switch with the primary switch, such that the primary switch and the secondary switch are switched on simultaneously, or with a controlled offset.

Abstract: Provided is a switching power supply apparatus that shifts to an OFF mode when electronic equipment is on standby, and includes: an OFF mode delay circuit that delays shifting to the OFF mode; and an electric storage unit and a power supply circuit that function as a power supply source of an OFF mode control circuit. With the configuration, the power consumption can almost be eliminated, and the switching power supply apparatus can start without any charge in an electricity storage component such as a primary battery or a secondary battery.

Abstract: A power supply circuit includes: an environment detecting circuit which detects an installation environment; and a voltage control circuit which makes a report of a power supply capability by performing fluctuation control of an output voltage in response to detection information of the environment detecting circuit.

Abstract: This disclosure provides control techniques for a resonant converter. In one control technique, for switching speeds that are below the resonant frequency of the primary stage of the converter, the switches of the synchronous rectifier (SR) portion (SR switches) of the resonant converter are controlled based on a rising edge of the corresponding primary side switch and the turn off time of a corresponding SR switch. In general, for below resonance operation, each corresponding SR switch will be turned off prior to the falling edge of each corresponding primary side switch, while each corresponding SR switch will be turned on at the rising edge of the each corresponding primary side switch. The conduction time of respective SR switches is generally constant for below resonance operation.

Abstract: A method of driving an isolated converter includes opening a first bi-directional switch on an input side of a transformer, accepting current into a resonant capacitor connected across the first bi-directional switch to reduce voltage across the first bi-directional switch in response to said opening the first bi-directional switch, reversing current out of the resonant capacitor, and closing the first bi-directional switch as voltage across the first bi-directional switch is approximately zero volts.

Abstract: An isolated power conversion apparatus has an isolation transformer, a series circuit including a load and an inductor connected in series with each other, the series circuit being disposed on a secondary side of the isolation transformer, and one or a plurality of switching means disposed between the series circuit and the secondary side of the isolation transformer, the switching means being bidirectional. This apparatus sends out power from a DC power supply of a primary side of the isolation transformer toward the load as DC power or AC power of an arbitrary polarity, or regenerates and supplies the DC power or AC power from the load to the DC power supply.

Abstract: An isolated power conversion apparatus has an isolation transformer, a series circuit including a load and an inductor connected in series with each other, the series circuit being disposed on a secondary side of the isolation transformer, and one or a plurality of switching means disposed between the series circuit and the secondary side of the isolation transformer, the switching means being bidirectional. This apparatus sends out power from a DC power supply of a primary side of the isolation transformer toward the load as DC power or AC power of an arbitrary polarity, or regenerates and supplies the DC power or AC power from the load to the DC power supply.

Abstract: A power supply device may include a transformer having a primary winding receiving a rectified alternating current (AC) input power and a secondary winding electromagnetically coupled to the primary winding to supply power to a load, an auxiliary switch selectively providing the rectified AC input power to the primary winding, and a limitation controlling unit controlling the auxiliary switch based on a voltage level of the AC input power.

Abstract: A converter and a driving method thereof are disclosed. The converter includes a transformer, a main switch, a clamp switch, and a switching controller. Here, the switching controller controls a turn-on time of the main switch and a turn-off time of the clamp switch corresponding to an output load.

Abstract: An exemplary Multi-Terminal High Voltage Direct Current (MTDC) system includes at least three terminals, where each terminal including a Voltage Source Converter (VSC) controlled by a VSC controller. A method for controlling the MTDC system includes providing a converter schedule including at least one of a desired power flow value and a DC voltage; determining, by a MTDC master controller, a present state of the MTDC system including a dynamic topology of the MTDC system; determining, by the MTDC master controller, based on the present state of the MTDC system, based on the schedule and based on MTDC system constraints, VSC controller parameters including droop settings for local control by the VSC controllers; and transmitting the VSC controller parameters to the VSC controllers.

Abstract: A boost PFC converter includes a rectifier, a converter and an output stage comprising an output capacitor where the DC output voltage is provided across the output capacitor. The rectifier includes four rectifying elements connected in a full bridge configuration where the upper two of these four rectifying elements are thyristors and where the lower two are diodes. In that the thyristors are controlled such as to be open for only a part of each half period of the input voltage, the amount of current per half period that is passed to the output capacitor is controllable and can be made very small. Accordingly, the charge current for precharging the output capacitor can be controllably limited such that a bulky precharge resistor is not required anymore to avoid high inrush currents.

Abstract: A boost circuit includes a power rail to provide a supply voltage, a switch transistor controlling output of a boosted signal from a source of the switch transistor, and a timing and voltage control circuit configured to generate an equalization (EQ) signal to be applied to a gate of the switch transistor. The EQ waveform has a level being an EQ high level, an EQ low level lower than the EQ high level, or an EQ clamped level between the EQ low level and the EQ high level.

Abstract: The present disclosure discloses a method and an apparatus implementing the method for minimising a circulating current of parallel-connected inverters. The method can include, for at least one parallel-connected inverter, measuring a common-mode voltage of the inverter, and controlling a cycle length of the switching cycle on the basis of the common-mode voltage.

Abstract: A method including: setting a weighting function based on an amount of change in impedance of a control target; and determining, for a power controller, a transfer function composed of a transfer function of an internal model obtainable by performing Laplace transform on the voltage reference value and a transfer function of a partial controller, the transfer function of the partial controller being for outputting the control output after receiving, as an input, an output of the transfer function of the internal model, wherein the determining includes determining the transfer function of the partial controller using an H?control theory so as to reduce (i) a first amount of control obtainable by multiplying the control output and the weighting function and (ii) a second amount of control that is an output of the transfer function of the internal model.

Abstract: The invention relates to a H-bridge inverter and a method for controlling a H-bridge converter. The H-bridge inverter (1) comprises first and second DC terminals (Tdc1, Tdc2), first and second AC terminals (Tac1, Tac2), a first switch (S1), a second switch (S2), a third switch (S3) and a fourth switch (S4). The inverter further comprises a control circuit for controlling the switching of the first, second, third and fourth switches (S11, S2, S3, S4).

Abstract: A reversible matrix converter circuit is provided with n levels per phase including n conversion arms exhibiting on one side n ends for generating or receiving respectively n intermediate DC voltage levels, and exhibiting on another side n ends linked at a common point of AC signal input or output. The circuit includes: —two external arms linked respectively to the highest level of positive voltage and to the lowest level of negative voltage, these two external arms each having a single IGBT transistor or two power transistors, linked by their emitter, —two IGBT power transistors, linked in series by their emitter on each of the n-1 internal arms, —filtering capacitors disposed respectively between the n intermediate voltage levels.

Abstract: A system including a multi-level power converter is provided. The system also includes a plurality of DC link capacitors and a balancing circuit coupled to the multi-level power converter. The balancing circuit further includes two sets of interface branches. Each set includes a plurality of interface branches and a plurality of switching elements. The balancing circuit also includes a battery coupled to one or more inductors across the two sets of interface branches and a controller for controlling switching operations of the plurality of switching elements for modifying a voltage of the battery to balance voltages of the plurality of DC link capacitors.

Abstract: This description relates to an electrical power converter including a series connection of two transistors, and provides a technology for suppressing increase in electrical current flowing through the transistors when the two transistors are turned on at the same time for some defective reason. An electrical power converter disclosed herein includes a series connection of a first transistor and a second transistor. The electrical power converter includes a clamp circuit configured to inhibit an abnormal rise in gate voltage, which is provided in at least either the first transistor or the second transistor. The clamp circuit includes a diode and a capacitor. The diode has an anode connected with a gate of the transistor. The capacitor has one electrode connected with a cathode of the diode and the other electrode connected with an emitter of the transistor.

Abstract: A method comprises: applying control signals to an inverter switching network according to a selected switching sequence, wherein a switching sequence is applied corresponding to a desired sector of a switching scheme in which a demand vector is currently located, the switching scheme corresponding to the demand vector in a space vector modulation scheme having stationary active vectors around the periphery and a stationary zero vector at an origin; storing a plurality of simultaneous switching schemes in which, for a single switching cycle, a switch in each of at least two phases of the inverter switching network is switched simultaneously from a first state to a second state with a corresponding switch in at least one other phase of the inverter switching network being in a given state and in which the switch in each of the at least two phases is switched simultaneously from the second state to the first state with the switch in the at least one other phase being in the given state; and applying a simultane

Abstract: A method is disclosed for controlling at least four switching components of a multi-level converter. The method comprises receiving first and second control signals for controlling a dual-level inverter having two switching components, and processing the first and second received control signals to produce at least four switching component control signals for controlling the switching components of a multi-level converter. Also disclosed are a control logic system, a multi-level converter system and a computer readable medium.

Abstract: According to one embodiment, a power supply device includes a main circuit board including a switching circuit, a transformer board opposite the main circuit board and including a transformer, and an intermediate cooling plate between the main circuit board and the transformer board and configured to cool at least one of a heat-producing element of the switching circuit and the transformer.

Abstract: According to one embodiment, an AC-DC converter includes a first printed wiring board, a planar transformer, a plurality of primary members, and a plurality of secondary members. The planar transformer has a primary coil, a secondary coil, a second printed wiring board and a core. The primary members are mounted on the first printed wiring board, and are electrically connected to the primary coil. The secondary members are mounted on the second printed wiring board, and are electrically connected to the secondary coil.

Abstract: An associative memory circuit including a first memristor, a second memristor, a fixed value resistor R, and an operational comparator. One terminal of the first memristor is a first input terminal of the associative memory circuit, and the other terminal of the first memristor is connected to a first input terminal of the operational comparator. One terminal of the second memristor is a second input terminal of the associative memory circuit, and the other terminal of the second memristor is connected to the first input terminal of the operational comparator. One terminal of the fixed value resistor is connected to the first input terminal of the operational comparator, and the other terminal of the fixed value resistor is connected to the ground. A second input terminal of the operational comparator is connected to a reference voltage.

Abstract: A method by which a defective memory cell can be efficiently excluded from a memory cell array is provided. In one embodiment, the memory cell array includes M word lines and (N+K) bit lines. K of the bit lines are spares (i.e., redundant bit lines). Programmable switches in a switch array are programmed so that the switch array connects a driver that drives the bit lines to N bit lines that are not connected to defective memory cells. The memory cell array is tested by a test circuit connected to the bit lines in such a manner that the test circuit transmits and receives a signal to and from the bit lines via the switch array. The test circuit may be formed using a reconfigurable circuit. Other embodiments may be claimed.

Abstract: Provided is a semiconductor device capable of increasing the number of signals. A semiconductor device according to an embodiment of the invention includes memories; a controller that designates addresses of the memories; amounting board having lines formed thereon, the lines connecting the controller with the memories; and a first ball group that connects the controller with the lines of the mounting board. A plurality of address lines formed on the mounting board includes an address line formed of a front surface wiring layer, and an address line formed of a back surface wiring layer. In each of the front surface wiring layer and the back surface wiring layer, each of the address lines from first balls of the first ball group is routed in order from a first memory to a fourth memory.

Abstract: This semiconductor device is provided with: a variable resistance first switch (103), which has a first terminal and a second terminal, and which has the resistance value thereof varied when an applied voltage exceeds a reference value; a variable resistance second switch (104), which has a third terminal and a fourth terminal, and which forms an intermediate node (105) by having the third terminal connected to the second terminal, and has the resistance state thereof varied when an applied voltage exceeds a reference value; first wiring (101) connected to the first terminal; second wiring (102), which is connected to the fourth terminal, and which extends in the direction intersecting the first wiring (101) in a planar view; a first selection switch element (106) connected to the first wiring (101); and a second selection switch element (107) connected to the second wiring (102).

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

Abstract: Vertical 1T-1R memory cells, memory arrays of vertical 1T-1R memory calls, and methods of forming such memory cells and memory arrays are described. The memory cells each include a vertical transistor and a resistivity-switching element coupled in series with and disposed above or below the vertical transistor. The vertical transistor includes a controlling electrode coupled to a word line that is above or below the vertical transistor. The controlling electrode is disposed on a sidewall of the vertical transistor. Each vertical transistor includes a first terminal coupled to a bit line, a second terminal comprising the controlling electrode coupled to a word line, and a third terminal coupled to the resistivity-switching element.

Abstract: A device includes a storage region, and a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array is disclosed herein. The storage region includes a first storage array and a second storage array. The first storage array includes a plurality of first storage cells. The second storage array includes a plurality of second storage cells. The second storage cells are configured to be in place of the first storage cells. The RRAM-based non-volatile storage array is configured to record at least one corresponding relationship between the first storage cells and the second storage cells.

Abstract: Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor. Examples of multiple cell devices include phase change memory devices with multiple cells associated with each access transistor.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.

Abstract: A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element.

Abstract: Among other things, one or more techniques or systems for facilitating access operations to a single port memory device are provided. Multiple access operations to a single port memory device, such as a 6 transistor bitcell array of an SPSRAM, are performed during a single clock period of a system clock. In an embodiment, a wrapper controller initiates a first access operation during a first clock period of the system clock based upon a rising edge of the system clock. Responsive to receiving an operation complete signal during the first clock operation, the wrapper controller initiates a second access operation to the single port memory device during the first clock period. In this way, multi-port access functionality is implemented, such as in a serial manner to mitigate operation disturbs, for a single port memory device that occupies a relatively smaller area than a multi-port memory device for improved storage density.

Abstract: A voltage controller is provided that is connected to a voltage inducing circuit which is connected to a static random-access memory (SRAM) cell. The voltage controller comprises a voltage clamping circuit and a pull up circuit. The voltage clamping circuit comprises one or more transistors. The voltage clamping circuit is configured to inhibit a second voltage of a second signal at a second node of the voltage inducing circuit from exceeding a first specified voltage threshold so that a fifth voltage of a fifth signal at a fifth node of the voltage inducing circuit is inhibited from exceeding a second specified voltage threshold. The pull up circuit is configured to maintain the second voltage substantially equal to a specified pull up voltage. The fifth node is connected to the SRAM cell, and a voltage to which the SRAM cell is exposed is thereby controlled.

Abstract: A normally-off state of an OS transistor is maintained or an on-state current thereof is increased without additionally generating a positive potential or a negative potential. When data is written to a node connecting an OS transistor and a capacitor, a potential supplied to the other side of the capacitor is set to an L level, and when the data is retained, the potential is switched from the L level to an H level. In addition, a power switch for a volatile memory circuit is provided on a low power supply potential side so that the supply of a power supply voltage can be stopped. Accordingly, at the time of data retention, a source and a drain of the OS transistor can be set at a high potential, whereby the normally-off state can be maintained and the on-state current can be increased.

Abstract: A method and circuit for implementing sense amplifiers for sensing local write driver with bootstrap write assist for Static Random Access Memory (SRAM) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a sense amplifier used in both read and write operations with a write assist boost circuitry. The sense amplifier captures and amplifies write data at a selected SRAM cell column and drives the write data onto local bit lines. The write assist boost circuitry temporarily supplies an increased device voltage differential to the SRAM cell during write operations to significantly increase SRAM cell write ability.

Abstract: A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the voltage-controlled MTJ is programmed to a desired state and if not, changing the Vp and repeating the applying and reading steps until the voltage-controlled MTJ is programmed to the desired state.

Abstract: The present invention is directed to a method for reading and writing an STT-MRAM multi-level cell (MLC), which includes a plurality of memory elements coupled in series. The method detects the resistance states of individual memory elements in an MLC by sequentially writing at least one of the plurality of memory element to the low resistance state in order of ascending write current threshold. If a written element switches the resistance state thereof after the write step, then the written element was in the high resistance state prior to the write step. Otherwise, the written element was in the low resistance state prior to the write step. The switching of the resistance state can be ascertained by comparing the resistance or voltage values of the plurality of memory elements before and after writing each of the plurality of memory elements in accordance with the embodiments of the present invention.

Abstract: Provided are a magnetic resistance structure, a method of manufacturing the magnetic resistance structure, and an electronic device including the magnetic resistance structure. The method of manufacturing the magnetic resistance structure includes forming a hexagonal boron nitride layer, forming a graphene layer on the boron nitride layer, forming a first magnetic material layer between the boron nitride layer and the graphene layer according to an intercalation process; and forming a second magnetic material layer on the graphene layer.

Abstract: A memory controller has a bit line driver configured to supply a selected bit line voltage to a selected bit line and an unselected bit line voltage to an unselected bit line. The selected bit line is coupled to a selected memory cell, and the unselected bit line is coupled to an unselected memory cell. The memory controller further has a word line driver configured to supply a selected word line voltage to a selected word line and an unselected word line voltage to an unselected word line. The selected word line is coupled to the selected memory cell, and the unselected word line is coupled to the unselected memory cell. The unselected bit line voltage is equal to or higher than a difference between the unselected word line voltage and a threshold voltage of the unselected memory cell.

Abstract: In a data storage system having multi-level memory cells, a counter tracks the number of program/erase cycles, anticipated read cycles, or anticipated length of data retention of a cell. When a threshold number of cycles is reached or length of retention or read frequency are anticipated, the cell is programmed using more program voltage pulses, narrower program voltage pulses or some other modification to the incremental step programming pulse to reduce the range where the intermediate least significant (lower) bit read voltage may be erroneous, thereby reducing the probability of write errors when the most significant page (upper) is programmed.