Abstract: Systems and methods may provide for monitoring one or more runtime performance characteristics of a link and determining a state of the link based on at least one of the one or more runtime performance characteristics. Additionally, a retraining of the link may be automatically scheduled based on the state of the link. In one example, scheduling the retraining of the link further includes setting one or more retraining parameters.

Abstract: The disclosure generally describes computer-implemented methods, software, and systems, including methods for generating visualizations. On a client side, a user request is received for an inter-entity call visualization. Code analysis data is accessed. A visualization model is built. The visualization is shown. User inputs are received for interacting with the visualization. The visualization is updated based on the received user inputs. On a server side, a request is received for code analysis data. The requested data collected, including running analyzers for any available data. The requested data is sent. The code analysis data can be used for other purposes than visualizations.

Abstract: Pre-silicon fairness evaluation to detect fairness issues pre-silicon. Drivers drive a plurality of commands on one or more interfaces of a device under test to test the device under test. State associated with the device under test is checked. Based on the state, a determination is made as to whether the drivers are to continue driving commands against the device under test. Based on determining that the drivers are to continue driving the commands, a further determination is made as to whether a predefined limit has been reached. Based on determining the predefined limit has been reached, ending the test of the device under test in which the test fails.

Abstract: The disclosure generally describes computer-implemented methods, software, and systems for presenting error information. Logs are received from different locations, the logs associated with a plurality of builds at the different locations and associated with one or more systems. The logs are stored in a centralized location. Build information is generated for a given build, including identifying errors associated with the given build. Information for a current log associated with the given build is analyzed, including accessing information for previous logs associated with previous related builds related to the given build. Based on the analyzing, error diagnostic information that is to be presented is determined, including an analysis of errors that occurred in the given build and previous related builds. Instructions are provided, the instructions operable to present the error diagnostic information to a user, including providing log information, for presentation in a user interface.

Abstract: Systems and methods are provided to test changes for a mobile app built by web-based tooling directly on a physical mobile device. A first application can be loaded on a mobile device. The first application can receive metadata of a second application. The first application can execute the second application using the metadata. Access to local resources can be intercepted and redirected to the server for processing. Additionally, changes made to the second application using the web-based tooling can be pushed to the first application using a persistent channel allowing the changes to be immediately tested.

Abstract: A system and method for reviewing of warning generated during static analysis of a clustered software code by identifying, common point warnings and unique warnings from warnings associated with a software code, and further identifying, a top of must overlapped function for each of the common point warnings. Generating, one or more groups of the common point warnings based on the top of must overlapped function, and assigning, the top of must overlapped function as a constraint for corresponding group of common point warnings. Eliminating, warnings from each of the one or more groups using a review output wherein the review output is identified by reviewing a common point warning from the one or more group under the constraint such that the review of the common point warning under the constraint satisfy for review of all remaining for reviews of all remaining common point warnings of the group.

Abstract: Systems and methods may provide for conducting an object trace of an allocation status of one or more objects in a computing system and using one or more hardware performance counters to conduct a hardware based address profiling of the computing system. Additionally, one or more stale objects in the system may be automatically identified based on the object trace and the hardware based address profiling. In one example, the object trace is initiated prior to a start of a task on the computing system and the hardware based address profiling is initiated in response to an end of the task on the computing system.

Abstract: In accordance with an embodiment, described herein is a system and method for dynamic debugging in an application server environment. An exemplary method can provide, at one or more computers, including an application server environment executing thereon, a plurality of deployable resources which can be used within the application server environment, one or more running managed servers, the one or more managed servers being within a domain, and a debug framework, the debug framework comprising a debug patch directory, the debug patch directory containing one or more debug patches. The method can activate a selected debug patch within the domain, the selected debug patch comprising at least one class, the selected debug patch designed to gather information about the problem within the domain. The managed servers, upon activation of the selected debug patch, can remain running. The method can also deactivate the selected debug patch without requiring a restart.

Abstract: A system may include an active first point of deployment (POD) configured to provide a specified business functionality and may include a first server and a first instance of a platform to provide the specified business function. A dark second POD may be configured to include a second server and a second instance of the platform template, where the first platform template instance comprises a different version than the second platform template instance. A POD management computing device may test an operation of the second POD in parallel with the operation of the first POD. The POD management computing device may upgrade the business functionality by deactivating the first POD and activating the second POD to provide the specified business function using the second instance of the platform template.

Abstract: An application programming interface (API) consumption development environment (CDE) is integrated with an API administration component and a determination is made whether an existing API conforms to application development requirements. A desired API is defined including test data, and the desired API and test data is forwarded to an API developer as a development request. The API CDE is integrated with the API administration component. A developed API is deployed to an API provider creating an integration testing deployment, and the API administration component is notified of the integration testing deployment. The developed API is deployed to an API provider productive for productive use.

Abstract: A plurality of processing elements having stream operators and operating on one or more computer processors receive a stream of tuples. A first stream operator adds a first attribute to a tuple received on a first port of the first stream operator. The first attribute indicates the first port and the first stream operator. A second stream operator adds a second attribute to a tuple received on a first port of the second stream operator. The second attribute indicates the first port of the second stream operator and the second stream operator. It is determined whether a debug tuple has been received by a third stream operator. A debug tuple is a tuple that includes the first and second attributes. An operation, such as halting execution or incrementing a count of debug tuples, is performed when it is determined that a debug tuple has been received.

Abstract: A computer-implemented method for automatically identifying a faulty behavior of a control system. The method includes receiving, at a test processor, a description of the faulty behavior. The method also includes selecting, using the test processor, a goal state based on a heuristic decision. The method also includes selecting, using the test processor, a selected system state. The method also includes selecting, using the test processor, a selected variable to the control system based on the goal state. The method also includes loading, from a memory, a control model of the control system. The method also includes performing, using the test processor, a simulation of the control model using the selected variable and the selected system state as parameters of the simulation. The method also includes determining, using the test processor, whether the faulty behavior was observed based on the simulation.

Abstract: Computerized systems and methods facilitate the generation of customized test scripts for testing customized healthcare information technology systems. A number of different test script templates may be provided that each corresponds with a different scenario of use of the healthcare information technology system. A user may select a test script template and modify the test script template to generate a customized test script to meet the unique design and/or patient scenarios for a given installation of a healthcare information technology system. The test script template modification process may include first presenting an outline of the test script template, which the user may choose to modify. A detailed view of the test script template may then be provided that allows the user to view and customize actions and expected results in order to generate the customized test script.

Abstract: For cloud development tools building native mobile applications, it is often useful to test out parts of an application on a physical device. Systems and methods are provide for providing an native application that allows portions of itself to uptake newly developed features allowing rapid testing of these features.

Abstract: Methods and arrangements for testing mobile applications. A mobile application for testing is input at a mobile device. The mobile application is automatically tested using a test script, wherein the testing requires data from an out-of-band channel. The testing includes: invoking a listener module based on the mobile application; using the listener module to automatically obtain data from an out-of-band channel; and communicating the automatically obtained data to the mobile application. Other variants and embodiments are broadly contemplated herein.

Abstract: Techniques and systems for creating a function call graph for a codebase are disclosed. Graph creation includes identifying functions in the codebase by a function signature and representing a function as a first node in the call graph. For that function, identifying call-to functions, call-from functions, and inheritance parents and children, and a base class from the function signature of that function; adding child nodes to the first node based on the identified call-to and call-from functions; for an interface call to a base class method in the function, adding child nodes to the first node based on implementations of an override of the base class method; for an added child node, removing that child node from the first node if a source file that includes an implementation of an override and a source code file that includes the function don't share at least one common binary file.

Abstract: A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.

Abstract: In one embodiment, a method includes maintaining a first open logical erase block for user writes, maintaining a second open logical erase block for relocate writes, wherein the first and second open logical erase blocks are different logical erase blocks, receiving a first data stream having the user writes, transferring the first data stream to the first open logical erase block, receiving a second data stream having the relocate writes, and transferring the second data stream to the second open logical erase block. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: Systems and methods may provide for detecting a pending write operation directed to a target memory region and determining whether the target memory region satisfies a degradation condition in response to the pending write operation. Additionally, the target memory region may be automatically reconfigured as a cold storage region if the target memory region satisfies the degradation condition. In one example, determining whether the target memory region satisfies the degradation condition includes updating the number of write operations directed to the target memory region based on the pending write operation and comparing the number of write operations to an offset value, wherein the degradation condition is satisfied if the number of write operations exceeds the offset value.

Abstract: Methods and apparatuses to control cache line coherency are described. A processor may include a first core having a cache to store a cache line, a second core to send a request for the cache line from the first core, moving logic to cause a move of the cache line between the first core and a memory and to update a tag directory of the move, and cache line coherency logic to create a chain home in the tag directory from the request to cause the cache line to be sent from the tag directory to the second core. A method to control cache line coherency may include creating a chain home in a tag directory from a request for a cache line in a first processor core from a second processor core to cause the cache line to be sent from the tag directory to the second processor core.

Abstract: A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.

Abstract: In an embodiment, a method can include storing a plurality of volumes on persistent media. A set of the volumes can store at least one portion of a same copy of data. The method can further include caching the set of the volumes as a single group. In an embodiment, the plurality of volumes can include at least one of drives, snapshots, clones and replicas.

Abstract: In an embodiment, a processor includes a first domain to operate according to a first clock. The first domain includes a write source, a payload bubble generator first in first out buffer (payload BGF) to store data packets, and write credit logic to maintain a count of write credits. The processor also includes a second domain to operate according to a second clock. When the write source has a data packet to be stored while the second clock is shut down, the write source is to write the data packet to the payload BGF responsive to the count of write credits being at least one, and after the second clock is restarted the second domain is to read the data packet from the payload BGF. Other embodiments are described and claimed.

Abstract: Embodiments relate to cache coherency verification using ordered lists. An aspect includes maintaining a plurality of ordered lists, each ordered list corresponding to a respective thread that is executed by a processor, wherein each ordered list comprises a plurality of atoms, each atom corresponding to a respective operation performed in a cache by the respective thread that corresponds to the ordered list in which the atom is located, wherein the plurality of atoms in an ordered list are ordered based on program order. Another aspect includes determining a state of an atom in an ordered list of the plurality of ordered lists. Another aspect includes comparing the state of the atom in an ordered list to a state of an operation corresponding to the atom in the cache. Yet another aspect includes, based on the comparing, determining that there is a coherency violation in the cache.

Abstract: Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. Each cache is associated with a directory having a number of directory entries and with a side table having a smaller number of entries. The directory entry for a cache line associates the cache line with a tag and a set of full-line descriptive bits. Creating a side table entry for the cache line places the cache line in sub-line coherency mode. The side table entry associates each of the sub-cache line portions of the cache line with a set of sub-line descriptive bits. Removing the side table entry may return the cache line to full-line coherency mode.

Abstract: An electronic system for multiple agents, both coherent and non-coherent, to communicate with a hybrid cache, the hybrid cache to provide functionality associated with a cache for coherent agents in an outer shareable domain, and to provide functionality associated with a cache for non-coherent agents in a system shareable domain, the functionality provided by tag fields in cache lines stored in the hybrid cache. The tag fields are configured to indicate if a cache line of the hybrid cache belongs to at least one of a logical coherent cache or a logical system cache.

Abstract: Caching technologies that employ data compression are described. The technologies of the present disclosure include cache systems, methods, and computer readable media in which data in a cache line is compressed prior to being written to cache memory. In some embodiments the technologies enable a caching controller to understand the degree to which data in a cache line is compressed, prior to writing the compressed data to cache memory. Consequently the cache controller may determine where the compressed data is to be stored in cache memory based at least in part on the size of the compressed data, a compression ratio attributable to the compressed data (or its corresponding input data), or a combination thereof.

Abstract: According to an example, memory traffic including memory access commands is routed between compute nodes and memory nodes in a memory network. Other traffic is also routed in the memory network. The other traffic may include input/output traffic between the compute nodes and peripherals connected to the memory network.

Abstract: In one embodiment, a processor includes: a plurality of cores each to independently execute instructions; a shared cache memory coupled to the plurality of cores and having a plurality of clusters each associated with one or more of the plurality of cores; a plurality of cache activity monitors each associated with one of the plurality of clusters, where each cache activity monitor is to monitor one or more performance metrics of the corresponding cluster and to output cache metric information; a plurality of thermal sensors each associated with one of the plurality of clusters and to output thermal information; and a logic coupled to the plurality of cores to receive the cache metric information from the plurality of cache activity monitors and the thermal information and to schedule one or more threads to a selected core based at least in part on the cache metric information and the thermal information for the cluster associated with the selected core. Other embodiments are described and claimed.

Abstract: In an approach for managing a storage system, distribution of storage volumes among a plurality of storage controller groups may be adjusted dynamically or adaptively based on the current access hot degrees of respective storage volumes in the storage system. In this way, optimized distribution of storage volumes can be achieved without user interference. Such redistribution eliminates the degradation of performance of the storage system.

Abstract: In accordance with an embodiment, described herein is a system and method for compacting a pseudo linear byte array, for use with supporting access to a database. A database driver (e.g., a Java Database Connectivity (JDBC) driver) provides access by software application clients to a database. When a result set (e.g., ResultSet) is returned for storage in a dynamic byte array (DBA), in response to a database query (e.g., a SELECT), the database driver determines if the DBA is underfilled and, if so, calculates the data size of the DBA, creates a static byte array (SBA) in a cache at the client, compacts the returned data into the SBA, and stores the data size as part of the metadata associated with the cache. In accordance with an embodiment, the DBA and the SBA can use a same interface for access by client applications.

Abstract: An apparatus and method are described for distributed snoop filtering. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions and process data; first snoop logic to track a first plurality of cache lines stored in a mid-level cache (“MLC”) accessible by one or more of the cores, the first snoop logic to allocate entries for cache lines stored in the MLC and to deallocate entries for cache lines evicted from the MLC, wherein at least some of the cache lines evicted from the MLC are retained in a level 1 (L1) cache; and second snoop logic to track a second plurality of cache lines stored in a non-inclusive last level cache (NI LLC), the second snoop logic to allocate entries in the NI LLC for cache lines evicted from the MLC and to deallocate entries for cache lines stored in the MLC, wherein the second snoop logic is to store and maintain a first set of core valid bits to identify cores containing copies of the cache lines stored in the NI LLC.

Abstract: Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.

Abstract: Embodiments relate to cache coherency verification using ordered lists. An aspect includes maintaining a plurality of ordered lists, each ordered list corresponding to a respective thread that is executed by a processor, wherein each ordered list comprises a plurality of atoms, each atom corresponding to a respective operation performed in a cache by the respective thread that corresponds to the ordered list in which the atom is located, wherein the plurality of atoms in an ordered list are ordered based on program order. Another aspect includes determining a state of an atom in an ordered list of the plurality of ordered lists. Another aspect includes comparing the state of the atom in an ordered list to a state of an operation corresponding to the atom in the cache. Yet another aspect includes, based on the comparing, determining that there is a coherency violation in the cache.

Abstract: Embodiments described include systems, apparatuses, and methods using sectored dynamic random access memory (DRAM) cache. An exemplary apparatus may include at least one hardware processor core and a sectored dynamic random access (DRAM) cache coupled to the at least one hardware processor core.

Abstract: A command to write data to a virtual location is received at a disk storage system. The virtual location is mapped to a tape storage system. A record is generated including the data, the virtual location, and a sequence value. The sequence value indicates relative sequence when compared to other sequence values. The record is written to a record location on a tape cartridge loaded in a tape drive. Record metadata on the disk storage system is modified to indicate that the first record location contains the first record. The data on the record can be read from the tape cartridge.

Abstract: An apparatus and method are described for translation lookaside buffer (TLB) miss handling. For example, one embodiment of a processor comprises: a translation lookaside buffer (TLB) to store virtual-to-physical address translations; a page miss handler (PMH) to process TLB misses when a desired virtual-to-physical address translation is not present in the TLB; and a compressed page table to be managed by the PMH, the compressed page table to store specified portions of page tables, wherein in response to a TLB miss for a first address translation, the PMH is to check the compressed page table to determine if a page table entry corresponding to the first address translation is stored therein and, if so, to provide the first address translation from the compressed page table.

Abstract: A method includes reading memory pages from a non-volatile memory that holds at least first memory pages having a first bit significance and second memory pages having a second bit significance, different from the first bit significance. At least some of the read memory pages are cached in a cache memory. One or more of the cached memory pages are selected for eviction from the cache memory, in accordance with a selection criterion that gives eviction preference to the memory pages of the second bit significance over the memory pages of the first bit significance. The selected memory pages are evicted from the cache memory.

Abstract: A processor includes a front end, a cache, and a cache controller. The front end includes logic to receive an instruction defining a priority dataset. The priority dataset includes ranges of memory addresses each corresponding to a respective priority level. The cache controller includes logic to detect a miss in the cache for a requested cache value, determine a candidate cache victim from the cache, determine a priority of the requested cache value and the candidate cache victim according to the priority dataset, and evict the candidate cache victim based on a determination that the priority of the candidate cache victim is less or equal to the priority of the requested cache value.

Abstract: Techniques for chunk-level client side encryption are provided. In a content-addressable storage system, a plurality of chunks is used to implement a hierarchical file system. The hierarchical file system supports both encrypted and non-encrypted volumes. A folders and files layer makes calls directly to a chunk system layer for operations involving non-encrypted volumes. The folders and files layer makes calls to a volume encryption layer for operations involving encrypted volumes. The volume encryption layer receives calls from the folders and files layer through an API that matches the API through which the chunk system layer receives calls from the folders and files layer.

Abstract: A protection circuit can be used with a computer system having a master device and at least one slave device that are connected by an inter-integrated circuit (I2C) bus. A first access request is received that includes an address that identifies a first slave device. In response to a permissible mode, the first access request is communicated to the first slave device using the I2C bus. A sticky protection bit can be set. In response to the sticky protection bit being set, the protection circuit can be placed in a protected mode. A second access request is received. The second access request can be determined to be a protected access to the first slave device. In response to the determining and the protected mode, the second access request to the first slave device can be denied.

Abstract: An electronic device is provided. The electronic device includes a first control module including a normal module and a security module, and a second control module distinct from the first control module. The normal module sets a secure memory which the security module and the second control module access, and the security module determines validity of the set secure memory.

Abstract: A system, a method, and an apparatus are disclosed. In an embodiment, a system includes a host processor with a communications unit, a memory coupled to the communications unit, and a coprocessor coupled to the communications unit. The memory may include at least a first area and a second area. The coprocessor may be configured to request access to the first area of the memory via the communications unit. The communications unit may be configured to verify an identity of the coprocessor, and grant access to the first area of the memory responsive to a positive identification of the coprocessor.

Abstract: A method for executing a program code is suggested, the method comprising: checking a memory access policy resource based on a trigger; and comparing a current program counter with a program counter information provided by the memory access policy resource and, in case the comparison of the current program counter and the program counter information fulfills a predefined condition, conducting a memory access policy check to allow permitted operations.

Abstract: Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities.

Abstract: A method, system, and computer program product for IO leveling comprising receiving an IO, determining if there is a delay for processing IO because of pending IO, based on a positive determination there is a delay for processing IO, determining a priority for the IO, and based on the priority of IO determining whether to process the IO.

Abstract: A first state of an interconnect protocol is entered. A particular signal is sent according to the protocol to a device over a link. During the first state, it is detected that a response to the particular signal is received in the first state. It is determined that the device supports a configuration mode outside the protocol based on the received response. The configuration mode is entered based on the response. One or more in-band configuration messages are sent within the configuration mode.

Abstract: A processor of an aspect includes a decode unit to decode an exception handler return instruction. The processor also includes an exception handler return execution unit coupled with the decode unit. The exception handler return execution unit, responsive to the exception handler return instruction, is to not configure the processor to enable delivery of a subsequently received nonmaskable interrupt (NMI) to an NMI handler if an exception, which corresponds to the exception handler return instruction, was taken within the NMI handler. The exception handler return execution unit, responsive to the exception handler return instruction, is to configure the processor to enable the delivery of the subsequently received NMI to the NMI handler if the exception was not taken within the NMI handler. Other processors, methods, systems, and instructions are disclosed.

Abstract: A memory device and a memory controller can interface over a system data bus that has a narrower bandwidth than a data bus internal to the memory device. The memory device and memory controller transfer data over the system data bus on all transfer periods of a burst length, but send fewer bits than would be needed for the exchange to transfer all bits that can be read or written on the internal data bus of the memory device. The memory device can have different operating modes to allow for a common memory device to be used in different system configurations based on the ability to interface with the narrower bandwidth system data bus.

Abstract: A read writeable random accessible non-volatile memory module includes a printed circuit board with an edge connector that can be plugged into a socket of a printed circuit board. The read writeable random accessible non-volatile memory modules further include a plurality of read writable non-volatile memory devices.