Characterized By Specified Crystallography Or Arrangement Of Substrate (e.g., Wafer Cassette, Miller Index) Patents (Class 117/101)
  • Patent number: 10023974
    Abstract: A method of fabricating a composite semiconductor component comprising: (i) providing a bowed substrate comprising a wafer of synthetic diamond material having a thickness td, the bowed substrate being bowed by an amount B and comprising a convex face and a concave face; (ii) growing a layer of compound semiconductor material on the convex face of the bowed substrate via a chemical vapour deposition technique at a growth temperature T to form a bowed composite semiconductor component comprising the layer of compound semiconductor material of thickness tsc on the convex face of the bowed substrate, the compound semiconductor material having a higher average thermal expansion coefficient than the synthetic diamond material between the growth temperature T and room temperature providing a thermal expansion mismatch ?Tec; and (iii) cooling the bowed composite semiconductor component, wherein the layer of compound semiconductor material contracts more than the wafer of synthetic diamond material during cooling due
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: July 17, 2018
    Inventors: Timothy Mollart, Quanzhong Jiang, Michael John Edwards, Duncan Allsopp, Christopher Rhys Bowen, Wang Nang Wang
  • Patent number: 10002981
    Abstract: Solar cell structures including multiple sub-cells that incorporate different materials that may have different lattice constants. In some embodiments, solar cell devices include several photovoltaic junctions.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: James Fiorenza, Anthony J. Lochtefeld
  • Patent number: 9997458
    Abstract: Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially filling said recessed structure with a metal chosen from the group consisting of copper, nickel and cobalt; introducing the substrate in a CVD reactor; bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, thereby substantially completely converting the metal in the recessed structure to a germanide.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: June 12, 2018
    Assignee: IMEC vzw
    Inventors: Laure Elisa Carbonell, Antony Premkumar Peter, Marc Schaekers, Sven Van Elshocht, Zsolt Tokei
  • Patent number: 9957640
    Abstract: A single crystal diamond has a surface. In the single crystal diamond, a measurement region is defined in the surface, the measurement region includes a portion exhibiting a transmittance that is highest in the single crystal diamond and a portion exhibiting a transmittance that is lowest in the single crystal diamond, the measurement region has a plurality of square regions that are continuously arranged and each have a side having a length of 0.2 mm, and an average value of transmittances in each of the plurality of square regions is measured, wherein assuming that the average value of the transmittances in one square region is defined as T1 and the average value of the transmittances in another square region adjacent to the one square region is defined as T2, a relation of ((T1?T2)/((T1+T2)/2)×100)/0.2?20 (%/mm) is satisfied throughout the measurement region.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: May 1, 2018
    Assignees: Sumitomo Electric Industries, Ltd., Sumitomo Electric Hardmetal Corp.
    Inventors: Yoshiki Nishibayashi, Akihiko Ueda, Hitoshi Sumiya, Yutaka Kobayashi, Yuichiro Seki, Toshiya Takahashi
  • Patent number: 9947830
    Abstract: A patterned sapphire substrate has a first surface and a second surface opposite to each other; the connection zone between first protrusion portions has no C surface (i.e. (0001) surface); and the patterned sapphire substrate may have no C surface on the growth surface to reduce the threading dislocation density of the GaN epitaxial material on the sapphire substrate.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: April 17, 2018
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Sheng-hsien Hsu, Gong Chen, Su-hui Lin, Yu-chieh Huang, Chen-ke Hsu
  • Patent number: 9899560
    Abstract: The present invention proposes a method to produce thin film CdTe solar cells having a pin-hole free and uniformly doped CdTe layer with a reduced layer thickness. The method according to the present invention is an efficient way to prevent shunting of the solar cells, to improve reliability and long-term stability of the solar cells and to provide a uniform doping of the CdTe layer. This is achieved by applying a sacrificial doping layer between a first CdTe layer having large grains and a second CdTe layer having small grains, which together form the CdTe layer of the solar cells. Furthermore it provides the possibility to eliminate the CdCl2 activation treatment step in case the sacrificial doping layer comprises a halogen.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: February 20, 2018
    Assignees: China Triumph International Engineering Co., Ltd., CTF Solar GmbH
    Inventors: Krishnakumar Velappan, Shou Peng
  • Patent number: 9881826
    Abstract: A buffer for use in semiconductor processing tools is disclosed. The buffer may be used to temporarily store wafers after processing operations are performed on those wafers. The buffer may include two side walls and a back wall interposed between the side walls. The side walls and the back wall may generally define an area within which the wafers may be stored in a stacked arrangement. Wafer support fins extending from the side walls and the back wall may extend into a wafer support region that overlaps with the edges of the wafers. Purge gas may be introduced in between each pair of wafers via purge gas ports located in one of the walls.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: January 30, 2018
    Assignee: Lam Research Corporation
    Inventors: Martin Robert Maraschin, Richard Howard Gould, Derek John Witkowicki
  • Patent number: 9853136
    Abstract: A directed epitaxial heterojunction bipolar transistor (HBT) structure is directly or indirectly formed on a GaAs substrate that is formed by a (100) face towards a (111)B face with an angle of inclination between 0.6° and 25°, and includes a sub-collector layer, a collector, a base layer, an emitter layer, an emitter cap layer and an ohmic contact layer, which are sequentially formed on the substrate. A tunnel collector layer formed by InGaP or InGaAsP is provided between the collector layer and the base layer. Since an epitaxial process is performed on the substrate from a (100) face towards a (111)B face with an angle of inclination between 0.6° and 25°, indium and gallium contained in InGaP or InGaAsP are affected by the ordering effect such that InGaP or InGaAsP used in the emitter layer and/or the tunnel collector layer has a higher electron affinity or a smaller bandgap.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: December 26, 2017
    Assignee: VISUAL PHOTONICS EPITAXY CO., LTD.
    Inventors: Yu-Chung Chin, Chao-Hsing Huang, Min-Nan Tseng
  • Patent number: 9777402
    Abstract: A method of forming a layered OP material is provided, where the layered OP material comprises an OPGaAs template, and a layer of GaP on the OPGaAs template. The OPGaAs template comprises a patterned layer of GaAs having alternating features of inverted crystallographic polarity of GaAs. The patterned layer of GaAs comprises a first feature comprising a first crystallographic polarity form of GaAs having a first dimension, and a second feature comprising a second crystallographic polarity form of GaAs having a second dimension. The layer of GaP on the patterned layer of GaAs comprises alternating regions of inverted crystallographic polarity that generally correspond to their underlying first and second features of the patterned layer of GaAs. Additionally, each of the alternating regions of inverted crystallographic polarity of GaP are present at about 100 micron thickness or more.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 3, 2017
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Vladimir L. Tassev, Rita D. Peterson
  • Patent number: 9780100
    Abstract: A method of forming a memory device that includes forming a sacrificial gate on a surface of a first source/drain region, and forming a channel opening through the sacrificial gate. The method may further include forming an epitaxial channel region is formed in the channel opening that is in situ doped to have an opposite conductivity type as the first of the source/drain region. A second source/drain region is formed on a portion of the epitaxial channel region opposite the portion of the epitaxial channel region that the first source/drain region is present on, wherein the second source/drain region has a same conductivity type as the conductivity type of the first source/drain region. A memory gate structure including a floating gate and a control gate is substituted for the sacrificial gate.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: October 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Patent number: 9762032
    Abstract: In an example, the present invention provides a gallium and nitrogen containing multilayered structure, and related method. The structure has a plurality of gallium and nitrogen containing semiconductor substrates, each of the gallium and nitrogen containing semiconductor substrates (“substrates”) having a plurality of epitaxially grown layers overlaying a top-side of each of the substrates. The structure has an orientation of a reference crystal direction for each of the substrates. The structure has a first handle substrate coupled to each of the substrates such that each of the substrates is aligned to a spatial region configured in a selected direction of the first handle substrate, which has a larger spatial region than a sum of a total backside region of plurality of the substrates to be arranged in a tiled configuration overlying the first handle substrate. The reference crystal direction for each of the substrates is parallel to the spatial region in the selected direction within 10 degrees or less.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: September 12, 2017
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Melvin McLaurin, Alexander Sztein, Po Shan Hsu, James W. Raring
  • Patent number: 9728628
    Abstract: A silicon carbide epitaxial layer includes: a first impurity region; a second impurity region; and a third impurity region. A gate insulating film is in contact with the first impurity region, the second impurity region, and the third impurity region. A groove portion is formed in a surface of the first impurity region, the surface being in contact with the gate insulating film, the groove portion extending in one direction along the surface, a width of the groove portion in the one direction being twice or more as large as a width of the groove portion in a direction perpendicular to the one direction, a maximum depth of the groove portion from the surface being not more than 10 nm.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: August 8, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Taro Nishiguchi, Toru Hiyoshi, Taku Horii, Kosuke Uchida
  • Patent number: 9698287
    Abstract: An epitaxial wafer of the present invention includes a substrate composed of a III-V compound semiconductor, a multiple quantum well structure composed of a III-V compound semiconductor and located on the substrate, and a top layer composed of a III-V compound semiconductor and located on the multiple quantum well structure. The substrate has a plane orientation of (100) and an off angle of ?0.030° or more and +0.030° or less, and a surface of the top layer has a root-mean-square roughness of less than 10 nm.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: July 4, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kei Fujii, Kaoru Shibata, Katsushi Akita
  • Patent number: 9657397
    Abstract: An apparatus for processing wafer-shaped articles comprises a closed process chamber providing a gas-tight enclosure. A rotary chuck is located within the closed process chamber, the rotary chuck being adapted to hold a wafer shaped article thereon. A lid is secured to an upper part of the closed process chamber, the lid comprising an upper plate formed from a composite fiber-reinforced material and a lower plate that faces into the process chamber and is formed from a chemically-resistant plastic.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: May 23, 2017
    Assignee: LAM RESEARCH AG
    Inventor: Andreas Gleissner
  • Patent number: 9653308
    Abstract: A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth substrate with a top surface, a sacrificial layer on the top surface, and a device layer on the sacrificial layer. This substrate is supported inside a container and the container is filled with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate. While filling the container with the wet etchant, the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant. Performed in this manner, the lift-off process requires little individual setup of the sample, and is capable of batch processing and high throughput.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: May 16, 2017
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Leathen Shi, Kuen-Ting Shiu
  • Patent number: 9647156
    Abstract: A layered OP material is provided that comprises an OPGaAs template, and a layer of GaP on the OPGaAs template. The OPGaAs template comprises a patterned layer of GaAs having alternating features of inverted crystallographic polarity of GaAs. The patterned layer of GaAs comprises a first feature comprising a first crystallographic polarity form of GaAs having a first dimension, and a second feature comprising a second crystallographic polarity form of GaAs having a second dimension. The layer of GaP on the patterned layer of GaAs comprises alternating regions of inverted crystallographic polarity that generally correspond to their underlying first and second features of the patterned layer of GaAs. Additionally, each of the alternating regions of inverted crystallographic polarity of GaP are present at about 100 micron thickness or more. A method of forming the OPGaP is also provided.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: May 9, 2017
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Vladimir L. Tassev, Rita D. Peterson
  • Patent number: 9640979
    Abstract: A superconducting element (1) has a metallic substrate (2), an insulating layer (3), a superconductor layer (5) and a metallic protective layer (6), wherein the insulating layer (3) is arranged between the substrate (2) and the superconductor layer (5). In cross-section of the superconducting element (1), the insulating layer (3) extends at both ends past the area (BSL) of the substrate (2) covered by the superconductor layer (5) to galvanically separate the superconductor layer (5) and the metallic protective layer (6) from the substrate (2). The thickness D of the insulating layer (3) is selected in such a fashion that the superconducting element (1) has a transverse breakdown voltage between the metallic substrate (2) and both the superconductor layer (5) as well as the metallic protective layer (6) of at least 25 V. The superconducting element has a reduced risk of being damaged in case of a quench.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: May 2, 2017
    Assignee: Bruker H I S GmbH
    Inventor: Alexander Usoskin
  • Patent number: 9631276
    Abstract: A gas delivery system includes a first valve including an inlet that communicates with a first gas source. A first inlet of a second valve communicates with an outlet of the first valve and a second inlet of the second valve communicates with a second gas source. An inlet of a third valve communicates with a third gas source. A connector includes a first gas channel and a cylinder defining a second gas channel. The cylinder and the first gas channel collectively define a flow channel between an outer surface of the cylinder and an inner surface of the first gas channel. The flow channel communicates with the outlet of the third valve and the first end of the second gas channel. A third gas channel communicates with the second gas channel, with the outlet of the second valve and with a gas distribution device of a processing chamber.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: April 25, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Ramesh Chandrasekharan, Jennifer O'Loughlin, Saangrut Sangplung, Shankar Swaminathan, Frank Pasquale, Chloe Baldasseroni, Adrien LaVoie
  • Patent number: 9607846
    Abstract: A device includes a crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by using a planarization process configured with a selectivity of the crystalline material to the insulator greater than one. In a preferred embodiment, the planarization process uses a composition including abrasive spherical silica, H2O2 and water. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jennifer M. Hydrick, James Fiorenza
  • Patent number: 9597701
    Abstract: An apparatus for processing wafer-shaped articles comprises a closed process chamber providing a gas-tight enclosure. A rotary chuck is located within the closed process chamber, and is adapted to hold a wafer shaped article thereon. A lid is secured to an upper part of the closed process chamber. The lid comprises an annular chamber, gas inlets communicating with the annular chamber and opening on a surface of the lid facing outwardly of the closed process chamber, and gas outlets communicating with the annular chamber and opening on a surface of the lid facing inwardly of the closed process chamber.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: March 21, 2017
    Assignee: LAM RESEARCH AG
    Inventors: Rainer Obweger, Andreas Gleissner, Philipp Engesser
  • Patent number: 9595470
    Abstract: Methods for forming tungsten film using fluorine-free tungsten precursors such as tungsten chlorides are provided. Methods involve depositing a tungsten nucleation layer by exposing a substrate to a reducing agent such as diborane (B2H6) and exposing the substrate to a tungsten chloride, followed by depositing bulk tungsten by exposing the substrate to a tungsten chloride and a reducing agent. Methods also involve diluting the reducing agent and exposing the substrate to a fluorine-free precursor in pulses to deposit a tungsten nucleation layer. Deposited films exhibit good step coverage and plugfill.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: March 14, 2017
    Assignee: Lam Research Corporation
    Inventors: Hanna Bamnolker, Raashina Humayun, Juwen Gao, Michal Danek, Joshua Collins
  • Patent number: 9587326
    Abstract: To provide silicon carbide epitaxial wafer in which occurrence of giant step bunchings (GSBs) caused by basal plane dislocations (BPDs) that occur during hydrogen etching is suppressed on low off-angle silicon carbide substrate to decrease surface defect density of epitaxially grown layer to allow formation of silicon carbide semiconductor device having high reliability, method for manufacturing the wafer, and apparatus for manufacturing the wafer, and silicon carbide semiconductor device having the wafer. A silicon carbide epitaxial wafer of the present invention is such that epitaxially grown layer is disposed on silicon carbide substrate which has ?-type crystal structure and in which (0001) Si face is tilted at greater than 0° and less than 5°, wherein surface defect density of the epitaxially grown layer based on giant step bunching caused by basal plane dislocation on substrate surface of the silicon carbide substrate is ?20/cm2.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: March 7, 2017
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Keiko Masumoto, Kazutoshi Kojima, Kentaro Tamura
  • Patent number: 9574287
    Abstract: A method of forming an epitaxial semiconductor material that includes forming a graphene layer on a semiconductor and carbon containing substrate and depositing a metal containing monolayer on the graphene layer. An epitaxial layer of a gallium containing material is formed on the metal containing monolayer. A layered stack of the metal containing monolayer and the epitaxial layer of gallium containing material is cleaved from the graphene layer that is present on the semiconductor and carbon containing substrate.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Can Bayram, Christos D. Dimitrakopoulos, Keith E. Fogel, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • Patent number: 9570292
    Abstract: A method for making an epitaxial structure includes the following steps. A substrate having an epitaxial growth surface is provided. A buffer layer is formed on the epitaxial growth surface. A carbon nanotube layer is placed on the buffer layer. A first epitaxial layer is epitaxially grown on the buffer layer. The substrate and the buffer layer are removed to expose a second epitaxial growth surface. A second epitaxial layer is epitaxially grown on the second epitaxial growth surface.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: February 14, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 9570540
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: February 14, 2017
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
  • Patent number: 9557378
    Abstract: Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast devices to classify the devices into different voltage bins. A bin-specific voltage limit is established for each of the voltage bins needed for core performance at system use conditions. The bin-specific voltage limit is compared to core minimum chip-level functionality voltage at system maximum and minimum frequency specifications. The method correlates system design evaluation of design maximum and minimum frequency at design maximum and minimum voltage conditions with evaluation of tested maximum and minimum frequency at tested maximum and minimum voltage conditions. A chip-specific functionality voltage limit is established for the device.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: January 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jeanne P. Bickford, Vikram Iyengar, Rahul K. Nadkarni, Pascal A. Nsame
  • Patent number: 9537095
    Abstract: Precursors for use in depositing tellurium-containing films on substrates such as wafers or other microelectronic device substrates, as well as associated processes of making and using such precursors, and source packages of such precursors. The precursors are useful for deposition of Ge2Sb2Te5 chalcogenide thin films in the manufacture of nonvolatile Phase Change Memory (PCM), by deposition techniques such as chemical vapor deposition (CVD) and atomic layer deposition (ALD).
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: January 3, 2017
    Assignee: Entegris, Inc.
    Inventors: Matthias Stender, Chongying Xu, Tianniu Chen, William Hunks, Philip S. H. Chen, Jeffrey F. Roeder, Thomas H. Baum
  • Patent number: 9534317
    Abstract: A seed crystal for SiC single-crystal growth includes a facet formation region containing a {0001}-plane uppermost portion and n (n>=3) planes provided enclosing the periphery of the facet formation region. The seed crystal for SiC single-crystal growth satisfies the relationships represented by formula (a): Bkk-1<=cos?1(sin(2.3 degrees)/sin Ck), formula (b): Bkk<=cos?1(sin(2.3 degrees)/sin Ck), and formula (c): min(Ck)<=20 degrees. In the formulas, Ck is an offset angle of a k-th plane, Bkk-1 is an angle defined by an offset downstream direction of the k-th plane and a (k?1)-th ridge line, and Bkk is an angle defined by the offset downstream direction of the k-th plane and a k-th ridge line.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: January 3, 2017
    Assignees: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, DENSO CORPORATION, SHOWA DENKO K.K.
    Inventors: Itaru Gunjishima, Keisuke Shigetoh, Yasushi Urakami, Akihiro Matsuse
  • Patent number: 9496132
    Abstract: A method of fabricating a layer of single crystal III-N material on a silicon substrate includes epitaxially growing a REO template on a silicon substrate. The template includes a REO layer adjacent the substrate with a crystal lattice spacing substantially matching the crystal lattice spacing of the substrate and selected to protect the substrate from nitridation. Either a rare earth oxynitride or a rare earth nitride is formed adjacent the upper surface of the template and a layer of single crystal III-N material is epitaxially grown thereon.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: November 15, 2016
    Assignee: Translucent, Inc.
    Inventors: Erdem Arkun, Andrew Clark, Rytis Dargis, Radek Roucka, Michael Lebby
  • Patent number: 9487884
    Abstract: A method for producing a mono-crystalline sheet includes providing at least two aperture elements forming a gap in between; providing a molten alloy including silicon in the gap; providing a gaseous precursor medium comprising silicon in the vicinity of the molten alloy; providing a silicon nucleation crystal in the vicinity of the molten alloy; and bringing in contact said silicon nucleation crystal and the molten alloy. A device for producing a mono-crystalline sheet includes at least two aperture elements at a predetermined distance from each other, thereby forming a gap, and being adapted to be heated for holding a molten alloy including silicon by surface tension in the gap between the aperture elements; a precursor gas supply supplies a gaseous precursor medium comprising silicon in the vicinity of the molten alloy; and a positioning device for holding and moving a nucleation crystal in the vicinity of the molten alloy.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: November 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Mikael T. Bjoerk, Heike E. Riel, Heinz Schmid
  • Patent number: 9461121
    Abstract: A process for producing a doped III-N bulk crystal, wherein III denotes at least one element of the main group III of the periodic system, selected from Al, Ga and In, wherein the doped crystalline III-N layer or the doped III-N bulk crystal is deposited on a substrate or template in a reactor, and wherein the feeding of at least one dopant into the reactor is carried out in admixture with at least one group III material. In this manner, III-N bulk crystals and III-N single crystal substrates separated therefrom can be obtained with a very homogeneous distribution of dopants in the growth direction as well as in the growth plane perpendicular thereto, a very homogeneous distribution of charge carriers and/or of the specific electric resistivity in the growth direction as well as in the growth plane perpendicular thereto, and a very good crystal quality.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: October 4, 2016
    Assignee: FREIBERGER COMPOUND MATERIALS GMBH
    Inventors: Ferdinand Scholz, Peter Brückner, Frank Habel, Gunnar Leibiger
  • Patent number: 9443939
    Abstract: A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: September 13, 2016
    Assignee: Translucent, Inc.
    Inventors: Rytis Dargis, Erdem Arkun, Radek Roucka, Andrew Clark, Michael Lebby
  • Patent number: 9431570
    Abstract: The object is to provide a photoelectric surface member which allows higher quantum efficiency. In order to achieve this object, a photoelectric surface member 1a is a crystalline layer formed by a nitride type semiconductor material, and comprises a nitride semiconductor crystal layer 10 where the direction from the first surface 101 to the second surface 102 is the negative c polar direction of the crystal, an adhesive layer 12 formed along the first surface 101 of the nitride semiconductor crystal layer 10, and a glass substrate 14 which is adhesively fixed to the adhesive layer 12 such that the adhesive layer 12 is located between the glass substrate 14 and the nitride semiconductor crystal layer 10.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: August 30, 2016
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Tokuaki Nihashi, Masatomo Sumiya, Minoru Hagino, Shunro Fuke
  • Patent number: 9401584
    Abstract: In an example, the present invention provides a gallium and nitrogen containing multilayered structure, and related method. The structure has a plurality of gallium and nitrogen containing semiconductor substrates, each of the gallium and nitrogen containing semiconductor substrates (“substrates”) having a plurality of epitaxially grown layers overlaying a top-side of each of the substrates. The structure has an orientation of a reference crystal direction for each of the substrates. The structure has a first handle substrate coupled to each of the substrates such that each of the substrates is aligned to a spatial region configured in a selected direction of the first handle substrate, which has a larger spatial region than a sum of a total backside region of plurality of the substrates to be arranged in a tiled configuration overlying the first handle substrate. The reference crystal direction for each of the substrates is parallel to the spatial region in the selected direction within 10 degrees or less.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: July 26, 2016
    Assignee: SORAA LASER DIODE, INC.
    Inventors: Melvin McLaurin, Alexander Sztein, Po Shan Hsu, James W. Raring
  • Patent number: 9373743
    Abstract: A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: June 21, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 9340898
    Abstract: A technology for growing silicon carbide single crystals by PVT (Physical Vapor Transport) and a technology for in-situ annealing the crystals after growth is finished is provided. The technology can achieve real-time dynamic control of the temperature distribution of growth chamber by regulating the position of the insulation layer on the upper part of the graphite crucible, thus controlling the temperature distribution of growth chamber in real-time during the growth process according to the needs of the technology, which helps to significantly improve the crystal quality and production yield.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: May 17, 2016
    Assignees: Tankeblue Semiconductor Co. Ltd., Institute of Physics Chinese Academy of Sciences
    Inventors: Xiaolong Chen, Bo Wang, Longyuan Li, Tonghua Peng, Chunjun Liu, Wenjun Wang, Gang Wang
  • Patent number: 9336989
    Abstract: Embodiments relate to use of a particle accelerator beam to form thin layers of material from a bulk substrate. In particular embodiments, a bulk substrate (e.g. donor substrate) having a top surface is exposed to a beam of accelerated particles. In certain embodiments, this bulk substrate may comprise a core of crystalline sapphire (Al2O3) material. Then, a thin layer of the material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. Embodiments may find particular use as hard, scratch-resistant covers for personal electric device displays, or as optical surfaces for fingerprint, eye, or other biometric scanning.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: May 10, 2016
    Assignee: SILICON GENESIS CORPORATION
    Inventor: Francois J. Henley
  • Patent number: 9230850
    Abstract: The invention relates to a method for manufacturing a multilayer structure on a first substrate made of a material having a first Young's modulus. The method includes: providing a second substrate covered with the multilayer structure, the multilayer structure having a planar surface opposite the second substrate, the second substrate being made of a material having a second Young's modulus; applying first deformations to said surface; molecularly boding the first substrate to said surface, the molecular bonding resulting in the appearance of second deformation in said surface in the absence of the first deformations, the first deformations being opposite the second deformations; and removing the second substrate, the resulting deformations in said surface being less than 5 ppm.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: January 5, 2016
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Umberto Rossini, Raphaël Eleouet, Thierry Flahaut
  • Patent number: 9142623
    Abstract: Provided is a substrate for epitaxial growth, which enables the improvement in quality of a Ga-containing oxide layer that is formed on a ?-Ga2O3 single-crystal substrate. A substrate (1) for epitaxial growth comprises ?-Ga2O3 single crystals, wherein face (010) of the single crystals or a face that is inclined at an angle equal to or smaller than 37.5° with respect to the face (010) is the major face. A crystal laminate structure (2) comprises: the substrate (1) for epitaxial growth; and epitaxial crystals (20) which are formed on the major face (10) of the substrate (1) for epitaxial growth and each of which comprises a Ga-containing oxide.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: September 22, 2015
    Assignee: TAMURA CORPORATION
    Inventor: Kohei Sasaki
  • Patent number: 9048102
    Abstract: An SiC single crystal includes a low dislocation density region (A) where the density of dislocations each of which has a Burgers vector in a {0001} in-plane direction (mainly a direction parallel to a <11-20> direction) is not more than 3,700 cm/cm3. Such an SiC single crystal is obtained by: cutting out a c-plane growth seed crystal of a high offset angle from an a-plane grown crystal; applying c-plane growth so that the density of screw dislocations introduced into a c-plane facet may fall in a prescribed range; cutting out a c-plane growth crystal of a low offset angle from the obtained c-plane grown crystal; and applying c-plane growth so that the density of screw dislocations introduced into a c-plane facet may fall in a prescribed range. An SiC wafer and a semiconductor device are obtained from such an SiC single crystal.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: June 2, 2015
    Assignees: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Itaru Gunjishima, Yasushi Urakami, Ayumu Adachi
  • Patent number: 9028612
    Abstract: In various embodiments, non-zero thermal gradients are formed within a growth chamber both substantially parallel and substantially perpendicular to the growth direction during formation of semiconductor crystals, where the ratio of the two thermal gradients (parallel to perpendicular) is less than 10, by, e.g., arrangement of thermal shields outside of the growth chamber.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: May 12, 2015
    Assignee: Crystal IS, Inc.
    Inventors: Robert T. Bondokov, Shailaja P. Rao, Shawn Robert Gibb, Leo J. Schowalter
  • Patent number: 9023673
    Abstract: A method to grow single phase group III-nitride articles including films, templates, free-standing substrates, and bulk crystals grown in semi-polar and non-polar orientations is disclosed. One or more steps in the growth process includes the use of additional free hydrogen chloride to eliminate undesirable phases, reduce surface roughness, and increase crystalline quality. The invention is particularly well-suited to the production of single crystal (11.2) GaN articles that have particular use in visible light emitting devices.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Ostendo Technologies, Inc.
    Inventors: Lisa Shapovalov, Oleg Kovalenkov, Vladimir Ivantsov, Vitali Soukhoveev, Alexander Syrkin, Alexander Usikov
  • Patent number: 9017633
    Abstract: Single crystal diamond material produced using chemical vapour deposition (CVD), and particularly diamond material having properties suitable for use in optical applications such as lasers, is disclosed. In particular, a CVD single crystal diamond material having preferred characteristics of longest linear internal dimension, birefringence and absorption coefficient, when measured at room temperature, is disclosed. Uses of the diamond material, including in a Raman laser, and methods of producing the diamond are also disclosed.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: April 28, 2015
    Assignee: Element Six Technologies Limited
    Inventors: Ian Friel, Sarah Louise Geoghegan, Daniel James Twitchen, Joseph Michael Dodson
  • Patent number: 9005362
    Abstract: The present invention is to provide a method for growing a group III nitride crystal that has a large size and has a small number of pits formed in the main surface of the crystal by using a plurality of tile substrates. A method for growing a group III nitride crystal includes a step of preparing a plurality of tile substrates 10 including main surfaces 10m having a shape of a triangle or a convex quadrangle that allows two-dimensional close packing of the plurality of tile substrates; a step of arranging the plurality of tile substrates 10 so as to be two-dimensionally closely packed such that, at any point across which vertexes of the plurality of tile substrates 10 oppose one another, 3 or less of the vertexes oppose one another; and a step of growing a group III nitride crystal 20 on the main surfaces 10m of the plurality of tile substrates arranged.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: April 14, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yuki Hiromura, Koji Uematsu, Hiroaki Yoshida, Shinsuke Fujiwara
  • Patent number: 8980003
    Abstract: In a method of manufacturing a silicon carbide single crystal, a silicon carbide substrate having a surface of one of a (11-2n) plane and a (1-10n) plane, where n is any integer number greater than or equal to 0, is prepared. An epitaxial layer having a predetermined impurity concentration is grown on the one of the (11-2n) plane and the (1-10n) plane of the silicon carbide substrate by a chemical vapor deposition method so that a threading dislocation is discharged from a side surface of the epitaxial layer. A silicon carbide single crystal is grown into a bulk shape by a sublimation method on the one of the (11-2n) plane and the (1-10n) plane of the epitaxial layer from which the threading dislocation is discharged.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: March 17, 2015
    Assignee: DENSO CORPORATION
    Inventors: Hiroki Watanabe, Yasuo Kitou, Masami Naito
  • Publication number: 20150064098
    Abstract: The present invention provides a process for producing a two-dimensional nanomaterial by chemical vapour deposition (CVD), the process comprising contacting a substrate in a reaction chamber with a first flow which contains hydrogen and a second flow which contains a precursor for said material, wherein the contacting takes place under conditions such that the precursor reacts in the chamber to form said material on a surface of the substrate, wherein the ratio of the flow rate of the first flow to the flow rate of the second flow is at least 5:1. Two-dimensional nanomaterials obtainable by said process are also provided, as well as devices comprising said nanomaterials.
    Type: Application
    Filed: March 28, 2013
    Publication date: March 5, 2015
    Applicant: Isis Innovation Limited
    Inventors: Nicole Grobert, Adrian Timothy Murdock, Antal Adolf Koós
  • Patent number: 8940094
    Abstract: A method of fabricating a semiconductor processing device includes providing a susceptor including a substantially cylindrical body portion having opposing upper and lower surfaces. The body portion has a diameter larger than a wafer diameter. The method also includes providing a set of holes circumferentially disposed at a first susceptor diameter, the set of holes being evenly spaced with respect to adjacent holes and extending through the upper and lower surfaces in an area. The first susceptor diameter is larger than the wafer diameter, and holes are omitted along the first diameter in a set of predetermined orientations.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: January 27, 2015
    Assignee: SunEdison Semiconductor Limited
    Inventors: John Allen Pitney, Manabu Hamano
  • Patent number: 8936682
    Abstract: A manufacturing method of a SiC single crystal includes growing a SiC single crystal on a surface of a SiC seed crystal, which satisfies following conditions: (i) the SiC seed crystal includes a main growth surface composed of a plurality of sub-growth surfaces; (ii) among directions from an uppermost portion of a {0001} plane on the main growth surface to portions on a periphery of the main growth surface, the SiC seed crystal has a main direction in which a plurality of sub-growth surfaces is arranged; and (iii) an offset angle ?k of a k-th sub-growth surface and an offset angle ?k+1 of a (k+1)-th sub-growth surface satisfy a relationship of ?k<?k+1.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: January 20, 2015
    Assignee: DENSO CORPORATION
    Inventors: Yasushi Urakami, Itaru Gunjishima, Ayumu Adachi
  • Publication number: 20150004435
    Abstract: The present invention relates to a method for growing a non-polar m-plane epitaxial layer on a single crystal oxide substrate, which comprises the following steps: providing a single crystal oxide with a perovskite structure; using a plane of the single crystal oxide as a substrate; and forming an m-plane epitaxial layer of wurtzite semiconductors on the plane of the single crystal oxide by a vapor deposition process, wherein the non-polar m-plane epitaxial layer may be GaN, or III-nitrides. The present invention also provides an epitaxial layer having an m-plane obtained according to the aforementioned method.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 1, 2015
    Inventors: Li CHANG, Yen-Teng HO
  • Patent number: 8906159
    Abstract: Disclosed are a (Al, Ga, In)N-based compound semiconductor device and a method of fabricating the same. The (Al, Ga, In)N-based compound semiconductor device of the present invention comprises a substrate; a (Al, Ga, In)N-based compound semiconductor layer grown on the substrate; and an electrode formed of at least one material or an alloy thereof selected from the group consisting of Pt, Pd and Au on the (Al, Ga, In)N-based compound semiconductor layer.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: December 9, 2014
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Chung Hoon Lee