Of Amorphous Precursor Patents (Class 117/8)
  • Patent number: 7018468
    Abstract: A process of lateral crystallization is provided for increasing the lateral growth length (LGL). A localized region of the substrate is heated for a short period of time. While the localized region of the substrate is still heated, a silicon film overlying the substrate is irradiated to anneal the silicon film to crystallize a portion of the silicon film in thermal contact with the heated substrate region. A CO2 laser may be used as a heat source to heat the substrate, while a UV laser or a visible spectrum laser is used to irradiate and crystallize the film.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: March 28, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Apostolos T. Voutsas, Robert S. Sposili, Mark A. Crowder
  • Patent number: 6997985
    Abstract: Method of fabricating semiconductor devices such as thin-film transistors by annealing a substantially amorphous silicon film at a temperature either lower than normal crystallization temperature of amorphous silicon or lower than the glass transition point of the substrate so as to crystallize the silicon film. Islands, stripes, lines, or dots of nickel, iron, cobalt, or platinum, silicide, acetate, or nitrate of nickel, iron, cobalt, or platinum, film containing various salts, particles, or clusters containing at least one of nickel, iron, cobalt, and platinum are used as starting materials for crystallization. These materials are formed on or under the amorphous silicon film.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: February 14, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura, Hongyong Zhang, Toru Takayama, Hideki Uochi
  • Patent number: 6987037
    Abstract: One aspect of this disclosure relates to a method for forming a strained silicon over silicon germanium (Si/SiGe) structure. In various embodiments, germanium ions are implanted into a silicon substrate with a desired dose and energy to be located beneath a surface silicon layer in the substrate. The implantation of germanium ions at least partially amorphizes the surface silicon layer. The substrate is heat treated to regrow a crystalline silicon layer over a resulting silicon germanium layer using a solid phase epitaxial (SPE) process. The crystalline silicon layer is strained by a lattice mismatch between the silicon germanium layer and the crystalline silicon layer. Other aspects are provided herein.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: January 17, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 6961361
    Abstract: An object is to obtain an even energy distribution of a laser beam in one direction, thereby conducting a uniform laser annealing on a film. A laser irradiation apparatus comprising: a lens for dividing a laser beam in one direction; and an optical system for overlapping the divided laser beam, characterized in that the shape of the laser beam entering into the lens has edges vertical to the above-mentioned direction.
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: November 1, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koichiro Tanaka
  • Patent number: 6887311
    Abstract: There is provided a method of forming an ohmic electrode, including the steps of: forming a hafnium layer on a surface of an n type nitride-based compound semiconductor layer to have a thickness of 1 to 15 nm; forming an aluminum layer on the hafnium layer; and annealing the hafnium layer and the aluminum layer to form a layer formed of hafnium and aluminum mixed together.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: May 3, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Mayuko Fudeta, Toshio Hata
  • Patent number: 6860938
    Abstract: The present invention provides a method by which an oxide material having excellent thermoelectric conversion performance can be produced by a simple process. Specifically, the present invention provides a method for producing a composite oxide single crystal in which a mixture of raw substances including a Bi-containing substance, a Sr-containing substance, a Ca-containing substance, a Co-containing substance and a Te-containing substance, or a mixture of raw substances also including a Pb-containing substance in addition to the above-mentioned substances, is heated in an oxygen-containing atmosphere at a temperature below the melting point of any of the raw substances. The composite oxide single crystal produced by the method of the present invention is a ribbon-shaped fibrous single crystal that is about 10 to 10,000 ?m long, about 20 to 200 ?m wide, and about 1 to 5 ?m thick.
    Type: Grant
    Filed: May 27, 2002
    Date of Patent: March 1, 2005
    Assignee: National Institute of Advanced Technology
    Inventors: Ryoji Funahashi, Ichiro Matsubara, Masahiro Shikano
  • Patent number: 6830616
    Abstract: The nickel element is provided selectively, i.e., adjacent to part of the surface of an amorphous silicon film in a long and narrow opening. The amorphous silicon film is irradiated with linear infrared light beams emitted from respective linear infrared lamps while scanned with the linear beams perpendicularly to the longitudinal direction of the opening. The longitudinal direction of the linear beams are set coincident with that of the opening. The infrared light beams are absorbed by the silicon film mainly as thermal energy, whereby a negative temperature gradient is formed in the silicon film. The temperature gradient moves as the lamps are moved for the scanning. The direction of the negative temperature gradient is set coincident with the lamp movement direction and an intended crystal growth direction, which enables crystal growth to proceed parallel with a substrate uniformly over a long distance.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: December 14, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Patent number: 6825102
    Abstract: A method in which a defective semiconductor crystal material is subjected to an amorphization step followed by a thermal treatment step is provided. The amorphization step amorphizes, partially or completely, a region, including the surface region, of a defective semiconductor crystal material. A thermal treatment step is next performed so as to recrystallize the amorphized region of the defective semiconductor crystal material. The recrystallization is achieved in the present invention by solid-phase crystal regrowth from the non-amorphized region of the defective semiconductor crystal material.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: November 30, 2004
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Shreesh Narasimha, Devendra K. Sadana
  • Patent number: 6818059
    Abstract: The present invention is related to a method of crystallizing an amorphous silicon layer and a crystallizing apparatus thereof which crystallize an amorphous silicon layer using plasma. The present invention includes the steps of depositing an inducing substance for silicon crystallization on an amorphous silicon layer by plasma exposure, and carrying out annealing on the amorphous silicon layer to the amorphous silicon layer. The present invention includes a chamber having an inner space, a substrate support in the chamber wherein the substrate support supports a substrate, a plasma generating means in the chamber wherein the plasma generating means produces plasma inside the chamber, and a heater at the substrate support wherein the heater supplies the substrate with heat.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: November 16, 2004
    Assignees: LG. Philips LCD Co., Ltd.
    Inventors: Jin Jang, Soo-Young Yoon, Jae-Young Oh, Woo-Sung Shon, Seong-Jin Park
  • Patent number: 6802902
    Abstract: A process for producing an epitaxial layer of gallium nitride (GaN). A film of a dielectric whose thickness is about one monolayer is formed on a surface of a substrate. A continuous gallium nitride layer is then deposited on the dielectric film at a temperature sufficiently low to suppress island formation of the gallium nitride. The deposited gallium nitride layer is annealed at a temperature sufficiently high to promote island formation of the gallium nitride. An epitaxial regrowth with gallium nitride at the end of a spontaneous in situ formation of islands of gallium nitride then takes place. This method makes it possible to avoid having to use ex situ etching of masks by photolitographiy or chemical ethching techniques.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: October 12, 2004
    Assignee: Lumilog
    Inventors: Bernard Beaumont, Pierre Gibart, Jean-Claude Guillaume, Gilles Nataf, Michel Vaille, Soufien Haffouz
  • Patent number: 6799888
    Abstract: A test wafer for use in wafer temperature prediction is prepared. The test wafer includes: first semiconductor layer formed in a crystalline state; second semiconductor layer formed in an amorphous state on the first semiconductor layer; and light absorption film formed over the second semiconductor layer. Next, the test wafer is loaded into a lamp heating system and then irradiating the test wafer with a light emitted from the lamp, thereby heating the second semiconductor layer through the light absorption film. Thereafter, a recovery rate, at which a part of the second semiconductor layer recovers from the amorphous state to the crystalline state at the interface with the first semiconductor layer, is calculated. Then, a temperature of the test wafer that has been irradiated with the light is measured according to a relationship between the recovery rate and a temperature corresponding to the recovery rate.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: October 5, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Shibata, Yuko Nambu
  • Patent number: 6784121
    Abstract: A xerogel aging system includes an aging chamber (190) with inlets and outlet and flows a gel catalyst in gas phase over a xerogel precursor film on a semiconductor wafer. Preferred embodiments use an ammonia and water vapor gas mixture catalyst.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: August 31, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Changming Jin, Richard Scott List, Joseph D. Luttmer
  • Patent number: 6758898
    Abstract: The invention relates to a method for growing single crystals of barium titanate [BaTiO3] and barium titanate solid solutions [(BaxM1−x)(TiyN1−y)O3]. This invention is directed to a method for growing single crystals of barium titanate or barium titanate solid solutions showing the primary and secondary abnormal grain growths with increasing temperature higher than the liquid formation temperature, characterized by comprising the step for a few secondary abnormal grains to continue to grow at a temperature slightly below the critical temperature where the secondary abnormal grain growth starts to occur. The method for growing single crystals of barium titanate or barium titanate solid solutions according to this invention has the advantage of providing an effective low cost in manufacturing process for single crystals by using a conventional heat-treatment process without the need of special equipment.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: July 6, 2004
    Assignee: Ceracomp Co. Ltd.
    Inventors: Ho-Yong Lee, Jao-Suk Kim, Jong-Bong Lee, Tae-Moo Hur, Doe-Yeon Kim, Nong-Moon Hwang, Byoung-Ki Lee, Sung-Yoon Chung, Suk-Joong L. Kang
  • Patent number: 6755909
    Abstract: A sequential lateral solidification mask having a first region with a plurality of first stripes that are separated by a plurality of first slits. The mask further includes a second region having a plurality of second stripes separated by a plurality of second slits. The second stripes are perpendicular to the first stripes. A third region having a plurality of third stripes separated by a plurality of third slits, with the third stripes being transversely arranged relative to the first stripes. A fourth region having a plurality of fourth stripes and a plurality of fourth slits between the fourth stripes, with the fourth stripes being transversely arranged relative to the second stripes. Sequential lateral solidification is performed using the mask by multiple movements of the mask and multiple, overlapping irradiations.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: June 29, 2004
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Yun-Ho Jung
  • Patent number: 6743294
    Abstract: Reactive gas is released through a crystal source material or melt to react with impurities and carry the impurities away as gaseous products or as precipitates or in light or heavy form. The gaseous products are removed by vacuum and the heavy products fall to the bottom of the melt. Light products rise to the top of the melt. After purifying, dopants are added to the melt. The melt moves away from the heater and the crystal is formed. Subsequent heating zones re-melt and refine the crystal, and a dopant is added in a final heating zone. The crystal is divided, and divided portions of the crystal are re-heated for heat treating and annealing.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: June 1, 2004
    Assignee: Optoscint, Inc.
    Inventor: Kiril A. Pandelisev
  • Patent number: 6733584
    Abstract: To provide a method of promoting quality of crystals and increasing growth rate in a process of carrying out crystal growth in a horizontal direction of an amorphous silicon film by using a catalyst element expediting crystallization, in respect of the amorphous silicon film for carrying out horizontal growth by using a catalyst element of nickel or the like, irregularities of a matrix (underlayer film or substrate) in contact with the amorphous silicon film are made smaller than the film thickness of the amorphous silicon film by which crystal growth occurs substantially entirely by the catalyst element and interruption of growth caused by natural crystallization or the irregularities of a matrix can be prevented.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: May 11, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Publication number: 20040020423
    Abstract: A three dimensional photonic crystal and layer-by-layer processes of fabricating the photonic crystal. A templated substrate is exposed to a plurality of first microspheres made of a first material, the first material being of a type that will bond to the templated substrate and form a self-passivated layer of first microspheres to produce a first layer. The first layer is exposed to a plurality of second microspheres made of a second material, the second material being of a type that will bond to the first layer and form a self-passivated layer of second microspheres. This layering of alternating first and second microspheres can be repeated as desired to build a three dimensional photonic crystal of desired geometry.
    Type: Application
    Filed: July 31, 2002
    Publication date: February 5, 2004
    Inventors: John South Lewis, Scott Halden Goodwin-Johansson, Brian Rhys Stoner, Sonia Grego, David Edward Dausch
  • Patent number: 6676748
    Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: January 13, 2004
    Assignee: Denso Corporation
    Inventors: Hiroaki Himi, Noriyuki Iwamori
  • Patent number: 6666577
    Abstract: A test wafer for use in wafer temperature prediction is prepared. The test wafer includes: first semiconductor layer formed in a crystalline state; second semiconductor layer formed in an amorphous state on the first semiconductor layer; and light absorption film formed over the second semiconductor layer. Next, the test wafer is loaded into a lamp heating system and then irradiating the test wafer with a light emitted from the lamp, thereby heating the second semiconductor layer through the light absorption film. Thereafter, a recovery rate, at which a part of the second semiconductor layer recovers from the amorphous state to the crystalline state at the interface with the first semiconductor layer, is calculated. Then, a temperature of the test wafer that has been irradiated with the light is measured according to a relationship between the recovery rate and a temperature corresponding to the recovery rate.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: December 23, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Shibata, Yuko Nambu
  • Publication number: 20030211714
    Abstract: A laser irradiation method using a laser crystallization method which can heighten an efficiency of substrate processing as compared to a conventional one and also heighten mobility of a semiconductor film is provided. It is an irradiation method of a laser beam in which, pattern information of a sub-island formed on a substrate is stored, and a beam spot of a laser beam is condensed so as to become linear, and by use of the stored pattern information, a scanning path of the beam spot is determined so as to include the sub-island, and by moving the beam spot along the scanning path, the laser beam is irradiated to the sub-island, characterized in that on the occasion of scanning the beam spot, when the beam spot has reached to the sub-island, the beam spot and the sub-island are contacted at a plurality of points.
    Type: Application
    Filed: December 13, 2002
    Publication date: November 13, 2003
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Chiho Kokubo, Aiko Shiga, Koichiro Tanaka, Hidekazu Miyairi, Koji Dairiki
  • Patent number: 6635110
    Abstract: The invention provides processes for producing a very low dislocation density in heterogeneous epitaxial layers with a wide range of thicknesses, including a thickness compatible with conventional silicon CMOS processing. In a process for reducing dislocation density in a semiconductor material formed as an epitaxial layer upon a dissimilar substrate material, the epitaxial layer and the substrate are heated at a heating temperature that is less than about a characteristic temperature of melting of the epitaxial layer but greater than about a temperature above which the epitaxial layer is characterized by plasticity, for a first time duration. Then the epitaxial layer and the substrate are cooled at a cooling temperature that is lower than the about the heating temperature, for a second time duration. These heating and cooling steps are carried out a selected number of cycles to reduce the dislocation density of the epitaxial layer.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: October 21, 2003
    Assignee: Massachusetts Institute of Technology
    Inventors: Hsin-Chiao Luan, Lionel C. Kimerling
  • Patent number: 6620661
    Abstract: A TFT fabricated from a single crystal grain, and fabrication method has been provided. A large crystal grain is made by precise control of annealment, transition metal concentration, the density of transition metal nucleation sites, and the distance between nucleation sites. In one aspect of the invention, a diffusion layer permits the continual delivery of transition metal at a rate that both supports the lateral growth of di-silicide, and large distances between nucleation sites.
    Type: Grant
    Filed: January 8, 2002
    Date of Patent: September 16, 2003
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Masashi Maekawa, Yukihiko Nakata
  • Patent number: 6616331
    Abstract: A test wafer for use in temperature prediction is prepared. The test wafer includes: first semiconductor layer formed in a crystalline state; second semiconductor layer formed in an amorphous state on the first semiconductor layer; and passivation film formed over the second semiconductor layer. Next, the test wafer is loaded into a device fabrication system and then heated therein at a predetermined period of time. Thereafter, a recovery rate, at which part of the second semiconductor layer recovers from the amorphous state to the crystalline state at the interface with the first semiconductor layer, is calculated. Then, a temperature of the test wafer that has been heated is measured according to a relationship between the recovery rate and a temperature corresponding to the recovery rate.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: September 9, 2003
    Assignee: Matsushita Electric Industrial Co., LTD
    Inventors: Satoshi Shibata, Yuko Nambu
  • Publication number: 20030159644
    Abstract: A process for manufacturing a semiconductor wafer which has superior suitability for mass production and reproducibility. The process comprises the steps of preparing a first member which has a monocrystalline semiconductor layer on a semiconductor substrate with a separation layer arranged therebetween with a semiconductor wafer as the raw material, transferring the monocrystalline semiconductor layer onto a second member which comprises a semiconductor wafer after separating the monocrystalline semiconductor layer through the separation layer, and smoothing the surface of the semiconductor substrate after the transferring step so as to be used as a semiconductor wafer for purposes other than forming the first and second members.
    Type: Application
    Filed: December 3, 1999
    Publication date: August 28, 2003
    Inventors: TAKAO YONEHARA, KUNIO WATANABE, TETSUYA SHIMADA, KAZUAKI OHMI, KIYOFUMI SAKAGUCHI
  • Patent number: 6610142
    Abstract: A process for fabricating a semiconductor at a lower crystallization temperature and yet at a shorter period of time, which comprises forming an insulator coating on a substrate; exposing said insulator coating to a plasma; forming an amorphous silicon film on said insulator coating after its exposure to said plasma; and heat treating said silicon film in the temperature range of from 400 to 650° C. or at a temperature not higher than the glass transition temperature of the substrate. The nucleation sites are controlled by selectively exposing the amorphous silicon film to a plasma or by selectively applying a substance containing elements having a catalytic effect thereto. A process for fabricating a thin film transistor using the same is also disclosed.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: August 26, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Hongyong Zhang, Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 6605321
    Abstract: The invention provides a method of treating a material to cause the material to evolve from one phase to a more ordered phase, the method comprising an operation of irradiating the material in which the irradiating particles are suitable, by their nature and by their energy, for inducing displacements of the atoms in the material towards positions that favor ordering of the material. Advantageously, the invention also provides apparatus for magnetically recording information, the apparatus comprising a material deposited on a substrate at a temperature of less than 350° C. and that has been subjected to irradiation with irradiating particles that are suitable, by their nature and their energy, for inducing displacements of the atoms in the material towards positions that favor relaxation of the material.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: August 12, 2003
    Assignee: Centre National de la Recherche Scientifique (CNRS)
    Inventors: Dafiné Ravelosona-Ramasitera, Claude Chappert, Véronique Mathet, Harry Bernas
  • Publication number: 20030140845
    Abstract: A pressure vessel for processing at least one material in a supercritical fluid. The pressure vessel includes a self-pressurizing capsule for containing at least one material and the supercritical fluid in a substantially air-free environment, a pressure transmission medium surrounding the capsule for maintaining an outer pressure on the capsule, at least one heating element insertable in the pressure transmission medium such that the heating element surrounds the capsule, a temperature measurement means for measuring a temperature of the capsule, a temperature controller for controlling the temperature and providing power to the heating element, a restraint to contain and hold in place the capsule, the pressure transmission medium, and the heating element, and at least one seal between the restraint and the pressure transmission medium for preventing escape of the pressure transmission medium.
    Type: Application
    Filed: January 31, 2002
    Publication date: July 31, 2003
    Applicant: General Electric Company
    Inventors: Mark Philip D'Evelyn, Kristi Jean Narang, Robert Arthur Giddings, Robert Vincent Leonelli, Stephen Lee Dole
  • Patent number: 6582512
    Abstract: A method of forming a periodic index of refraction pattern in a superlattice of a solid material to achieve photonic bandgap effects at desired optical wavelengths is disclosed. A plurality of space group symmetries, including a plurality of empty-spaced buried patterns, are formed by drilling holes in the solid material and annealing the solid material to form empty-spaced patterns of various geometries. The empty-spaced patterns may have various sizes and may be formed at different periodicities, so that various photonic band structures can be produced for wavelength regions of interest.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: June 24, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Joseph E. Geusic, Kevin G. Donohoe
  • Patent number: 6524662
    Abstract: The present invention is related to a method of crystallizing an amorphous silicon layer and a crystallizing apparatus thereof which crystallize an amorphous silicon layer using of electric fields and plasma. The present invention includes the steps of depositing an inducing substance for silicon crystallization on an amorphous silicon layer by plasma exposure, and carrying out annealing on the amorphous silicon layer while applying an electric field to the amorphous silicon layer. The present invention includes a chamber having an inner space, a substrate support in the chamber wherein the substrate support supports a substrate, a plasma generating means in the chamber wherein the plasma generating means produces plasma inside the chamber, an electric field generating means in the chamber wherein the electric field generating means applies electric field to the substrate, and a heater at the substrate support wherein the heater supplies the substrate with heat.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: February 25, 2003
    Assignees: LG. Philips LDC Co., LTD
    Inventors: Jin Jang, Soo-Young Yoon, Jae-Young Oh, Woo-Sung Shon, Seong-Jin Park
  • Patent number: 6482259
    Abstract: The invention relates to a method for growing single crystals of barium titanate [BaTiO3] and barium titanate solid solutions [(BaxM1-x)(TiyN1-y)O3]. This invention is directed to a method for growing single crystals of barium titanate or barium titanate solid solutions showing the primary and secondary abnormal grain growths with increasing temperature higher than the liquid formation temperature, characterized by comprising the step for a few secondary abnormal grains to continue to grow at a temperature slightly below the critical temperature where the secondary abnormal grain growth starts to occur. The method for growing single crystals of barium titanate or barium titanate solid solutions according to this invention has an advantage to provide an effective low cost in manufacturing process for single crystals by using usual heat-treatment process without special equipments.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: November 19, 2002
    Assignee: Ceracomp Co., Ltd.
    Inventors: Ho-Yong Lee, Jae-Suk Kim, Jong-Hong Lee, Tae-Moo Hur, Doe-Yeon Kim, Nong-Moon Hwang, Byoung-Ki Lee, Sung-Yoon Chung, Suk-Joong L. Kang
  • Patent number: 6475815
    Abstract: An amorphous region is formed by implanting an impurity such as As into a semiconductor substrate having a natural oxide film. The amorphous region is divided into a heavily doped oxygen region in which the concentration of oxygen is equal to or higher than a critical value and a lightly doped oxygen region in which the oxygen concentration is lower than the critical value. Then, oxygen ions are implanted to expand the heavily doped oxygen region throughout the amorphous region. Annealing is performed such that the reordering rate of the amorphous region is determined and the annealing temperature is determined by using the relationship between the annealing temperature and the reordering rate. By adjusting the oxygen concentration in the amorphous region to the critical value or more, the reordering rate can be adjusted to a nearly constant low value and the accuracy and reliability of temperature measurement is increased.
    Type: Grant
    Filed: December 8, 1999
    Date of Patent: November 5, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuko Nambu, Satoshi Shibata
  • Patent number: 6471770
    Abstract: A thick GaN layer is grown on sapphire through an Au layer at a temperature lower than the melting point of 1064° C. of the Au layer, and temperature of a sample is raised to reach and exceed the melting point of the Au layer so that the Au layer is dissolved. In this state, the sapphire and GaN layer are separated from each other.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: October 29, 2002
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Seiji Nagai
  • Patent number: 6458199
    Abstract: A crystallization apparatus and method that is adapted to crystallize a semiconductor using a non-vacuum process. In the apparatus and method, laser beams are irradiated onto a substrate to grow a crystal unilaterally from the side surface of the substrate. Grain boundaries are minimized under the air atmosphere, so that a crystallization of the substrate can be made in a non-vacuum state to improve the throughput.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: October 1, 2002
    Assignee: LG. Philips LCD Co., Ltd.
    Inventor: Jin Mo Yoon
  • Patent number: 6451638
    Abstract: A process for fabricating a semiconductor by crystallizing a silicon film in a substantially amorphous state by annealing it at a temperature not higher than the crystallization temperature of amorphous silicon, and it comprises forming selectively, on the surface or under an amorphous silicon film, a coating, particles, clusters, and the like containing nickel, iron, cobalt, platinum or palladium either as a pure metal or a compound thereof such as a silicide, a salt, and the like, shaped into island-like portions, linear portions, stripes, or dots; and then annealing the resulting structure at a temperature lower than the crystallization temperature of an amorphous silicon by 20 to 150° C.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: September 17, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Hideki Uochi, Toru Takayama, Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 6440214
    Abstract: A method of growing a nitride semiconductor layer, such as a GaN layer, by molecular beam epitaxy comprises the step of growing a GaAlN nucleation layer on a substrate by molecular beam epitaxy. The nucleation layer is annealed, and a nitride semiconductor layer is then grown over the nucleation layer by molecular beam epitaxy. The nitride semiconductor layer is grown at a V/III molar ratio of 100 or greater, and this enables a high substrate temperature to be used so that a good quality semiconductor layer is obtained. Ammonia gas is supplied during the growth process, to provide the nitrogen required for the MBE growth process.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: August 27, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Stewart Edward Hooper, Jennifer Mary Barnes, Jonathan Heffernan, Alistair Henderson Kean
  • Patent number: 6436186
    Abstract: According to the invention, a complex (M or M′) formed by stacking in a closely contacted state a single crystal &agr;-SiC base material (1) and a polycrystalline plate (2) which is produced into a plate-like shape by the CVD method with interposing an intermediate layer (4 or 4′) containing Si and O as fundamental components, such as silicon rubber between opposing faces of the two members (1) and (2) in a laminated manner is heat-treated at a temperature of 2,200° C. or higher, and under a saturated SiC vapor pressure, thereby causing polycrystal members of the polycrystalline plate (3) to be transformed in a same direction as single crystal of the single crystal &agr;-SiC base material (1) to integrally grow single crystal. Therefore, single crystal SiC of a high quality in which crystal defects and distortion are prevented from occurring and micropipe defects hardly occur can be produced easily and efficiently.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: August 20, 2002
    Assignee: Nissin Electric Co., Ltd.
    Inventors: Kichiya Tanino, Masanobu Hiramoto
  • Patent number: 6423585
    Abstract: To provide a method and a device for subjecting a film to be treated to a heating treatment effectively by a lamp annealing process, ultraviolet light is irradiated from the upper face side of a substrate where the film to be treated is formed and infrared light is irradiated from the lower face side by which the lamp annealing process is carried out. According to such a constitution, the efficiency of exciting the film to be treated is significantly promoted since electron excitation effect by the ultraviolet light irradiation is added to vibrational excitation effect by the infrared light irradiation and strain energy caused in the film to be treated by the lamp annealing process is removed or reduced by a furnace annealing process.
    Type: Grant
    Filed: March 10, 1998
    Date of Patent: July 23, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Publication number: 20020046693
    Abstract: A method of growing a nitride semiconductor crystal which has very few crystal defects and can be used as a substrate is disclosed. This invention includes the step of forming a first selective growth mask on a support member including a dissimilar substrate having a major surface and made of a material different from a nitride semiconductor, the first selective growth mask having a plurality of first windows for selectively exposing the upper surface of the support member, and the step of growing nitride semiconductor portions from the upper surface, of the support member, which is exposed from the windows, by using a gaseous Group 3 element source and a gaseous nitrogen source, until the nitride semiconductor portions grown in the adjacent windows combine with each other on the upper surface of the selective growth mask.
    Type: Application
    Filed: November 8, 2001
    Publication date: April 25, 2002
    Applicant: NICHIA CHEMICAL INDUSTRIES, LTD.
    Inventors: Hiroyuki Kiyoku, Shuji Nakamura, Tokuya Kozaki, Naruhito Iwasa, Kazuyuki Chocho
  • Patent number: 6373091
    Abstract: A memory cell which comprises a substrate having a top surface; a capacitor extending vertically into the substrate for storing a voltage representing a datum, said capacitor occupying a geometrically shaped horizontal area; a transistor formed above the capacitor and occupying a horizontal area substantially equal to the geometrically shaped horizontal area, and having a vertical device depth, for establishing an electrical connection with the capacitor, in response to a control signal, for reading from, and writing to, the capacitor, wherein the transistor includes a gate formed near the periphery of said horizontal device area and having a vertical depth approximately equal to the vertical device depth; an oxide layer on an inside surface of the gate; a conductive body formed inside the oxide layer, said conductive body having a top surface and a bottom surface and a vertical depth approximately equal to the vertical device depth; and diffusion regions in the body near the top and bottom surfaces and a met
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: April 16, 2002
    Assignee: International Business Machines Corporation
    Inventors: David Vaclav Horak, Rick Lawrence Mohler, Gorden Seth Starkey, Jr.
  • Patent number: 6372039
    Abstract: A method and device for irradiating a pulse laser beam having a linear shape and a rectangular shape beam spot onto a non-single crystal semiconductor thin film. The method includes scanning the pulse laser beam so that previous and next beam spots are partially overlapped.
    Type: Grant
    Filed: March 22, 1999
    Date of Patent: April 16, 2002
    Assignee: NEC Corporation
    Inventors: Hiroshi Okumura, Hiroshi Tanabe
  • Patent number: 6358313
    Abstract: A method of manufacturing a crystalline silicon base semiconductor thin film on a substrate, includes the steps of forming a thin film primarily made of silicon on the substrate by forming plasma of a film material gas containing at least a silicon base gas at the vicinity of the substrate; and crystallizing the silicon in the thin film primarily made of the silicon by emitting excited particles produced from an excited particle material gas to the substrate. At least one of the film material gas and the excited particle material gas contains an impurity gas for forming the silicon semiconductor, and thereby the crystalline silicon base semiconductor thin film is formed on the substrate.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: March 19, 2002
    Assignees: Sharp Kabushiki Kaisha, Nissin Electric Co., Ltd.
    Inventors: Shuhei Tsuchimoto, Hirohisa Tanaka, Kiyoshi Ogata, Hiroya Kirimura
  • Patent number: 6350311
    Abstract: A method for growing an epitaxial silicon-germanium layer is described. The method includes removing a native oxide layer on the silicon substrate surface. A HF vapor treatment process is then conducted on the silicon substrate. Thereafter, a germanium layer is formed on the silicon substrate, followed by performing a rapid thermal anneal process under an inert gas to form a silicon-germanium alloy layer on the surface of the silicon substrate.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: February 26, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Feng-Der Chin, Ming-Jang Hwang
  • Patent number: 6348369
    Abstract: A laser-annealing method includes the steps of a first step of cleaning a non-monocrystal silicon film formed on a substrate, and a second step of laser-annealing the non-monocrystal silicon film in an atmosphere containing oxygen therein, wherein the first and second steps are conducted continuously without being exposed to the air. Also, a laser-annealing device includes a cleaning chamber, and a laser irradiation chamber, wherein a substrate to be processed is transported between the cleaning chamber and the laser irradiation chamber without being exposed to the air.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: February 19, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Naoto Kusumoto, Toru Takayama, Masato Yonezawa
  • Patent number: 6346437
    Abstract: A TFT fabricated from a single crystal grain, and fabrication method has been provided. A large crystal grain is made by precise control of annealment, transition metal concentration, the density of transition metal nucleation sites, and the distance between nucleation sites. In one aspect of the invention, a diffusion layer permits the continual delivery of transition metal at a rate that both supports the lateral growth of di-silicide, and large distances between nucleation sites.
    Type: Grant
    Filed: July 16, 1998
    Date of Patent: February 12, 2002
    Assignees: Sharp Laboratories of America, Inc., Sharp Kabushiki Kaisha
    Inventors: Masashi Maekawa, Yukihiko Nakata
  • Patent number: 6344082
    Abstract: Si nanocrystals are formed by irradiating SiO2 substrates with electron beams at a temperature of 400° C. or higher, thereby causing electron-stimulated decomposition reaction. As a result of the said reaction, single crystalline Si nanostructures are fabricated on the SiO2 substrate with good size and positional controllability.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: February 5, 2002
    Assignee: Japan Agency of Industrial Science and Technology as represented by Director General of National Research Institute for Metals
    Inventors: Kazuo Furuya, Masaki Takeguchi, Kazuhiro Yoshihara
  • Patent number: 6299681
    Abstract: A polycrystalline article is converted to a single crystal in a solid-state process. Heat is applied at a first end of the article to effect a predetermined spatial temperature profile thereat having a maximum temperature approaching a melting temperature thereof. The temperature profile is maintained to initiate conversion at the first end. The heat is moved along the article toward an opposite second end to correspondingly propagate the conversion along the article.
    Type: Grant
    Filed: November 27, 1998
    Date of Patent: October 9, 2001
    Assignee: General Electric Company
    Inventors: Farzin Homayoun Azad, Marshall Gordon Jones
  • Patent number: 6294016
    Abstract: Disclosed is a method for manufacturing a high conductivity p-type GaN-based thin film superior in electrical and optical properties by use of nitridation and RTA (rapid thermal annealing) in combination. A GaN-based epitaxial layer is grown to a desired thickness while being doped with Mg dopant with a carrier gas of hydrogen by use of a MOCVD process. The film thus obtained is subjected to nitridation using nitrogen plasma and RTA in combination. The p-type GaN-based thin film exhibits high hole concentration as well as low resistivity, so that it can be used where high electrical, optical, thermal and structural properties are needed. The method finds application in the fabrication of blue/white LEDs, laser diodes and other electronic devices.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: September 25, 2001
    Assignee: Kwangju Institute of Science and Technology
    Inventors: Sang Woo Kim, Ji Myon Lee, Kwang Soon Ahn, Rae Man Park, Ja Soon Jang, Seong Ju Park
  • Publication number: 20010017099
    Abstract: A thick GaN layer is grown on sapphire through an Au layer at a temperature lower than the melting point of 1064° C. of the Au layer, and temperature of a sample is raised to reach and exceed the melting point of the Au layer so that the Au layer is dissolved. In this state, the sapphire and GaN layer are separated from each other.
    Type: Application
    Filed: December 27, 2000
    Publication date: August 30, 2001
    Inventors: Masayoshi Koike, Seiji Nagai
  • Patent number: 6270571
    Abstract: A method for producing narrow wires including titanium oxide of high crystallinity and diameter of the order of nanometer, in particular whiskers of titanium oxide, and including a first step of preparing a base having a titanium-including surface, second step of discretely depositing a material other than titanium over the above surface, and third step of thermally treating the above surface, obtained by the second step, in a titanium-oxidizing atmosphere.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: August 7, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tatsuya Iwasaki, Tohru Den
  • Publication number: 20010009134
    Abstract: GaN system compound semiconductor and method for growing a crystal thereof, which can significantly reduce a concentration of crystalline defects caused by lattice mismatch by growing a GaN system compound semiconductor of GaN or InxGa1-xN by using InxAl1-xN crystal on a substrate as an intermediate buffer layer, the method including the steps of (1) providing a sapphire substrate, (2) growing an intermediate buffer layer of InxAl1-xN on the sapphire substrate, and (3) growing GaN or InxGa1-xN system compound semiconductor on the intermediate buffer layer.
    Type: Application
    Filed: February 28, 2001
    Publication date: July 26, 2001
    Applicant: LG Electronics Inc.
    Inventors: Chin Kyo Kim, Tae Kyung Yoo