Abstract: More than two isoelectronic impurities are doped in a host crystal of compound semiconductors of groups III-V.An impurity atom forms a covalent bond with a host atom. Although the real bond length "A" between an impurity and a host atom in the crystal cannot be measured, it can be surmised from the bond length "a" between two atoms in a pure two-component crystal consisting of the elements same with the impurity atom and the host atom. The bond length between host atoms in the crystal is called standard bond length "a.sub.0 ". Definite and measurable bond length "a" replaces the real unknown bond length "A". The impurity whose replaced bond length "a.sub.1 " is shorter than "a.sub.0 " is called an under-impurity. The impurity whose replaced bond length "a.sub.2 " is longer than "a.sub.0 " is called an over-impurity.In this invention at least one under-impurity and at least one over-impurity are doped in the host single crystal. From the concentrations "x.sub.1 " and "x.sub.

Abstract: A thin conducting line such as a gate pattern is defined on a semiconductor chip (10) by applying a narrow ion beam, suitably a focused-ion-beam (16) having a submicrometer thickness from a source (18) onto a thin layer (14) of an inorganic material such as silicon or aluminum overlying a layer (12) of refractory metal on a substrate (11). The ion beam is translated to form a gate pattern at a dose between about 0.1 to 50.times.10.sup.15 cm.sup.-2 and an energy from about 1 to 1000 KeV. Ions are implanted into the silicon and aluminum layers and into the underlying portions of the refractory metal layer and to render the exposed portions of the layers preferentially resistant to wet-etchant. The portions of layers which are not exposed nor protected by layers which are exposed, are preferentially removed to form a gate. Conventional MOSFET or MESFET processing to implant ions to form source and drain regions may then be performed.

Abstract: A method for fabricating polysilicon of reduced resistance that may be incorporated in silicon integrated chip manufacturing processes which comprises coating a wafer bearing dielectrically isolated islands with an isolating layer, and depositing thereover a layer of polysilicon. On the surface of the polysilicon layer, a masking layer is formed, and coated with a metallic reflective layer. The portion of the reflective layer, and, optionally, the masking layer, overlaying the interisland area is removed, and the wafer is then exposed to a laser beam, transforming the polysilicon layer into the appropriate resistor material. The remaining metallic and/or masking layer may then be removed, the device exposed to a laser beam again, thereby transforming the polysilicon across the entire surface.

Abstract: An improved large surface, quasi-monocrystalline silicon crystal bodies of the type used in solar cells. The bodies are produced by reacting at least the surface of a carbon fiber fabric with molten silicon under conditions of temperature and viscosity sufficient to cause the molten silicon to penetrate the fabric and produce silicon carbide at at least the surface of the fibers, and immediately thereafter coating the thus reacted fabric with metallic silicon from a second molten silicon bath to produce a silicon coating.

Abstract: Seed crystals are made in a region of a polycrystalline layer on a substrate by melting the region and then cooling it so that it solidifies from one end to the other in a first direction and outwardly toward the edges in a second direction normal to the first direction. The desired cooling pattern is established by providing a thermal layer under the polycrystalline layer, which thermal layer is used to provide different rates of heat conduction therethrough in different parts of the thermal layer. A large, single-crystal device can be made by providing an operating layer of polycrystalline material in contact with the seed, melting the operating layer and recrystallizing it so that its solidification proceeds from the seed. The thermal layer can be used to ensure the desired direction of resolidification by providing different rates of heat conduction therethrough in different parts of the thermal layer.

Abstract: Small scale integrated chips are fabricated from a semiconductor wafer and subsequently pretested and formed into large area arrays with self aligning and self locking characteristics due to the axial orientation of the semiconductor wafer and geometries employed for the chips based upon the wafer orientation, whereby the spacing of abutting chip edges in an array may be less than 7 .mu.m. The chips are fabricated from <110> axial wafer, e.g., silicon <110> axial wafer, wherein the chip boundaries are aligned with vertical {111} planes of the crystalline material so that each of the chips formed from the wafer may be defined within parallelogrammatic like geometries defined by these planes and their intersections. The term "parallelogrammatic like geometries" means all geometric shapes capable of being formed with various vertical {111} planes within the crystalline structure of the wafer.

Abstract: The production of improved photoresponsive amorphous alloys and devices, such as photovoltaic, photoreceptive devices and the like. The alloys and devices have improved wavelength threshold characteristics made possible by introducing one or more band gap adjusting elements and dopants into the alloys and devices in layers and/or clusters. The dopants and adjusting element or elements are added to the amorphous devices containing silicon and at least one reducing element, such as hydrogen. One adjusting element is germanium which narrows the band gap from that of the materials without the adjusting element incorporated therein. Other adjusting elements can be used such as tin or nitrogen along with conventional dopants. The silicon and adjusting elements are concurrently combined and deposited as amorphous alloys by vapor deposition, sputtering or glow discharge decomposition.

Abstract: The invention provides an SOS substrate for a semiconductor device wherein an epitaxial silicon layer which has an index of plane (100) is formed on a single crystal sapphire plate which has an index of plane (1012). An orientation flat is formed at an incline angle of 2.1 to 2.2.degree. with respect to a [011] or [011] direction on the surface of the epitaxial silicon layer which has the index of plane (100). The direction of the orientation flat on the surface of the sapphire plate is aligned with the direction of a cleavage plane of the sapphire plate.

Abstract: A method is provided for manufacturing a semiconductor device, comprising the steps of forming alignment marks on a side surface of a semiconductor wafer, aligning the semiconductor wafer with a unit apparatus for manufacturing the semiconductor device utilizing the alignment mark, and processing the semiconductor wafer with the unit apparatus. The alignment mark attached on the side surface of the wafer can be identified even if chip patterns or various films are formed on the wafer.

Abstract: A photovoltaic cell and the method of manufacturing the same. The cell includes a substrate of, e.g., aluminum, having a layer of cesium fluoride-like material with the outer surface thereof containing a p+ boron doped outer layer. A substantially transparent electrically conductive coating is applied over the surface of said cesium fluoride-like material and appropriate electrical contacts are made to the conductive layer for protective purposes.

Abstract: An epitaxial composite comprising a thin film of single crystal Group III-V wide band-gap compound semiconductor or semiconductor alloy on single crystal, electrically insulating oxide substrates such as sapphire, spinel, BeO, ThO.sub.2, or the like, and on III-V semiconductors or alloys. The thin film may be produced in situ on a heated substrate by reaction of an organic compound containing the Group III constituent, typically tfhe alkyl metal organic, such as trimethylgallium and/or triethylgallium with a Group V hydride such as arsine, phosphine and/or stibine.

Abstract: A substrate is made for silicon solar cells by heating a sheet of large-grained silicon steel at a temperature of at least about 1300.degree. C. in an atmosphere of hydrogen and tungsten hexafluoride (or hexachloride) at a partial pressure ratio of hydrogen to tungsten hexafluoride of about 3 to about 6 to deposit an epitaxial layer of tungsten on said sheet of silicon steel. Epitaxial silicon can then be deposited in a conventional manner on the layer of epitaxial tungsten.

Abstract: Rutile, lead zirconate and barium titanate are employed as a filler material in a polymeric material to improve the electrical characteristics thereof for use as a surface coating on semiconductor devices.

Abstract: A method is disclosed for producing single-crystal semiconductor films. A thin layer of semiconductor single-crystal material is grown on a substrate having a lower melting point temperature than the layer material. The substrate and layer are heated in an oven to the melting point temperature of the substrate. Laser radiation of a wavelength absorbed by the layer is impinged on the layer, thereby generating heat in the layer and raising its temperature. Heat then flows to the substrate where it is absorbed, as is any transmitted radiation. Liquification of substrate material at the interface of the substrate with the layer results. Following such liquification, the layer is locally separated from the substrate. As the laser radiation is swept along the layer, the layer (film) is progressively removed from the substrate, until the film is entirely separated.

Abstract: A single crystal substrate for epitaxial growth thereon of a semiconductor layer. The substrate consists essentially of sapphire (aluminum oxide) and magnesium titanium oxide (MgTiO.sub.3). The invention also provides the aforesaid single crystal substrate in combination with a semiconductor epitaxially grown thereon. The preferred semiconductors are silicon, gallium phosphide, aluminum phosphide and zinc sulphide.

Abstract: A single crystal substrate for epitaxial growth thereon of a semiconductor layer. The substrate consists essentially of sapphire (aluminum oxide) and scandium oxide (Sc.sub.2 O.sub.3). The invention also provides the aforesaid single crystal substrate in combination with a semiconductor epitaxially grown thereon. The preferred semiconductors are silicon, gallium phosphide, aluminum phosphide and zinc sulphide.

Abstract: Semiconductor devices using chemically treated n-type GaAs have greatly reduced surface recombination velocities. A preferred embodiment uses fractional monolayers of ruthenium on the GaAs surface.

Abstract: An epitaxial wafer of GaAs.sub.1-x P.sub.x has been doped with nitrogen and used for the production of light emitting diode (LED). The carrier concentration of the conventional GaAs.sub.1-x P.sub.x was from 3.times.10.sup.16 to 2.times.10.sup.17 /cm.sup.3.According to the present invention, the carrier concentration is reduced lower than the conventional concentration and the luminance of LED is increased approximately two or three times the conventional luminance.

Abstract: The basewidth of a lateral, bipolar transistor is markedly reduced by first forming a layer of polycrystalline silicon over an oxide coated substrate. By utilizing a process for doping the exposed edges of the patterned polysilicon layer, a narrower basewidth dimension is achieved than heretofore possible with photolithographic techniques.

Abstract: Thin layers of polycrystalline n-type GaAs have been deposited on a conducting substrate such as graphite. These contacted GaAs layers exhibit desirable properties for device applications, i.e., adequate cohesion between the GaAs and the substrate, good electrical contact to the conducting substrate, and good nucleation of the GaAs on the substrate yielding pinhole free or near pinhole free GaAs layers composed of large grains. These properties are obtained by first depositing a very thin coating, a coating with a nominal thickness between 1000 A and 250 A, of a Group IV element, Ge, Si, or Sn, onto the conducting substrate and then depositing the GaAs over this thin layer.

Abstract: The self-aligning characteristics of surface-active molecules are used to provide a multiply-coupled thin film surface coating on a substrate, comprising an outermost layer of normally fluid, flexible backbone chain polymer units of at least about 30 atoms in length, the ends of which are attached by chemical bonds to a relatively highly polar second layer of atoms serving to anchor the relatively fluid outer surface layer polymer chains to the surface of the substrate.

Abstract: A foraminous sheet of carrier substrate is contacted, by full or partial immersion, with a bath of molten silicon to form a sheet of material in which the foramina are filled with silicon and at least one surface of the sheet is coated with silicon. The coated sheet is suitable for use in forming a photovoltaic cell.

Abstract: A foraminous sheet of carrier substrate is formed by immersing the sheet in a bath of molten silicon. After cooling, the coated sheet is suitable for use in making a photovoltaic cell.

Abstract: A body of semiconductor material to be processed by thermal gradient zone melting (TGZM) has an outer side peripheral surface beveled at a predetermined included angle .alpha. with the bottom surface of the body in order that the radiant heat impinging on the beveled side peripheral surface is equal to the radiant heat emitted by the beveled side peripheral surface of the body.

Abstract: Disclosed is a single phase crystalline alloy of silicon and gallium arsenide and methods of making same. The alloy is compounded by reacting elemental gallium, arsenic and silicon in the atomic stoichiometry desired to produce a material which is transmissive in the infrared wavelengths.

Abstract: Thermal gradient zone melting (TGZM) is employed to make a semiconductor magnetoresistor device embodying a plurality of spaced highly conductive planar metallic-like electrodes formed in situ by TGZM to maximize the increase in the current path in a magnetic field established in the device.

Abstract: In a semi-insulating gallium arsenide single crystal containing at least one of deep acceptor impurities and at least one of deep donor impurities and having a resistivity of at least about 10.sup.6 .OMEGA..multidot.cm at 300 .degree. K., (1) at least one of the deep donor impurities is oxygen, the oxygen concentration in the single crystal being at least about 4.times.10.sup.16 cm.sup.-3, while the silicon concentration in the single crystal being simultaneously at most about 2.times.10.sup.15 cm.sup.-3, (2) at least one of the deep acceptor impurities is chromium, the chromium concentration in the single crystal being within a range of about 3.times.10.sup.15 to about 3.times.10.sup.17 cm.sup.-3 and (3) at least one of tellurium, tin, selenium and sulfur is contained as another shallow donor impurity than silicon so to satisfy the relationship of N.sub.AA >N.sub.D -N.sub.A >-N.sub.DD wherein N.sub.AA represents the sum of concentrations of the deep acceptor impurities including chromium, N.sub.

Abstract: CCDs and bipolar transistors are formed together on a silicon chip. For n channel CCDs and npn transistors, only a single extra diffusion is necessary in addition to the diffusions used for the CCDs alone. This step is diffusion of n.sup.+ collector wells, and is performed before CCD channel stop-transistor base diffusion. For p channel CCDs and pnp transistors, two extra diffusions are necessary and are: diffusion of a p collector wells, and diffusion of n.sup.+ base contracts; the extra diffusions may both be performed before CCD channel stop-transistor base diffusion, or the n.sup.+ base contact diffusion may be performed thereafter.

Abstract: Gettered semiconductor wafers for integrated circuit device manufacture are prepared by grinding a layer of damage into the back face of the wafer to a depth of about 8-35 microns, heating the wafer to a temperature of about 800.degree.-1150.degree. C. for about 1 to 3 hours and quickly cooling the wafer to a temperature below about 600.degree. C., and polishing both sides of the wafer to form a polished, substantially damage-free front face and a smooth back face which has a residual layer of crystallographic damage to provide additional gettering during device manufacture.

Abstract: A method for forming N conductivity-type regions in a silicon substrate comprising ion implanting arsenic to form a region in said substrate having an arsenic atom concentration of at least 1 .times. 10.sup.-2 As atoms/total atoms in substrate, and ion implanting germanium into said substrate region. Even though the atomic radius of arsenic is very close to that of silicon -- the arsenic radius is only 0.5% smaller -- when high arsenic atom concentrations of at least 1 .times. 10.sup.-2 atoms/total atoms in the substrate are introduced in the substrate, and such high concentrations are only possible when arsenic is ion implanted, then atomic misfit dislocations will occur. The implanted germanium atoms compensate for the lattice strain in the silicon to minimize dislocations.

Abstract: The ultra-miniaturized, active solid-state devices and circuitries have unique material bodies having signal-translating regions attached thereto for active signal translation. These regions, comprising melt-grown, or simulated melt-grown, metallurgical compounds including oxides, eutectics, and intermetallics, are of controlled compositions, concentration profiles, and electronic or other optoelectromagnetic properties. In some devices, the microstructure of the compounds comprises a plurality of microscopically thin, regularly-shaped and uniformly-spaced bodies of one phase material dispersed in a matrix of another phase material. The electronic conductivity of the bodies is substantially different from that of the matrix, and the bodies all terminate at microscopic distance from the pn junction (or other interfacial rectifying barrier region), so as to confine the signal current carriers to flow mainly in only one of the phases. This achieves carriers microstreaming or microbranching effects.

Abstract: A NTD semiconductor material comprising polycrystalline silicon having a mean grain size less than 1000 microns and containing phosphorus dispersed uniformly throughout the silicon rather than at the grain boundaries.

Abstract: An improved contact material for use in the fabrication of semiconductor devices is provided. This material comprises one of the mercury chalcogenides. The application of this material to a nondegenerate semiconductor may be made by the process of evaporation. The resulting contact is stable in the atmosphere, and is more electronegative than the best contact material, namely gold, that is now used.

Abstract: A method of adjusting the donor concentration in a body of mercury cadmium telluride, or in regions of a body, comprising the steps of contacting the donor material region with a donor material of either aluminum or silicon and heating the body at a temperature of at least 550.degree. C for sufficient time to diffuse the donor material into the body. In a preferred embodiment, the heating is done in the presence of a source of mercury vapor pressure other than the body of semiconductor.

Abstract: Mercury cadmium telluride is described having a quantity of a silicon dispersed therein in an amount to measurably increase the donor concentration of the mercury cadmium telluride. Silicon has been found to substitute for metal, either mercury or cadmium, in the mercury cadmium telluride crystal. Doping of a region of mercury cadmium telluride with silicon can produce a PN junction when the adjacent region is P-type, and an N-N+ type junction when the adjacent region is N-type.

Abstract: Mercury cadmium telluride carrier concentration can be adjusted by having a quantity of lithium dispersed therein in an amount sufficient to measurably increase the acceptor concentration of the semiconductor. Methods of forming the acceptor doped mercury cadmium telluride include diffusion of a quantity of lithium into an already existing body of mercury cadmium telluride. Formation of NP junctions and P-P+ regions are disclosed using the compositions and methods of the present invention.

Abstract: Mercury cadmium telluride is disclosed having a quantity of a halogen donor material preferably selected from the group consisting of bromine and iodine dispersed therein in an amount sufficient to measurably increase the donor concentration. Also disclosed are PN junctions formed using this donor material. A method of introducing the donor material is additionally disclosed.

Abstract: The preparation of a semiconductor substrate for epitaxial deposition and the deposition of a solution from which the epitaxial film is formed is carried out at room temperature. The solution is deposited on the condensing surface in two discrete layering operations, the first of which ensures complete wetting of the condensing surface, the second of which ensures junction formation at a prescribed depth. The procedure is particularly useful in forming P Type epitaxial films on N-Type gallium phosphide substrates.

Abstract: A semiconductor device comprising a semiconductor body portion having a shallow surface layer which is higher doped than the bulk of the semiconductor body portion, and a metal electrode on this layer and forming a Schottky barrier with the body portion. The layer serves to control the effective height of the barrier. The depth of the layer is such that the layer is substantially depleted of charge carriers in the zero bias condition whereby the slope of the reverse current-voltage characteristic of the barrier below break-down is determined by the doping of the bulk of the body portion substantially independently of the presence of the layer. Depending on the conductivity type of the layer relative to the bulk, the barrier can be higher or lower than that which would be formed in the absence of this layer. By providing the layer by implantation good control of the doping and hence of the barrier height can be obtained. Applicable to both discrete Schottky diodes and Schottky barriers in integrated circuits.

Abstract: Process of the removal of point defects and point defect agglomerates from emiconductor discs, which comprises the steps of providing one side of the discs with a mechanical stress field and then subjecting the discs to a heat treatment.

Abstract: A multilayer passivation-encapsulation for a semiconductor element is provided by a suitable polymer layer disposed on the device and overcoated with a glass layer for hermeticity.

Abstract: A method for making a four-layer P+PNN+ or N+NPP+ diode, and the diode, wherein the impurity profile about the PN junction is optimally graded for TRAPATT operation throughout the span of the avalanche region by ion implantation of the impurities to a depth of 1000A in a semiconductor wafer and wherein these impurities are subsequently thermally diffused.

Abstract: A method of manufacturing a hetero junction by epitaxial deposition in a solution.The solution contains an amphoteric dopant and the composition thereof is modified at a temperature which lies between the transition temperatures prior to and after the modification.Application to electroluminescent devices of III and V type.

Abstract: Crystalline silicon wafers have an electrical junction formed at a surface thereof by impregnating the surface with a diffusant, such as phosphorus, in an atmosphere that includes significant quantities of helium.

Abstract: A process for forming a monolithic gallium arsenide structure having a plurality of electrically insulated gallium arsenide regions.

Abstract: A multilayer passivation-encapsulation for a semiconductor element is provided by a suitable polymer layer disposed on the device and overcoated with a glass layer for hermeticity.

Abstract: A contact of an indium gallium arsenide alloy forms an ohmic contact with a body of n-type or p-type single crystal gallium arsenide of a resistivity of 1 ohm-cm or greater. The method for forming the contact utilizes a low temperature range. This low temperature range lessens the amount of surface disassociation and aids in the prevention of contamination of the body of gallium arsenide.

Abstract: A semiconductor light source on the basis of n-type silicon carbide single crystal, wherein an epitaxial silicon carbide film of the same type is disposed on the basic single crystal, a p-n junction with a depth of 0.1-2 .mu.m is arranged on the surface of this film, the basic silicon carbide single crystal having a concentration of uncompensated donor atoms of 5.sup.. 10.sup.17 - 5.sup.. 10.sup.18 cm.sup.-.sup.3 and a concentration of atoms of secondary impurities not greater than 2.sup.. 10.sup.18 cm.sup.-.sup.3, while the epitaxial film has a concentration of uncompensated donor atoms of 0.8.sup.. 10.sup.18 -3.sup.. 10.sup.18 cm.sup.-.sup.3, a concentration of atoms of secondary impurities of 0.4.sup.. 10.sup.17 -1.5.sup.. 10.sup.17 cm.sup.-.sup.3 and a thickness of 5-100 .mu.m.

Abstract: A method of producing light emitting diodes of high quantum efficiency in mass production by utilizing an epitaxial deposition from a small size melt such that the substrate itself serves as a saturation source. A silicon doped gallium arsenide wafer is cleaned and etched by normal means and subsequently the wafer is precoated with a properly doped gallium master melt. The coated wafers are inserted into an epitaxial furnace and the gallium master melt effects solution of a portion of the gallium arsenide monocrystal substrate and finally the entire wafer is cooled, maintaining a temperature gradient causing epitaxial growth on the substrate.

Abstract: A method of setting the lifetime of charge carriers in a semiconductor body by the formation of recombination centers in the semiconductor body. The quantity of the recombination centers forming material necessary to provide the desired concentration in the semiconductor body is applied to the surface of the semiconductor body and into the surface thereof by ion implantation, and thereafter, in order to diffuse the material into the semiconductor body, the body is heated until an approximately stationary value for the charge carrier lifetime has developed in the entire volume of the body.