Polycrystalline Diffuse Anneal Patents (Class 148/DIG123)
  • Patent number: 5981321
    Abstract: A method of forming shallow junctions in a CMOS transistor is disclosed. The method comprises the steps of: (a) forming a diffusion source layer on a N-well region, a P-well region, field oxide layer, and the gates of a CMOS transistor; (b) forming a photoresist layer over the P-well region; (c) carrying out p-type ion implantation to dope a part of the diffusion source layer on the P-well region; (d) removing the photoresist layer on the P-well region; (e) forming a photoresist layer over the N-well region; (f) carrying out n-type ion implantation to dope the other part of the diffusion source layer on the N-well region; (g) removing the photoresist layer on the N-well region; and (h) oxidizing the diffusion source layer and driving the ions therein into the P-well and N-well regions to form shallow junctions, respectively. The present invention has several advantages. First, it is compatible with the conventional CMOS process.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: November 9, 1999
    Assignee: National Science Council
    Inventor: Tien-Sheng Chao
  • Patent number: 5970335
    Abstract: A semiconductor processing method of forming complementary first conductivity type doped and second conductivity type doped active regions within a semiconductor substrate includes, a) providing a semiconductor substrate; b) masking a desired first conductivity type region of the substrate while conducting second conductivity type doping into a desired second conductivity type active region of the substrate; c) providing an insulating layer over the substrate over the desired first conductivity type region and the second conductivity type doped region; d) patterning the insulating layer to provide a void therethrough to the desired first conductivity type region; e) filling the void with a first conductivity type doped polysilicon plug, the plug having a first conductivity type dopant impurity concentration of at least 1.times.10.sup.20 ions/cm.sup.
    Type: Grant
    Filed: February 7, 1997
    Date of Patent: October 19, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Mark Helm, Charles Dennison
  • Patent number: 5801087
    Abstract: The method of the present invention introduces a method of forming conductively doped contacts on a supporting substrate in a semiconductor device that minimizes the lateral out-diffusion of the conductive dopants and also provides for a low resistive contact by the steps of: preparing a conductive area to accept contact formation; forming a phosphorus insitu doped polysilicon layer over the conductive area; forming an arsenic insitu doped polysilicon layer over the phosphorus insitu doped polysilicon layer, wherein the two insitu doped polysilicon layers are deposited one after another in separate deposition steps; and annealing the layers at a temperature range of approximately 900.degree.-1100.degree. C. thereby, resulting in sufficient thermal treatment to allow phosphorus atoms to break up a first interfacial silicon dioxide layer formed between the conductive area and the phosphorus insitu doped polysilicon layer.
    Type: Grant
    Filed: January 3, 1996
    Date of Patent: September 1, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Monte Manning, Shubneesh Batra, Charles H. Dennison
  • Patent number: 5541134
    Abstract: A merged BiCMOS device 10 having a bipolar transistor 60 and a PMOS transistor 64 formed in the same well region 18a. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18b. Emitter electrode 30 is separated from base region 26 by thick oxide 24. PMOS transistor 64 comprises source/drain regions 52 and 52a, gate electrode 40, and gate oxide 36. PMOS transistor 64 may also comprises LDD regions 44. Source/drain region 52a is in contact with base region 26. If desired, the emitter electrode 30 and gate electrode 40 may be silicided.
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: July 30, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Robert H. Eklund
  • Patent number: 5541137
    Abstract: The method of the present invention introduces a method of forming conductively doped contacts on a supporting substrate in a semiconductor device that minimizes the lateral out-diffusion of the conductive dopants and also provides for a low resistive contact by the steps of: preparing a conductive area to accept contact formation; forming a phosphorus insitu doped polysilicon layer over the conductive area; forming an arsenic insitu doped polysilicon layer over the phosphorus insitu doped polysilicon layer, wherein the two insitu doped polysilicon layers are deposited one after another in separate deposition steps; and annealing the layers at a temperature range of approximately 900.degree.-1100.degree. C. thereby, resulting in sufficient thermal treatment to allow phosphorus atoms to break up a first interfacial silicon dioxide layer formed between the conductive area and the phosphorus insitu doped polysilicon layer.
    Type: Grant
    Filed: October 27, 1994
    Date of Patent: July 30, 1996
    Assignee: Micron Semiconductor Inc.
    Inventors: Monte Manning, Shubneesh Batra, Charles H. Dennison
  • Patent number: 5496744
    Abstract: In a method of manufacturing a bipolar transistor by forming emitter regions of PNP and NPN transistors with diffusion of impurity from the polycrystalline silicon film into the substrate, the B-doped polycrystalline silicon film is deposited on the interlayer insulating film in which the emitter holes of the PNP and NPN transistors are made. Further, the interlayer insulating film is deposited on this film, and the portion of the insulating film which situated on the NPN transistor region is removed. Then, the thermal treatment is carried out in a high-concentration P atmosphere, so as to change the portion of the film which is located on the NPN transistor region to a P-doped polycrystalline silicon film. With this thermal treatment, the P-type and N-type emitter diffusion regions are formed on the base regions of the PNP and NPN transistors.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: March 5, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazunari Ishimaru
  • Patent number: 5476799
    Abstract: A process for preparing a semiconductor device forms an insulating thin film capable of tunnelling phenomenon of carriers on a semiconductor substrate and forms a polycrystalline semiconductor layer on the thin film. An impurity is injected to the surface of the polycrystalline semiconductor layer, the diffusion coefficient to the thin film being smaller than that to the polycrystalline semiconductor layer. The process effects a first heat treatment at a temperature of 800.degree. C. or less to diffuse the impurity injected into the polycrystalline semiconductor layer in the polycrystalline semiconductor layer, thereby forming a uniform or substantially uniform impurity containing region at least at the thin film side of the polycrystalline semiconductor layer, and, effects a second heat treatment the temperature of which is 950.degree. C.
    Type: Grant
    Filed: May 27, 1993
    Date of Patent: December 19, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masaru Sakamoto, Masakazu Morishita, Shigeru Nishimura
  • Patent number: 5462888
    Abstract: A process for fabricating transistors on a substrate is disclosed. In accordance with the process, stacks of material are formed on the surface of the substrate. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. A first layer of polycrystalline material is deposited over the substrate and selectively removed such that only those portions of the polycrystalline layer that surround the stacks of material remain. A layer of silicon nitride or silicon dioxide is then formed over the substrate surface. A first resist is then spun on the substrate surface. This resist aggregates near the stacks of material. An isolation mask is generated that leaves exposed only those areas of the substrate that correspond to the area of overlap between the first polycrystalline area and the stacks of material, which also contain a layer of polycrystalline material.
    Type: Grant
    Filed: June 6, 1994
    Date of Patent: October 31, 1995
    Assignee: AT&T IPM Corp.
    Inventors: Tzu-Yin Chiu, Frank M. Erceg, Francis A. Krafty, Te-Yin M. Liu, William A. Possanza, Janmye Sung
  • Patent number: 5453389
    Abstract: A method for manufacturing bipolar semiconductor devices wherein damage to the active regions of the devices due to the direct implantation of impurities is suppressed. A material is selectively deposited on a semiconductor substrate, the material having a characteristic such that formation of the material occurs on some substances such as silicon and polysilicon, and formation of the material is suppressed on other substances such as silicon dioxide and silicon nitride. Impurities are introduced into the material rather than into the substrate. The impurities are then diffused into the active regions by standard processes such as rapid thermal anneal (RTA) or furnace anneal. The material generally contains germanium, and usually is a polycrystalline silicon-germanium alloy. The diffusion depth of the impurities may be controlled with great precision by manipulating several parameters.
    Type: Grant
    Filed: August 27, 1993
    Date of Patent: September 26, 1995
    Assignee: National Semiconductor, Inc.
    Inventors: Robert J. Strain, Sheldon Aronowitz
  • Patent number: 5270224
    Abstract: A bipolar transistor includes a base region made of silicon crystal doped with a first impurity to a first level so as to establish a first carrier concentration in the base region and an emitter region made of silicon crystal doped with a second impurity to a second level substantially larger than the first level by a predetermined factor so as to establish a second carrier concentration in the emitter region, in which the second impurity exceeds the solubility limit of the second impurity in silicon crystal. The first and second levels are chosen in such a range that a difference in the carrier concentrations between the emitter region and the base region decreases substantially with increasing impurity level in the base region.
    Type: Grant
    Filed: January 17, 1992
    Date of Patent: December 14, 1993
    Assignee: Fujitsu Limited
    Inventors: Yuji Furumura, Fumitake Mieno, Tsutomu Nakazawa, Takashi Eshita, Mamoru Maeda, Tsunenori Yamauchi
  • Patent number: 5244831
    Abstract: The present invention concerns a method for doping a polysilicon layer with phosphorous in which phosphorous oxychloride is supplied to the silicon wafer near the beginning of the oven temperature ramping of the silicon wafer. By introducing the phosphorous oxychloride earlier than in prior art methods, the present invention can reduce the poly rho and poly rho sigma of the doped polysilicon layer. Alternatively, the root DT of the diffusion of the doped material in the doped silicon region on the silicon wafer can be reduced, which helps to maintain the junction depth of the doped silicon region.
    Type: Grant
    Filed: May 4, 1992
    Date of Patent: September 14, 1993
    Assignee: Zilog, Inc.
    Inventors: Gregory Hindman, John Rule, Jack Berg
  • Patent number: 5242858
    Abstract: A process for preparing a semiconductor device comprises exposing at least a part of the main surface of a semiconductor substrate, forming a layer comprising the same main component as the above substrate, forming a flattening agent layer on the surface of said layer, removing the above layer and the flattening agent layer at the same time and injecting an impurity after said removing step.
    Type: Grant
    Filed: September 5, 1991
    Date of Patent: September 7, 1993
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masaru Sakamoto, Masakazu Morishita, Shigeru Nishimura
  • Patent number: 5204275
    Abstract: A process for fabricating a compact bipolar transistor structure is disclosed which eliminates the need for a field oxide isolation region between the collector contact region and emitter of the transistor. An island of non-monocrystalline silicon is formed on top of the transistor structure partially covering the base and collector contact regions. Ribbons of non-insulating material are formed along the sidewalls of the island. The ribbon over the base region is employed to form a narrow emitter region with an annealing step that drives dopant from the ribbon or island into the portion of the base region below the ribbon. An insulating layer is disposed between the transistor structure and the island and ribbon over the collector contact region to insulate the emitter from the collector. Insulating sidewall spacers are formed next to the sidewall ribbons to insulate silicide regions grown over the base region, island and collector contact region for the three transistor contacts.
    Type: Grant
    Filed: December 26, 1990
    Date of Patent: April 20, 1993
    Assignee: North American Philips Corp.
    Inventor: Richard H. Lane
  • Patent number: 5098638
    Abstract: A method of manufacturing a semiconductor device forms an intrinsic base layer by doping an impurity in the emitter polysilicon electrode into the intrinsic base region of the surface of a semiconductor substrate by heat treatment through the emitter lead-out part hole self-aligned to the base lead-out electrode. Thus, beneath the insulation film of the substrate surface between the base lead-out part hole and emitter lead-out part hole, the outer marginal part of the intrinsic base layer and the inner marginal part of the extrinsic base layer overlap uniformly. Still more, since the diffusion of the impurity by heat treatment is very fast in the polysilicon emitter electrode as compared with that in the silicon substrate, an extremely shallow intrinsic base layer may be formed.
    Type: Grant
    Filed: April 25, 1990
    Date of Patent: March 24, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Shigeki Sawada
  • Patent number: 5071780
    Abstract: A method of forming self-aligned transistors which may be either bipolar or field effect is described. A heavily doped conductive layer of one conductivity type is formed upon a monocrystalline semiconductor substrate of the opposite conductivity type to that of the one type. The conductive layer may be polycrystalline silicon, tungsten silicide, titanium nitride or the like. An insulator layer is formed upon the surface of the conductive layer. Openings with substantially vertical sidewalls are formed through the conductive layer to the semiconductor substrate in at least the locations of the first element of the transistors to be formed. The structure is heated to form the heavily doped portions of the second element of said transistors of the one conductivity type by outdiffusing from the conductive layer.
    Type: Grant
    Filed: August 27, 1990
    Date of Patent: December 10, 1991
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Nun-Sian Tsai
  • Patent number: 5064776
    Abstract: A buried contact between the gate of a transistor device formed at the surface of a semiconductor substrate and a diffusion region formed in the surface of the substrate remote from the transistor device. The buried contact includes a polysilicon interconnect structure formed after shaping of the gate layer and the gate insulator. The polysilicon interconnect structure engages a side edge and an adjoining lower surface of the gate layer at a location where the gate insulator has been removed by isotropic etching from between the gate layer and the surface of the substrate. The polysilicon interconnect layer also contacts the surface of the substrate beneath an overhanging edge of the gate layer so as to form a surface current pathway interface. Below the surface current pathway interface a migration region is formed by heat-induced movement of ions from the gate layer through the polysilicon interconnect structure.
    Type: Grant
    Filed: October 3, 1990
    Date of Patent: November 12, 1991
    Assignee: Micron Technology, Inc.
    Inventor: Martin C. Roberts
  • Patent number: 5047357
    Abstract: A bipolar transistor and method of making the same is disclosed. The transistor has an emitter region which is diffused from polysilicon into the intrinsic base region, where the polysilicon is doped with two dopant species of different diffusivity. The impurity concentration of the higher diffusivity species, for example phosphorous, can be selected to define the emitter junction depth, which is preferably shallow, while the impurity concentration of the lower diffusivity species, for example arsenic, can be selected to provide a high conductivity emitter electrode, as well as reduce the sensitivity of the emitter electrode to counterdoping from the implantation of the extrinsic base region. The structure is compatible with BiCMOS processing, as the same anneal can be used to diffuse the emitter and the source/drains of the MOS transistors, with the emitter junction depth optimized via the implant conditions of the higher diffusivity species.
    Type: Grant
    Filed: February 3, 1989
    Date of Patent: September 10, 1991
    Assignee: Texas Instruments Incorporated
    Inventor: Robert H. Eklund
  • Patent number: 5045483
    Abstract: A bipolar transistor and resistor are provided. Fabrication includes using a high temperature oxide to form sidewall spacers for the transistor contacts and/or to overlay the resistor portion of the device. Deposition of the HTO is combined with dopant drive-in so that fewer total steps are required. The process is compatible with MOS technology so that the bipolar transistor and resistor can be formed on a substrate along with MOS devices.
    Type: Grant
    Filed: April 2, 1990
    Date of Patent: September 3, 1991
    Assignee: National Semiconductor Corporation
    Inventors: Bancherd DeLong, Christopher S. Blair, George E. Ganschow, Thomas S. Crabb
  • Patent number: 4988632
    Abstract: A process is disclosed for fabricating bipolar transistors having self aligned and closely spaced polycrystalline silicon base and emitter electrodes. The process is especially amenable to integration with the fabrication of MOS transistors to form BiMOS integrated circuits. In accordance with one embodiment of the invention, a P type polycrystalline silicon layer is deposited overlying an N type silicon substrate. The polycrystalline silicon layer is patterned to form base contact electrodes and to leave exposed a portion of the surface of the N-type substrate. An electrically insulating layer is formed overlying the polycrystalline silicon base contacts and the exposed silicon substrate. Sidewall spacers are formed on the electrically insulating layer at the sidewalls of the base contact electrode.
    Type: Grant
    Filed: January 2, 1990
    Date of Patent: January 29, 1991
    Assignee: Motorola, Inc.
    Inventor: James R. Pfiester
  • Patent number: 4983531
    Abstract: An improved bipolar transistor of a BiCMOS integrated circuit is fabricated by utilizing a nitride layer over a thin silicon dioxide layer combined with a polysilicon layer. This bipolar structure has a self-aligned, P-type extrinsic base which results in lower base resistance and improved performance.
    Type: Grant
    Filed: February 12, 1990
    Date of Patent: January 8, 1991
    Assignee: Motorola, Inc.
    Inventor: Stephen J. Cosentino
  • Patent number: 4965216
    Abstract: A process for fabricating a CMOS compatible bipolar transistor is described. The transistor, which is of the polysilicon emitter type, is fabricated by forming a p-type layer in a well, providing a polysilicon emitter in contact with the layer, using the emitter as a mask to implant p.sup.+ -type base contact regions, and applying contacts to the device.
    Type: Grant
    Filed: January 26, 1990
    Date of Patent: October 23, 1990
    Assignee: STC PLC
    Inventors: Peter D. Scovell, Peter F. Blomley, Roger L. Baker
  • Patent number: 4965220
    Abstract: A semiconductor integrated circuit device is disclosed which comprises a bipolar transistor and a field effect transistor, in which a gate electrode of the field effect transistor and a collector electrode of the bipolar transistor are formed from a common electrode layer of a high impurity concentration, and in which the collector region of the bipolar transistor comprises a region of a high impurity concentration having a conductivity type the same as that of the collector region of the bipolar transistor.
    Type: Grant
    Filed: February 6, 1989
    Date of Patent: October 23, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Iwasaki
  • Patent number: 4945070
    Abstract: A CMOS device having shallow source and drain regions is formed in a body of single crystalline silicon having a major surface by forming in the body adjacent well regions of opposite conductivity type having an isolation region of an insulating material extending into the body from the major surface along the junction of the well regions. Thin layers of silicon oxide are formed on the major surface over each of the well regions, and a gate line of conductive polycrystalline silicon is formed over each of the silicon oxide layers. The side walls of the gate lines are covered with a layer of silicon oxide. A layer of polycrystalline silicon is selectively deposited on the surface of the body at each side of each gate line and on the gate lines. A layer of a refractory metal is deposited on the polycrystalline silicon layer. The polycrystalline silicon layer is heated to cause the metal to react with the silicon and form a metal silicide region at least partially through the polycrystalline silicon layer.
    Type: Grant
    Filed: January 24, 1989
    Date of Patent: July 31, 1990
    Assignee: Harris Corporation
    Inventor: Sheng T. Hsu
  • Patent number: 4882290
    Abstract: In an NPN transistor, a contact base region, an active base region, and a further base region are formed in the silicon substrate. The further base region is between the contact base region and the active base region, and is adjacent to the contact base region and the active base region. The further base region has a depth shallower than that of the contact base region and deeper than that of the active base region. In the method of forming the bipolar transistor, a polysilicon semiconductor layer is formed on a semiconductor substrate. The polysilicon semiconductor layer is partially etched to form a base leading electrode and an emitter leading electrode. A semiconductor impurity is implanted into a base forming region of the silicon substrate via that portion where the polysilicon semiconductor layer is removed.
    Type: Grant
    Filed: January 25, 1988
    Date of Patent: November 21, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shigeru Komatsu
  • Patent number: 4882297
    Abstract: In fabricating the contact, the electrode layer of polycrystalline silicon whose rim portion is bonded via a layer portion of insulating material to the substrate, is used at least throughout the length of a part of its rim portion for the lateral delimitation of a etching process, as an etch mask, in the course of which a frame-shaped layer portion is formed underneath the rim portion of the electrode layer, and the contact area of the substrate as bordering on the layer portion is exposed. Following the deposition of a metal layer of a metal forming a silicide in a thickness smaller than the thickness of the layer portion, and the heating for forming the silicide, the metal which has so far not reacted with the silicon, is removed by using an etching agent selectively dissolving the metal.
    Type: Grant
    Filed: June 13, 1988
    Date of Patent: November 21, 1989
    Assignee: Deutsche ITT Industries GmbH
    Inventor: Lothar Blossfeld
  • Patent number: 4879252
    Abstract: The method of manufacturing a semiconductor device according to the present invention comprises the step of forming an opening in use for forming an emitter region. This step uses the independent etching characteristics of N and P type polysilicons to simplify the opening forming process, which is very complicated in the conventional method. To be more specific, the impurity doped in the first polysilicon layer at a high concentration is diffused into the second polysilicon layer adjacent to the first polysilicon layer. When the impurity doped in the first polysilicon layer is diffused into the second polysilicon layer, the diffused impurity dominantly determines the conductivity type of that portion of the second polysilicon layer, into which the impurity is diffused. Therefore, one of the first polysilicon layer and the second polysilicon layer portion is etched by a solution, independently of the other.
    Type: Grant
    Filed: January 25, 1988
    Date of Patent: November 7, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shigeru Komatsu
  • Patent number: 4843033
    Abstract: A method of diffusion of dopants (e.g. zinc) into III-V substrates (e.g. GaAs) using metal silicide and dopants (e.g. W.sub.x Si.sub.y :Zn) is disclosed. A cap layer (e.g. SiO.sub.2 or Si.sub.3 N.sub.4) is also used. The zinc tungsten silicide is formed by cosputtering zinc and tungsten silicide (W.sub.5 Si.sub.3). Applications include adjustment of threshold voltages in JFETs by rapid thermal pulsing of zinc into device channel regions and use of the zinc tungsten silicide as a base contact plus extrinsic base dopant source together with a nitride sidewall self-alignment.
    Type: Grant
    Filed: April 20, 1987
    Date of Patent: June 27, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Donald L. Plumton, Shiban K. Tiku
  • Patent number: 4839309
    Abstract: A method of fabricating a dielectrically-isolated structure is disclosed rein the structure includes a layer of silicide which is selectively doped, preferably using an ion implantation process. The doped silicide is then used as the diffusion source for the subsequent formation (through a heat treatment) of various active portions (collector, emitter, drain, source, for example) of a variety of high-voltage, high-speed active devices. The non-doped silicide is advantageously utilized as a low-resistance contact between the buried diffusion region and the surface electrode. In an alternative embodiment, bottom portions of the silicide contiguous to the tub are removed, leaving only vertical silicide portions adjacent to the sidewalls of the dielectrically isolated tub.
    Type: Grant
    Filed: March 30, 1988
    Date of Patent: June 13, 1989
    Assignees: American Telephone and Telegraph Company, AT&T Technologies, Inc., AT&T Bell Laboratories
    Inventors: William G. Easter, Anatoly Feygenson
  • Patent number: 4586240
    Abstract: A vertical IGFET comprising a substantially planar silicon wafer with a source electrode on one major surface and a drain electrode on the opposite major surface is disclosed. An insulated gate electrode, which includes a conductive finger portion surrounded by an insulating layer, is internally disposed in the silicon wafer such that a predetermined voltage applied to the gate electrode will regulate a current flow between the source and drain electrodes. The device is fabricated utilizing an epitaxial lateral overgrowth technique for depositing monocrystalline silicon over the insulated gate which is disposed on a silicon substrate.
    Type: Grant
    Filed: June 26, 1985
    Date of Patent: May 6, 1986
    Assignee: RCA Corporation
    Inventors: Scott C. Blackstone, Lubomir L. Jastrzebski, John F. Corboy, Jr.
  • Patent number: 4581814
    Abstract: The efficacy of dielectrically isolated device formation on a substrate is substantially enhanced through a specific set of processing steps. In particular, before silicon oxide regions, e.g., gate oxide regions, are produced, bulk polycrystalline areas are heat treated to substantially increase their polycrystalline silicon grain size.
    Type: Grant
    Filed: December 13, 1984
    Date of Patent: April 15, 1986
    Assignee: AT&T Bell Laboratories
    Inventors: George K. Celler, Pradip K. Roy, Donald G. Schimmel, Lee E. Trimble
  • Patent number: 4569123
    Abstract: A method for manufacturing semiconductor devices is presented. The method comprises the steps of opening two windows on an insulating layer covering a semiconductor substrate, and forming a polysilicon layer over the entire surface of the insulating layer and the windows. Donor and acceptor impurities are respectively implanted into the portions of the polysilicon layer corresponding to the two opening windows through the appropriate photoresists. The doped impurities are thereafter subjected to annealing to form two different conduction type regions under the two opening windows. Thereafter, a metal layer and a photoresist are deposited in order to make the metal electrodes for each conduction region. Thus, the patterning of the polysilicon can be made in self-alignment with the etching mask, and the formation of two different conduction type semiconductor regions are simultaneously attained.
    Type: Grant
    Filed: September 7, 1984
    Date of Patent: February 11, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Ishii, Tatsuro Mitani
  • Patent number: 4565584
    Abstract: An amorphous or polycrystalline film which continuously covers the exposed surface of a single crystal substrate and an insulating film, is deposited in ultra-high vacuum and then heat-treated. The film is subjected to solid phase epitaxial growth at a temperature far lower than in prior-art methods, whereby a single crystal film is formed.
    Type: Grant
    Filed: January 25, 1983
    Date of Patent: January 21, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Masao Tamura, Makoto Ohkura, Masanobu Miyao, Nobuyoshi Natsuaki, Naotsugu Yoshihiro, Takashi Tokuyama, Hiroshi Ishihara
  • Patent number: 4563807
    Abstract: Semiconductor device, such as bipolar transistor, is made by molecular beam epitaxy, wherein a emitter layer (27) and overriding contact regions (28) of polycrystalline silicon are grown continuously on a silicon substrate (23+26) without breaking high vacuum, thus eliminating the adverse interface of natural oxide film under the polycrystalline silicon layer (28) and the adverse donor-acceptor compensation while attaining a well controlled h.sub.FE and enabling a shallow emitter junction.
    Type: Grant
    Filed: April 4, 1984
    Date of Patent: January 14, 1986
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Sakai, Toyoki Takemoto, Kenji Kawakita, Tsutomu Fujita, Atsuko Akiyama
  • Patent number: 4554030
    Abstract: A monocrystalline layer of one semiconductor material is grown onto a surface of a monocrystalline semiconductor body by means of molecular beam epitaxy. During such growth, the semiconductor body is kept at such a low temperature that a non-monocrystalline layer is obtained. The non-monocrystalline layer is then converted by a heat treatment into a monocrystalline form. Accordingly, an abrupt junction between the two semiconductor materials is obtained.
    Type: Grant
    Filed: March 2, 1984
    Date of Patent: November 19, 1985
    Inventors: Jan Haisma, Poul K. Larsen, Tim De Jong, Johannes F. Van der Veen, Willem A. S. Douma, Frans W. Saris