Abstract: A method of producing a semiconductor-on-insulator structure generates a first fixed charge in an insulator layer of a base substrate. An active substrate which is made of a semiconductor is bonded on the insulator layer of the base substrate to thereby generate a second fixed charge at an interface of the insulator layer and the active substrate. The first and second fixed charges have mutually opposite polarities. A portion of the active substrate is removed to form the active substrate to an arbitrary thickness.

Abstract: A method is provided for making a plurality of intrinsic gettering sites in a bonded silicon substrate (21). A first silicon substrate (10) with a first and second surface (12, 13) is provided. The first surface (12) of the first silicon substrate (10) is implanted with a plurality of nucleation ions (14). The first silicon substrate (10) is then heated in such a manner that a plurality of nucleation sites form from the plurality of nucleation ions. A second substrate (20) with a first surface (22) is then bonded to the first surface(12) of the first silicon substrate (10). A predetermined portion (24) of the first silicon substrate (10) is removed from the second surface (13) of the first silicon substrate (10), thereby providing a thin substrate having a plurality of intrinsic gettering sites near its active area, wherein the thin substrate is bonded to a handle semiconductor substrate (21).

Abstract: A process for making a backside illuminated image sensor fabricated upon a thinned silicon layer bonded to a quartz wafer is described. A borosilicate glass (BSG) layer interposed between the thinned silicon device layer and quartz support serves as a doping source for the back-surface accumulating electrostatic potential and serves to minimize stress associated with the thermal expansion differences associated with quartz and silicon.

Abstract: A manufacturing method of this invention improves nonuniformity in film thickness of a circuit element formation region produced due to a poor flatness of a semiconductor substrate in the manufacture of a semiconductor substrate having a dielectric isolating structure. Mirror-polished surfaces of first and second semiconductor substrates are opposed and bonded to each other so as to sandwich a dielectric having a predetermined thickness, and the first semiconductor substrate is ground from the surface opposite to the adhesion surface to have a predetermined thickness with reference to the dielectric. An impurity is doped in the first semiconductor substrate to form a high-concentration impurity layer having an impurity concentration corresponding to a predetermined low-concentration impurity layer having a predetermined thickness thereon, thereby constituting a circuit element region.

Abstract: A very thin silicon film SOI device can be made utilizing a bond and etch-back process. In the presently claimed invention, boron dopant is introduced into a surface of a silicon device wafer and the doped surface is bonded onto another silicon wafer at an oxide surface. The device wafer is thinned by etching down to the doped region and, by subsequent annealing in hydrogen, boron is diffused out of the silicon surface layer to produce very thin SOI films.

Abstract: A semiconductor circuit structure including a semiconductor substrate portion and at least one region provided on one main surface thereof insulatedly isolated from other regions provided on the same surface, by an burying means made of an oxide film, the burying means including a bottom flat portion and at least one side wall portion provided at least in the vicinity of an edge portion of and integrally formed with the bottom flat portion, thereby a semiconductor circuit structure provided with a plurality of insulatedly isolated regions on a main surface thereof and having a high withstand voltage can be obtained in a short production process.

Abstract: A method for manufacturing a bonded semiconductor body including contacting the flat mirror surfaces of semiconductor substrate wafers used as semiconductor element substrates, and subjecting the adhered semiconductor substrate wafers to a heat treatment at a temperature higher than 200.degree. C. and lower than the melting point of the semiconductor substrate wafers to bond the mirror surfaces. The surface roughness of each of the mirror surfaces of the semiconductor substrate wafers is set not more than 130 .ANG. at its maximum value when measured in a range of 1 mm on a reference plane provided in a predetermined area of the mirror surface.

Abstract: An intermediate contact layer (16) is created within a vertical current flow semiconductor device such as an enhanced insulated gate bipolar transistor (EIGBT) (17). An active wafer (11) that is used for forming active elements of the device is wafer bonded to a conductor (16) that is on a surface of a substrate wafer (12). The wafer bonding not only forms the intermediate contact layer (16) but also diffuses a series of P (18) and N (19) regions into the active wafer (11) thereby forming ohmic contacts between the P (18) and N (19) regions and the intermediate contact layer (16). The substrate wafer (12) provides support for the active wafer (11) during subsequent wafer processing operations.

Abstract: Multi-layer silicon structures particularly micromechanical sensors, can be made by cleaning and polishing respective surfaces of two silicon wafers, assembling the wafers together under clean room conditions and adhering them together by temperature treatment. This method is improved by the pretreatment of the wafer surfaces using fuming nitric acid (e.g., 100% HNO.sub.3), rinsing with de-ionized water, drying, and temperature treatment at a lower temperature than was previously thought necessary, namely between 100.degree. and 400.degree. C. This has the advantage that such gentler treatment preserves previously-applied integrated circuit structures, which can therefore be applied before the wafer assembly steps. The method is particularly suitable for producing pressure sensors having a pressure-responsive silicon membrane, and an evaluation circuit integrated on the silicon wafer.

Abstract: A method of forming a high density semiconductor structure including one or more buried metal layers. One or more metal layers may be formed on a first semiconductor substrate, with the metal layer or layers being insulated from one another and from the substrate. One or more metal layers may be formed on the surface of a second substrate which may or may not be a semiconductor substrate. The topmost metal layers, either or both of which may have an insulating layer thereon, are placed in contact and heated in an oxidizing ambient atmosphere to form a bond therebetween. One or more vias connect the buried metal layers to the active devices in the substrates. The buried metal layers may form buried power and ground planes and buried metallization patterns for device interconnection.

Abstract: A semiconductor device of vertical arrangement includes an anode region formed of a first semiconductor substrate and a second semiconductor substrate joined with the first semiconductor substrate. The first semiconductor substrate forms a high-resistance layer with a predetermined impurity density, and the second semiconductor substrate forms a low-resistance layer whose impurity density is higher than that of the high-resistance layer. A PN junction is formed inside the first semiconductor substrate. The periphery of the first semiconductor substrate including the PN junction is configured in an inverted mesa structure and coated with an insulation material. With this arrangement, the semiconductor device has a high withstand voltage and enables an employment of a large diameter wafer.

Abstract: A standard thick silicon charge-coupled device (FIG. 1A) has its pixel face mounted to a transparent, optically flat glass substrate using a thin layer of thermoset epoxy. The backside silicon of the charge-coupled device is thinned to 10 .+-.0.5 um using a two-step chemi-mechanical process. The bulk silicon is thinned to 75 um with a 700 micro-grit aluminium oxide abrasive and is then thinned and polished to 10 um using 80 nm grit colloidal silica. Access from the backside to the aluminum bonding pads (36 of FIG. 5) of the device is achieved by photolithographic patterning and reactive ion etching of the silicon above the bonding pads. The charge-coupled device is then packaged and wire-bonded in a structure which offers support for the silicon membrane and allows for unobstructed backside illumination.

Abstract: A method for producing optically flat thin semiconductor wafers (12) bonded to a substrate (16). The wafer (12) is bonded without touching the top surface of the wafer (12). Also, the bond is created without the use of pressure. Electrostatic bonding, or contact bonding or both may be employed. After the wafer (12) is bonded, it is then polished to a desired thickness and flatness. After contact bonding and polishing the wafer (12) may then be removed for further processing. The wafer may then be contact bonded to a final substrate (b 34) or electrostatically bonded to a final substrate (42). The contact bonding technique may also be employed as a means for holding the wafer (12) during precise photolithography. The optical flatness achieved permits improved yields over conventional means for securing wafers during photolithography. The electrostatic bonding technique permits extremely thin optically flat silicon wafers to be produced.

Abstract: A method for fabricating an all silicon absolute pressure sensor employing silicon-on-insulator structures. More particularly, a method for fabricating an all silicon absolute pressure sensor based upon an ungated metal-oxide semiconductor field-effect transistor which offers a high degree of immunity to temperature effects, increased reliability, minimal substrate parasitics, reduced manufacturing variations from device to device, as well as inexpensive and simple fabrication.

Abstract: In a method for preparing a substrate for semiconductor device, the substrate is prepared either by directly bonding a bonding wafer to a base wafer or by bonding the bonding wafer to the base wafer with an oxide film formed on at least the bonding surface of the bonding wafer or the bonding surface of the base wafer to make finished semiconductor devices with an SOI structure. Prior to the bonding operation, the bonding wafer and the base wafer are subjected to the steps of (1) making the diameter of the bonding wafer smaller than the diameter of the base wafer, (2) setting the beveling width of the back side (bonding side) of the bonding wafer at 50 microns or less, and (3) beveling the front side of said base wafer so that the bonding surface of the base wafer is equal in size to the bonding surface of the bonding wafer.

Abstract: A method of fabricating a low voltage, deep junction semiconductor device includes providing first and second wafers of opposite conductivity types, each having a dopant concentration of at least 4.0.times.10.sup.16 atoms/cc. After cleaning the wafers and removing heavy metal impurities therefrom by gettering, the wafers are bonded together. This method results in the successful fabrication of semiconductor devices having a junction depth in the range of 20 to 500 microns and a breakdown voltage of less than 20 volts.

Abstract: There is provided a method for bonding at least two semiconductor wafers to each other which comprises the steps of warping one of the semiconductor wafers, bringing the warped semiconductor wafer into contact with the other semiconductor wafer at one contact point, and reducing pressure in an atmosphere surrounding the semiconductor wafers to flatten the warped semiconductor wafer. An apparatus for bonding wafers using the above bonding method comprises a first wafer holder for warping and holding one of two wafers and a second wafer holder for holding the other wafer. First and second covers are attached so as to surround the first and second wafer holders. The apparatus further comprises a shaft for rotating the first and second wafer holders so that one of the wafers contact the other wafer at one contact point and the first and second covers are connected to each other to form a chamber.

Abstract: A conductivity modulation type semiconductor device comprises a semiconductor anode substrate of a P type having two surfaces, a semiconductor substrate of an N type having two surfaces, the semiconductor substrate having a high impurity layer-like region on one surface thereof and a low concentration drain region on the other surface thereof, a body region of P type formed in the drain region and exposed at one surface of the semiconductor substrate, source regions of an N type formed in the body region and exposed at the other surface of the semiconductor substrate, and a gate layer formed within the isulating layer, which extends between the source and drain regions, on the body region. The other surface of the anode substrate is polished and is intimately joined to the polished surface of the semiconductor substrate to form a junction layer therebetween.

Abstract: High mobility thin film transistors for fabricating integrated drivers for active matrix displays and a special method of fabrication for obtaining the thin film transistors having mobility sufficiently high enough as drivers operable in the several megahertz frequency range needed for driving high resolution active matrix displays.

Abstract: This is a method of forming a semiconductor-on-insulator wafer from two individual wafers. The method comprises: forming a layer of metal (e.g. titanium 24) on a first wafer; forming an insulator (e.g. oxide 32) on a second wafer; forming a bonding layer (e.g. poly 38) over the insulator; anisotropically etching the bonding layer forming chambers in the bonding layer; stacking the first and second wafers with the metal against the second wafer's bonding layer; forming a chemical bond between the metal layer and the bonding layer (e.g. between the titanium 20 and the poly 38) in a vacuum chamber, thereby creating micro-vacuum chambers (42) between the wafers; selectively etching the second wafer to form a thin semiconductor layer (e.g. epi layer 30). This is also a semiconductor-on-insulator wafer. The wafer comprises: a substrate (e.g. semiconductor substrate 20); a layer of metal (e.g. titanium 24) and semiconductor (e.g. silicide 40) over the substrate; a bonding layer (e.g.

Abstract: A rod base material for forming wafers for electronic devices is formed from a plurality of rod members made of selected materials. The rods are assembled in parallel and are bonded with each other into an integrated body. In one aspect of this invention, a mirror-finished bonding face is formed at the outer surface of each of the rod members, and is cleaned by a surface treatment using chemicals. Subsequently, respective rod members are assembled in parallel and brought into contact with each other at their respective bonding faces. The thus prepared and assembled rod members are maintained in a heated atmosphere until they combine into an integrated body to provide the base material. The rod base material is thereafter subjected to slicing to provide wafers used for forming electronic devices.

Abstract: A dielectric isolated area is formed by bonding a first and a second wafer. A first wafer having a first and a second major surface is provided. A second wafer having a first and a second major surface is then provided. Trenches are formed in the first surface of the second wafer. Subsequently, a dielectric layer which can be planarized is formed on the surface of the second wafer having trenches formed therein. The first and second wafers are then bonded so that the dielectric layer and the first surface of the first wafer are bonded to each other. A portion of the second surface of the second wafer is then removed down to at least the bottom of each trench.

Abstract: A semiconductor device (10) is formed by providing first and second semiconductor bodies (1 and 11) each having first and second major surfaces (2 and 3) and (12 and 13), respectively, defining a rectifying junction pattern (21) adjacent to at least one (12) of the first major surfaces, and bonding the first major surfaces (2 and 12) together to join the two semiconductor bodies (1 and 11) to form the semiconductor device (10) in which the rectifying junction pattern 21 defines a path for the flow of charge carriers between the second major surfaces. The rectifying junction pattern (21) is defined at the one first major surface (12) by an electrically conductive pattern (20) forming a Schottky junction (21) with at least one of the first and second semiconductor bodies (1 and 11).

Abstract: A semiconductor fabrication process uses an epitaxial layer as an etch stop in a plasma etch process. In one embodiment, mechanical stops and an epitaxial layer are used in combination for stopping precisely at a desired end point.

Abstract: A semiconductor device includes a semiconductor substrate, a pair of low breakdown voltage elements formed in the substrate so as to be adjacent to each other, and a high breakdown voltage element formed to be adjacent to one of the low breakdown voltage elements. The pair of low breakdown voltage elements are isolated from each other by a pn junction and the low breakdown voltage elements and the high breakdown voltage element are isolated from each other by a dielectric material. The semiconductor substrate is a composite substrate formed by directly bonding a first substrate serving as an element region to a second substrate serving as a supporting member through an insulating film.

Abstract: A new method of preparing an exceedingly flat substrate for forming semiconductor devices having an SOI structure is disclosed.In this process at least a first wafer made of silicon single crystal is concavely warped beforehand. A second silicon single crystal wafer is bonded to the concavely warped side of the first wafer with an oxide film interposed between the first and the second wafers. Subsequently the wafers are subjected to polishing and/or etching so that the second wafer bonded is thinned into a thin film to prepare a substrate for forming semiconductor devices having a SOI structure.At this time the polishing and/or etching cause the bonded wafers to be warped convexly to offset the concavity of the first wafer, resulting in realization of a precisely flat substrate for forming semiconductor devices having an SOI structure.

Abstract: First and second single crystal silicon substrates are integrated, by means of a thermal treatment, with first and second silicon oxide films formed on surfaces of said respective first and second single crystal silicon substrates in contact with each other. More specifically, an insulating region is formed by integrating first and second silicon oxide films formed on the first and second single crystal silicon substrates. First and second semiconductor regions constituted by the first and second single crystal silicon substrates are electrically isolated by the insulating region. As a result, it is possible to reduce the width of the depletion layer generated in the second semiconductor region by the influence of the first semiconductor region in which an element is formed. A back gate region formed in the second semiconductor region and the first semiconductor region, in which an element is not formed, are held substantially at an equal potential.

Abstract: A method for manufacture of a semiconductor wafer in a manner to attain a high uniformity in the thickness of a semiconductor layer, by first forming hardly polishable stoppers of mutually different thicknesses in the semiconductor, then polishing the semiconductor until the thicker stopper is exposed on one main surface of the semiconductor, subsequently removing the thicker stopper to attain a thickness less than that of the thinner stopper, and thereafter polishing the aforesaid one main surface of the semiconductor until the thinner stopper is exposed. There is also disclosed a semiconductor device of a quantum well wire structure comprising a semiconductor layer formed on an insulator substrate, a thermally oxidized film of the semiconductor layer formed on such layer, and a gate electrode fromed on one side of the semiconductor layer, wherein the channel width is determined by the thickness of the semiconductor layer.

Abstract: An improved method for eutectically bonding a silicon wafer into a cavity of a packaging body. A gold/silicon eutectic alloy cladding is formed on a ribbon made of gold. A strip is cut from the ribbon and placed into the package cavity with the cladding side up. Then a die is placed onto the strip on top of the gold/silicon cladding. The die is then scrubbed at a temperature of approximately 400.degree. C. and the gold/silicon cladding acts as a catalyst to form a gold/silicon eutectic bond between the die and the packaging body.

Abstract: A process for producing an SOI-structured semiconductor device substrate has the steps of: reducing the diameter of the one Si-monocrystal wafer of two bonded polished Si-monocrystal wafers to be slightly smaller than that of the other Si-monocrystal wafer so that the width of the annular margin defined between the bonded surfaces of the Si-monocrystal wafers is uniform; then forming an annular polishing guard on the cylindrical surface of the one wafer and the margin of the other wafer, the polishing guard having a predetermined thickness and being made of a material providing a polishing speed lower under the same condition than the one wafer; and then polishing the one wafer so as to make it in thin film. The polishing guard provides an accurate thickness control of the resulting Si-monocrystal thin film, in particular, even at a few micrometers level.

Abstract: A method of manufacturing a silicon-on-insulator semiconductor body is characterized by the steps consisting in that a carrier body is temporarily connected to a supporting body with accurately flat and parallel major surfaces and having a thickness of at least 1/8 of the largest dimension of the carrier body, in that the free major surface of the carrier body is mechanically polished to a precision of at least 1/2 .mu.m flatness, in that the carrier body is detached from the supporting body and the polished major surface is temporarily connected to the supporting body and the other major surface of the carrier body is mechanically polished to a precision of at least 1/2 .mu.m flatness and a parallelism between the major surfaces of at least 1/2 .mu.m whereupon a semiconductor body is connected through a major surface permanently to a major surface of the carrier body, in that then the semiconductor body is mechanically ground to a thickness of at least 50 .mu.

Abstract: A solid state accelerometer having an all silicon sensor for measuring accelerational and gravitational forces. The accelerometer measuring system also has associated electronics that include an analog rebalance loop and a digitizer loop.

Abstract: A process for fabricating a semiconductor device by forming a diffusion region in a first semiconductor wafer and bonding the surface of the first semiconductor wafer having the diffused region to a second semiconductor wafer to form a low resistance buried layer. The process includes further diffusion to provide an external electrical contact with the buried layer. Further enhancements are provided by selectively forming voids and/or selectively applying materials of greater and lesser conductivity on at least one of the semiconductor wafers before bonding, forming complex internal semiconductor structures in the bonded wafer structures.

Abstract: A semiconductor transducer structure is fabricated by utilizing varying height diffused layers in a sacrificial wafer. A carrier wafer has a dielectric layer on a top surface which includes a layer of glass. The sacrificial wafer, after being subject to diffusion of highly doped semiconductor material, exhibits a plurality of varying depth regions. These regions manifest the basic transducer structure. By utilizing selective etching, one can thus form a transducer structure on the sacrificial wafer which is bonded to the carrier wafer by mean of an electrostatic bond. The resultant method and structure enables one to provide transducers with improved operating characteristics which are adaptable for many different modes of operation.

Abstract: A method for manufacturing a semiconductor device comprising at least a support body and a monocrystalline semiconductor body, in which both bodies are provided with at least one flat optically smooth surface obtained by means of bulk-reducing polishing (mirror polishing), and at least the semiconductor body is then provided at the optically smooth surface with an electrically insulating layer with at least the electrically insulating layer on the semiconductor body being subjected to a bonding-activating operation, whereupon both bodies after their flat surfaces have been cleaned, are contacted with each other in a dust-free atmosphere in order to obtain a rigid mechanical connection, after which they are subjected to a heat treatment of at least 250.degree. C., whereupon the semiconductor body is etched to a thin layer having a thickness lying between 0.05 and 100 .mu.m.

Abstract: Herein disclosed is a semiconductor pressure sensor and a method of manufacture. The sensor includes a plate having a recess in its main surface. A diaphragm has a lower surface therof bonded to a first main surface of the plate and formed so as to have an upper surface having no holes therein. A piezoresistive layer is formed so as to be in contact with the diaphragm and is positioned so as to be at least partially over the recess. The resistance of the piezoresistive layer provides an indication of pressure applied to the diaphragm. The manufacturing method includes forming a piezoresistive layer of a single crystal substrate in a diaphragm without any recrystallization.

Abstract: A method including forming an alignment moat of a first depth on a first surface of a substrate and performing all backside processing, forming a first oxide layer on the first surface and oxide bonding it to a handling wafer by oxide bonding. The substrate is then thinned from a second surface opposite the first surface down to a thickness less than the depth of the alignment moat so the alignment moat is exposed at a third surface for front side processing.

Abstract: Disclosed is a semiconductor device which comprises a substrate, an insulating film formed at a predetermined region in the substrate or on the main surface of the substrate, a polycrystalline semiconductor layer formed on at least the insulating film, a single crystal semiconductor layer formed on at least the polycrystalline semiconductor layer, an isolation region formed to extend from the top main surface of the single crystal semiconductor layer to at least the surface of the insulating film, through the polycrystalline semiconductor layer, to electrically isolate a portion formed in the single crystal semiconductor layer surrounded by the isolation region from another portion formed in the single crystal semiconductor layer and not surrounded by the isolation region, at least a semiconductor device formed within the portion surrounded by the isolation region.

Abstract: According to the method of the present invention of manufacturing, from a semiconductor wafer, a dielectric substrate including insulated and separated island regions, a silicon oxide film is formed on a surface of a monocrystalline semiconductor wafer, and a mask consisting of a frame portion spreading on a peripheral region of the wafer and a grid-like portion arranged within the frame portion is formed. Then, in a patterning step, the surface of the wafer is exposed with the frame portion and the grid-like portion of the mask being left. Separation grooves arranged in a grid-like manner are formed in the exposed surface by etching. After a silicon oxide film is formed on the surfaces of the grooves, a polycrystalline semiconductor layer is made to grow on the silicon oxide film formed on the surfaces of the grooves and on the silicon oxide film formed on the surface of the wafer.

Abstract: Two semiconductor substrates, each having a polished surface and at least one groove is formed in the surface of at least one of the two substrates, are tightly and inseparably joined by the steps of wetting the polished surface of at least one of the two substrates with a liquid not containing any solute that causes precipitation of a solid substance upon evaporation of the liquid, e.g. methanol or water, placing one substrate on the other so as to bring the polished surfaces of the two substrates into contact with each other with intervention of a thin film of the liquid therebetween and, after a while, subjecting the provisionally joined substrates to a heat treatment and then forming a dielectric layer of organic polymer or silicon compound in at least one groove. This method is suitable for joining silicon substrates such as silicon wafers now on the market.

Abstract: A substrate structure for a composite semiconductor device comprises first and second semiconductor substrates whose major surfaces are bonded to each other with an insulating layer interposed therebetween. In this substrate structure, an epitaxial layer is grown from part of the second semiconductor substrate, forming one element area, and another element area is formed in the first semiconductor substrate area and isolated from the epitaxial layer.

Abstract: Wafers which are direct bonded to each other in accordance with prior art processes suffer from voids at their bonded interface. Annealing such composite structures at high temperature and high pressure (for silicon wafers preferably about 1,100.degree. C. and 15,000 psi) eliminates all voids which are not a result of the presence of a particle on one of the wafers at the time of mating.

Abstract: A method of manufacturing a semiconductor device comprising the steps of bringing a mirror-polished surface of a first semiconductor substrate of a first conductivity type into contact with a mirror-polished surface of a second semiconductor substrate of a second conductivity type having an impurity concentration which is lower than that of said first conductivity type, in a clean atmosphere, and thermally heating said first and second semiconductor substrates so that they unite. Impurity is diffused from said first semicondutor substrate into said second semiconductor substrate, thereby forming a diffusion layer of a first conductivity type in said second semiconductor substrate. A total amount of impurity of said diffusion layer is 1.times.10.sup.13 /cm.sup.2 to 2.times.10.sup.15 /cm.sup.2, to form a pn junction in said second semiconductor substrate.

Abstract: A process is disclosed for forming an oxide isolated semiconductor wafer which can include the formation of an associated high voltage transistor. The same wafer can include a plurality of low voltage transistors which can be connected in the form of circuitry that can control the high voltage transistor. Thus, a single IC chip can be fabricated for a power control function. The process includes bonding a first wafer to a second wafer using oxide (11/14), forming a groove (18) through the oxide (15), backfilling with epitaxially regrown semiconductor (19) to provide a high voltage section, and subsequently forming the high voltage transistor, e.g. NPN or DMOS devices, in said section.

Abstract: A method of forming a high-quality complementary transistor device using bonded wafer technology. The invention includes bonding a handle wafer to a first epitaxial layer and then providing dopants to form the respective N and P buried layers in said first epitaxial layer. A second epitaxial layer is then deposited over the buried layers to provide the device forming regions for the respective transistor devices.

Abstract: A method of forming a nonsilicon semiconductor layer on an insulating layer by forming a thin heteroepitaxial layer of nonsilicon semiconductor on a first substrate having a lattice structure which matches that of the heteroepitaxial layer. A first insulating layer is formed on the heteroepitaxial layer. A second insulating layer is formed on the surface of a second substrate. The first and second insulating layers are bonded together to form a unified structure, and the first substate is etched away. In a preferred embodiment the heteroepitaxial layer is germanium, gallium arsenide or silicon-germanium alloy while the first substrate is silicon, germanium, gallium arsenide or silicon-germanium alloy.

Abstract: The present semiconductor device comprises a first semiconductor substrate, an oxide film formed on the substrate and a second semiconductor substrate bonded to the oxide film. In particular, the semiconductor substrate further has a monocrystalline silicon layer which is formed by an epitaxial growth method on the second semiconductor substrate. Circuit elements are formed within the monocrystalline silicon layer.

Abstract: A method for bubble-free bonding of silicon wafers to silicon wafers or silicon wafers to quartz wafers either outside or inside a Clean Room. The method includes the steps of positioning wafers in closely spaced-apart and parallel relationship to each other in a rack or the like with mirror-polished surfaces of the wafers facing each other, cleansing the mirror-polished surfaces with a hydrophilization cleansing solution, flushing the cleansing solution from the mirror-polished surfaces of the wafers with deionized water, drying the wafers in a spin-dryer, and moving the wafers together so that contact occurs between opposing mirror-polished surfaces of the wafers and bonding occurs.

Abstract: A silicon semiconductor substrate includes an insulating layer embedded therein. The silicon semiconductor substrate comprises a first silicon plate, an insulating layer embedded in the first silicon plate so that the surfaces of the silicon plate and the insulating layer are in a mirror surface, and a second silicon plate united with the first silicon plate and the insulating layer at the mirror surface of the first silicon plate and the insulating layer. The insulating layer is used for forming an isolated region in the second silicon plate.

Abstract: During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In modular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substrate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating.