Thick-thin Oxides Patents (Class 148/DIG163)
  • Patent number: 6150220
    Abstract: A dual thickness gate insulation layer, for use with, e.g., a dual gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor), is formed using a more simplified method and improves the reliability. An impurity layer is formed in the semiconductor substrate, and the impurity layer includes a first portion and a second portion. An insulation layer is grown in the semiconductor substrate, and the insulation layer includes a first layer and a second layer which are different from each other in thickness. The present invention simplifies the insulation layer fabricating steps and improves product reliability.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: November 21, 2000
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Yun-Jun Huh, Nam-Hoon Cho
  • Patent number: 6124153
    Abstract: A method for manufacturing a polysilicon thin film transistor (TFT) according to the present invention reduces the electric field near the drain junction by varying partially the thickness of a gate insulating layer through a post oxide process. A polysilicon layer is patterned to become an active layer and a chemical vapor deposition oxide film deposited. By thermal oxidation a thermal oxide film is formed under the chemical vapor deposition oxide film. A gate electrode made of polysilicon is formed on the gate insulating layer. Thermal oxidation is performed to make the end portions of the thermal oxide film thicker than the portion under the gate electrode of the thermal oxide film. With this process, the electric field near the drain junction region is reduced and thus the leakage currents of the TFT decrease. In addition, the method in this invention is very simple compared with the conventional methods of obtaining a LDD structure and on-current is not reduced.
    Type: Grant
    Filed: July 15, 1996
    Date of Patent: September 26, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-hyung Lee, Yong-suk Jin
  • Patent number: 6037201
    Abstract: A method for manufacturing mixed-mode devices that can eliminate watermarks resulting from the formation of residues at the dead corner space of an inverted trapezium-shaped structure at the upper end of a shallow trench during dual gate-oxide processing operation. This method uses the same chemical processing conditions for etching the oxide layer and the removal of photoresist layer, so that no watermarks remain after the etching and cleaning processes. MOS transistors are formed over the thin gate oxide layer region and the thick gate oxide region are of, two types, each having a different gate oxide layer thickness so that each has a different operating voltage.
    Type: Grant
    Filed: March 17, 1998
    Date of Patent: March 14, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Meng-Jin Tsai, Cheng-Han Huang
  • Patent number: 5989946
    Abstract: A method of forming a pair of field effect transistors having different thickness gate dielectric layers includes, a) providing a first region on a substrate for formation of a first field effect transistor s having a first gate dielectric layer of a first thickness and providing a second region on the substrate for formation of a second field effect transistor having a second gate dielectric layer of a second thickness; b) providing the first gate dielectric layer and a first conductive gate layer over the first and second regions; c) patterning the first conductive layer to define a first gate of the first field effect transistor in the first region while leaving the first conductive layer not patterned for gate formation for the second field effect transistor in the second region; d) after defining the first gate, stripping the first conductive layer and the first gate dielectric layer from the second region; e) after stripping the first conductive layer and the first gate dielectric layer from the second
    Type: Grant
    Filed: August 19, 1997
    Date of Patent: November 23, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Jeffrey W. Honeycutt
  • Patent number: 5943566
    Abstract: After the formation of a gate oxide layer, a polysilicon layer is formed right away. The polysilicon layer is used for patterning the gate oxide layer. The photolithography and etching processes of forming the buried contact window are combined with the step of removing the gate oxide layer at the periphery circuit region. Then, after the formation of the gate oxide layer at the memory cell region, one thermal oxidation process is performed to form the gate oxide layer at the periphery circuit region.
    Type: Grant
    Filed: May 26, 1998
    Date of Patent: August 24, 1999
    Assignee: United Semiconductor Corp.
    Inventor: Jyh-Ming Wang
  • Patent number: 5861347
    Abstract: A method for form an integrated circuit device begins by growing a tunnel oxide (22). The tunnel oxide is exposed to a nitrogen containing ambient whereby nitrogen is incorporated at atomic locations at the interface between the tunnel oxide (22) and a substrate (11). This tunnel oxide and nitrogen exposure is performed for all of a floating gate active area (12), a high voltage active area (14) and a logic gate active area (16). A floating gate electrode (24) and interpoly dielectric regions (26 through 30) are then formed in the floating gate region (12). The tunnel oxide (22) is etched from the active areas (14 and 16) whereby nitrogen contamination (32) may remain. An optional sacrificial oxidation and a low temperature 830.degree. C. wet oxidation process utilizing HCL, H2 and O2 is then used to grow a high voltage gate dielectric (34) which has been shown to improve charge to breakdown characteristics by a factor of 1,000.
    Type: Grant
    Filed: July 3, 1997
    Date of Patent: January 19, 1999
    Assignee: Motorola Inc.
    Inventors: Bikas Maiti, Wayne Paulson, James Heddleson
  • Patent number: 5849611
    Abstract: A wiring formed on a substrate is oxidized and the oxide is used as a mask for forming source and drain impurity regions of a transistor, or as a material for insulating wirings from each other, or as a dielectric of a capacitor. Thickness of the oxide is determined depending on purpose of the oxide.In a transistor adapted to be used in an active-matrix liquid-crystal display, the channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: December 15, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akira Mase, Masaaki Hiroki, Yasuhiko Takemura, Hongyong Zhang, Hideki Uochi
  • Patent number: 5712203
    Abstract: A process for fabricating memory cells of a read-only memory (ROM) device is disclosed. First, a silicon dioxide layer and a silicon nitride layer are successively formed on the surface of a silicon substrate. These layers are patterned by etching to form a plurality of parallel barrier strips extending along a first direction on the surface of the substrate. Impurities are then implanted into the silicon substrate by using the barrier strips as masks, to form a plurality of buried bit lines in the areas between the barrier strips. Next, insulating sidewall spacers are formed on the sidewalls of the barrier strips. A metal silicide layer is then formed over the exposed surface of the buried bit lines in a self-aligned process. A thick dielectric layer is then formed overlying the barrier strips, the insulating sidewall spacers, and the metal silicide layer.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: January 27, 1998
    Assignee: United Microelectronics Corporation
    Inventor: Chen-Chung Hsu
  • Patent number: 5691217
    Abstract: A method of forming a pair of field effect transistors having different thickness gate dielectric layers includes, a) providing a first region on a substrate for formation of a first field effect transistor having a first gate dielectric layer of a first thickness and providing a second region on the substrate for formation of a second field effect transistor having a second gate dielectric layer of a second thickness; b) providing the first gate dielectric layer and a first conductive gate layer over the first and second regions; c) patterning the first conductive layer to define a first gate of the first field effect transistor in the first region while leaving the first conductive layer not patterned for gate formation for the second field effect transistor in the second region; d) after defining the first gate, stripping the first conductive layer and the first gate dielectric layer from the second region; e) after stripping the first conductive layer and the first gate dielectric layer from the second re
    Type: Grant
    Filed: January 3, 1996
    Date of Patent: November 25, 1997
    Assignee: Micron Technology, Inc.
    Inventor: Jeffrey W. Honeycutt
  • Patent number: 5691214
    Abstract: A method of manufacturing a semiconductor device furnished on a silicon substrate with a bipolar element part and a resistance element part formed of an impurity diffusion layer, having (a) a step of forming a first oxide film on said silicon substrate and on the component elements formed on said substrate throughout the entire surface thereof, (b) a step of selectively and sequentially removing the part of said first oxide film corresponding to the base region of said bipolar element part and the surface of said silicon substrate directly underlying said first oxide film and, at the same time, cleaning the freshly exposed surface, (c) a step of forming a second oxide film on said silicon substrate and said component elements formed thereon throughout the entire surface thereof thereby differentiating the thickness of the oxide film formed on said base region and the thickness of the oxide film formed on said resistance element part, and (d) a step of selectively and instantaneously implanting an ion into sai
    Type: Grant
    Filed: October 4, 1996
    Date of Patent: November 25, 1997
    Assignee: NEC Corporation
    Inventor: Masaru Wakabayashi
  • Patent number: 5679586
    Abstract: This is a method of making a semiconductor device comprising covering a first semiconductor compound having a plurality of windows on a major surface of a semiconductor body, covering a second semiconductor compound on selected windows of the first compound, forming openings in the second compound over the selected windows, forming electrodes by introducing an impurity in the semiconductor body through the openings.
    Type: Grant
    Filed: October 14, 1993
    Date of Patent: October 21, 1997
    Assignee: Seagate Technology, Inc.
    Inventors: Richard Anthony Alexis Rodrigues, Ewen Gillespie
  • Patent number: 5672521
    Abstract: An integrated circuit device and manufacturing process wherein a first region is formed in a substrate with a dopant that enhances oxide formation and a second region is formed in the substrate with a dose of nitrogen that retards oxide formation. An oxide layer is grown over the first and the second regions and over a third region of the substrate such that the first, second, and third regions yield differing thicknesses of the oxide layer.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: September 30, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Radu M. Barsan, Xiao-Yu Li, Sunil Mehta
  • Patent number: 5668034
    Abstract: High voltage MOS transistors are fabricated contemporaneously with scaled flash EEPROM array transistors. Active silicon regions separated by field oxide isolation structures are formed as in the prior art. A sacrificial thermal oxide layer simultaneously removes Kooi effect residual nitridization and provides gate oxide for the high voltage transistors of a thickness commensurate with the high voltage application. The sacrificial oxide is thereafter removed from all circuit areas except over high voltage device active areas. Growth of tunnel oxide, first polysilicon, interpoly dielectric, peripheral gate oxide and second polysilicon layers as well as patterning of the layers are accomplished in a known manner. The second polysilicon layer is patterned to create lines which lie within lines formed of the first polysilicon layer, the second polysilicon layer aiding controlling the final channel length of the high voltage devices.
    Type: Grant
    Filed: May 14, 1996
    Date of Patent: September 16, 1997
    Assignee: Intel Corporation
    Inventors: George E. Sery, Jan A. Smudski
  • Patent number: 5614425
    Abstract: An N type diffusion layer as a collector is formed on a P type silicon substrate, and a field oxide film is formed on this diffusion layer. An MoSi.sub.2 film is formed on this field oxide film and a first opening is formed on those field oxide film and MoSi.sub.2 film to expose the diffusion layer. An N type layer is selectively epitaxially grown only on the bottom of the first opening. A base layer is formed on the N type layer, the side wall of the first opening and the MoSi.sub.2 film. The base layer on the N type layer is formed by epitaxial growth, while the base layer on the side wall of the first opening and the MoSi.sub.2 film is formed in a polycrystalline state. A first silicon oxide film is formed on this based layer. The first silicon oxide film is thinner on the polycrystalline base layer than on the epitaxially grown base layer. The first silicon oxide film is subjected to anisotropic etching to expose only the surface of the epitaxially grown base layer.
    Type: Grant
    Filed: March 27, 1996
    Date of Patent: March 25, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Kimura, Hiroshi Naruse
  • Patent number: 5576226
    Abstract: A method of fabricating a memory device for improving the reliability of the cell area and the driving capability of the peripheral area is disclosed, wherein the method comprises the steps of forming a cell area and a peripheral area by forming a field oxidation layer over a first conductive semiconductor substrate, forming gate oxidation layers of the different thickness from each other over a surface of the substrate which corresponds to the cell area and the peripheral area through once oxidation process, forming a gate over the gate oxidation layer, and implanting a second conductive impurity ion into the substrate partly covered with the gates as a mask to form highly-doped source/drain areas in the respective cell and peripheral area, thereby forming respective MOS transistors on each of the cell area and the peripheral area.
    Type: Grant
    Filed: May 17, 1994
    Date of Patent: November 19, 1996
    Assignee: LG Semicon Co., Ltd.
    Inventor: Hyun S. Hwang
  • Patent number: 5554545
    Abstract: An MOSFET device is fabricated with a plurality of conductors capacitively coupled to a first electrode, forming a mask on the surface of the first electrode exposing a predetermined zone of the first electrode, doping the first electrode through the mask, removing the mask from the surface of the first electrode, oxidizing the first electrode to form a layer of oxide over the first electrode with a thicker layer of oxide over the predetermined zone and a thinner layer of oxide elsewhere, forming at least one electrode over the first electrode on the thinner layer of oxide outside of the zone and forming at least one other electrode over the first electrode on the thicker layer of oxide inside the zone, whereby the one electrode and the other electrode have substantially different capacitive coupling to the electrode.
    Type: Grant
    Filed: September 1, 1994
    Date of Patent: September 10, 1996
    Assignee: United Microelectronics Corporation
    Inventors: Chung-Cheng Wu, Ming-Tzong Yang
  • Patent number: 5521107
    Abstract: An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.
    Type: Grant
    Filed: March 29, 1994
    Date of Patent: May 28, 1996
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akira Mase, Masaaki Hiroki, Yasuhiko Takemura, Hongyong Zhang, Hideki Uochi, Hideki Nemoto
  • Patent number: 5459106
    Abstract: An AlGaAs chip which has an n-type layer and a p-type layer is immersed in an aqueous solution containing 0.2-0.6 wt. % of ammonia and 25-35 wt. % of hydrogen peroxide to form a primary protective layer, and after drying the AlGaAs chip, the AlGaAs chip is for a second time immersed in an aqueous solution containing 0.2-0.6 wt. % of ammonia and 25-35 wt. % of hydrogen peroxide to form a secondary protective layer.
    Type: Grant
    Filed: September 22, 1994
    Date of Patent: October 17, 1995
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masato Yamada, Tadashi Sakurai
  • Patent number: 5426065
    Abstract: An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node.
    Type: Grant
    Filed: November 30, 1993
    Date of Patent: June 20, 1995
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Tsiu C. Chan, Frank R. Bryant
  • Patent number: 5358894
    Abstract: A LOCOS process is enhanced by enhancing the depth of field oxide in regions having a narrow field oxide width. Subsequent to forming a pattern of nitride to define the field oxide and active area, photoresist is applied to selected areas of the wafer. An impurity is then applied to the underlying semiconductor substrate in areas not protected by photoresist and nitride. The impurity results in an enhanced oxidation rate and therefore compensates for a thinning effect in selected field oxide areas, such as those having a narrow width. Subsequent formation of the field oxide results in the doped material being consumed by the oxide.
    Type: Grant
    Filed: December 30, 1993
    Date of Patent: October 25, 1994
    Assignee: Micron Technology, Inc.
    Inventors: Pierre Fazan, Viju Mathews, Gurtej S. Sandhu, Mohammed Anjum, Hiang C. Chan
  • Patent number: 5352618
    Abstract: A method for making submicron dielectric windows for electron tunneling between a floating gate and substrate in a semiconductor EEPROM device. A mask edge overlying an oxide layer on a substrate is undercut a small distance, the area surrounding that small distance is built up with oxide, then a thin layer of oxide is formed in the undercut distance to serve as a tunneling window.
    Type: Grant
    Filed: July 30, 1993
    Date of Patent: October 4, 1994
    Assignee: Atmel Corporation
    Inventors: Bradley J. Larsen, Donald A. Erickson
  • Patent number: 5330920
    Abstract: A method of controlling gate oxide thickness in the fabrication of semiconductor devices wherein a sacrificial gate oxide layer is formed on a semiconductor substrate surface. Nitrogens ions are implanted into select locations of the substrate through the sacrificial gate oxide layer, and the substrate and the gate oxide layer are then thermally annealed. The sacrificial gate oxide layer is then removed and a gate oxide layer is then formed on the substrate layer wherein the portion of the gate oxide layer formed on the nitrogen ion implanted portion of the substrate is thinner than the portion of the gate oxide layer formed on the non-nitrogen ion implanted portion.
    Type: Grant
    Filed: June 15, 1993
    Date of Patent: July 19, 1994
    Assignee: Digital Equipment Corporation
    Inventors: Hamid R. Soleimani, Brian S. Doyle, Ara Philipossian
  • Patent number: 5308781
    Abstract: A semiconductor memory device comprising a substrate, a longitudinal source diffusion layer for a plurality of memory transistor source regions continuously formed on the substrate, and a longitudinal drain diffusion layer for a plurality of memory transistor drain regions continuously formed on the substrate in parallel to the source diffusion layer. A word line is formed crossing over the diffusion layers. And an electrically insulating film is interposed between the word line and the diffusion layers. The insulating film is thicker than a gate oxide film formed between the diffusion layers.
    Type: Grant
    Filed: January 13, 1993
    Date of Patent: May 3, 1994
    Assignee: Ricoh Company, Ltd.
    Inventors: Yuichi Ando, Koichi Sogawa, Norio Yoshida, Masao Kiyohara
  • Patent number: 5279985
    Abstract: The present invention relates to a semiconductor device and a method of fabrication of the same, said semiconductor device including a capacitive structure comprising of a lower layer electrode consisting of a silicon material, a capacitive insulating film consisting of a tantalum oxide film and an upper layer electrode, said upper layer electrode comprising at least a titanium nitride film for covering said capacitive insulating film. Said method of fabrication comprises the steps of: forming the lower layer electrode; forming the capacitive insulating film for covering said lower layer electrode; and forming the titanium nitride film for covering said capacitive insulating film.
    Type: Grant
    Filed: September 15, 1992
    Date of Patent: January 18, 1994
    Assignee: NEC Corporation
    Inventor: Satoshi Kamiyama
  • Patent number: 5240875
    Abstract: The present invention is directed to a technique for selectively oxidizing trench side walls in a silicon substrate. Each of the side walls can be oxidized individually and to different thicknesses according to the requirements of the trench IC.
    Type: Grant
    Filed: August 12, 1992
    Date of Patent: August 31, 1993
    Assignee: North American Philips Corporation
    Inventor: Len-Yuan Tsou
  • Patent number: 5219797
    Abstract: A gallium arsenide surface is treated and made ready for passivation by esing the gallium arsenide surface to silicon monoxide (SiO) vapor under a vacuum at about 450.degree. C. for a short time.
    Type: Grant
    Filed: August 31, 1992
    Date of Patent: June 15, 1993
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Gary J. Gerardi, Edward H. Poindexter, Fang Rong
  • Patent number: 5106768
    Abstract: The present method uses a one block out mask method for forming both the N channel and P channel MOS field effect transistors by providing a special oxidizing method that grows sufficient silicon oxide upon the already formed N+ source/drain regions which is sufficient to block the P+ ion implantation which forms the P channel device from the N channel device area.
    Type: Grant
    Filed: August 31, 1990
    Date of Patent: April 21, 1992
    Assignee: United Microelectronics Corporation
    Inventor: Kuo-Yun Kuo
  • Patent number: 5079191
    Abstract: A semiconductor device having a large-capacitance capacitor in which an insulator film is formed underneath a film made of a material having a high dielectric constant, such as tantalum oxide, in such a manner that a portion of the insulator film underneath a defect region which is undesirably thin is thicker than other portions of the insulator film, thereby preventing occurrence of a failure in terms of dielectric strength and deterioration of the lifetime of the capacitor which would otherwise be caused by the existence of the defect region. Also disclosed is a process for producing such semiconductor device. Thus, it is possible to effectively prevent occurrence of problems which would otherwise be caused when a material having a high dielectric constant, such as tantalum oxide, is employed as a dielectric film of a capacitor, so that the reliability of a semiconductor having a large-capacitance capacitor is greatly improved.
    Type: Grant
    Filed: May 1, 1990
    Date of Patent: January 7, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Shinriki, Yasushiro Nishioka, Noriyuki Sakuma, Kiichiro Mukai
  • Patent number: 4892838
    Abstract: A method of manufacturing a semiconductor device in which a lateral insulated gate field effect transistor (IGFET) (1) is provided by defining an insulated gate structure (12) on a given surface (3a) of a semiconductor body (3) by providing an insulating layer on the given surface (3a) having a relatively thin region on a first area of the given surface adjoining a relatively thin region (14a) on a second area (31b) of the given surface and providing a conductive layer (15,16) on the insulating layer to define an insulated gate over the first area of the given surface with the conductive layer extending up onto the relatively thick region of the insulating layer.
    Type: Grant
    Filed: May 23, 1988
    Date of Patent: January 9, 1990
    Assignee: U.S. Philips Corporation
    Inventors: Carole A. Fisher, David H. Paxman
  • Patent number: 4877751
    Abstract: An N+ poly-to-N+ silicon capacitor structure is provided by adding a single mask step to a standard CMOS process flow. The capacitor oxide between the N+ poly plate and the N+ silicon plate is grown simultaneously with gate oxide for the MOSFET devices. A high dose, deep phosphorous implant is employed to form the N+ substrate plate. This results in an excellent capacitance voltage coefficient. The resulting thin interplate oxide leads to high capacitance per unit area and, thus, small die size.
    Type: Grant
    Filed: March 11, 1988
    Date of Patent: October 31, 1989
    Assignee: National Semiconductor Corporation
    Inventors: Chih-Sieh Teng, Tian-I Liou, Hiekyung Chun-Min
  • Patent number: 4840920
    Abstract: In a method of manufacturing a semiconductor device according to the present invention, regions of first conductivity type buried layers formed on a first conductivity type substrate are retracted with respect to regions of second conductivity type buried layers. Thus, in formation of second conductivity type epitaxial layer, first conductivity type impurity contained in the first conductivity type buried layers is prevented from floating diffusion up to element regions of the second conductivity type epitaxial layers. At the same time, the semiconductor device can be implemented with high density of integration.
    Type: Grant
    Filed: September 25, 1987
    Date of Patent: June 20, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kakutaro Suda
  • Patent number: 4830975
    Abstract: A PRIMOS (Planar Recessed Isolated MOS) transistor and a method for fabricating same is described wherein the source and drain in a semiconductor body are separated by a recess. A gate oxide is disposed on the body in the recess, with conductive gate material thereon. Oxide regions are positioned on each side of the gate, such oxide regions being substantially thicker in cross-section than the gate oxide. The method described teaches fabrication of this device.
    Type: Grant
    Filed: November 27, 1987
    Date of Patent: May 16, 1989
    Assignee: National Semiconductor Corporation
    Inventors: Arthur J. Bovaird, Reza Fatemi