Abstract: A distribution feedback laser diode, comprises a substrate, a waveguide layer provided on the substrate, an active layer provided on the waveguide layer, a diffraction grating provided at an interface between the substrate and the waveguide layer for reflecting an optical radiation formed in the active layer back and forth, a clad layer provided on the active layer for confining the optical radiation within the active layer, a plurality of segmented electrodes provided on the top surface of the clad layer along an elongated direction of the laser diode for injecting the carriers into the active layer, wherein at least one of the segmented electrodes is provided in correspondence to a part of the active layer in which the optical radiation formed in the active layer has a maximum intensity level, and a backside electrode provided at the bottom surface of the substrate for injecting the carriers into the active layer through the substrate.

Abstract: A method of forming and refilling a trench in a substrate. First a trench is formed in the substrate. The trench is then refilled with a conformal material. Next, a recess is etched into the top portion of the refilled trench. The recess is then refilled with a second material until the refilled recess and substrate are substantially planar.

Abstract: A method of forming micro-trench isolation regions with a separation of 0.20 .mu.m to 0.35 .mu.m in the fabrication of semiconductor devices involves forming an silicon dioxide layer on select locations of a semiconductor substrate and depositing a polysilicon layer onto the silicon dioxide layer. A layer of photoresist is then deposited over select areas of the polysilicon layer and patterned to form micro-trench isolation regions of widths between about 0.2 .mu.m to about 0.5 .mu.m and aspect ratio of between about 2:1 to about 7:1. Thereafter, the isolation regions are etched for a time and pressure sufficient to form micro-trenches in the substrate surface. The micro-trenches will generally have a width ranging from about 1000 .ANG. to about 3500 .ANG. and depth ranging from about 500 .ANG. to about 5000 .ANG.. The layer of photoresist is then removed to expose the polysilicon layer and a channel stop implant is deposited and aligned with the micro-trenches.

Abstract: The present invention relates to a manufacturing method of a contact of a multi-layered metal line of a highly integrated semiconductor device.The insulating layer between the metal lines is flattened and step coverage is improved by using a SOG layer or polyimide.

Abstract: In manufacturing a semiconductor substrate having a dielectric isolation structure, a dielectric film is formed at a semiconductor layer formed by epitaxial growth. Grooves for carrying out dielectric isolation to deposit filler thereon thereafter are used to polish the deposited filler. The polishing condition is obeyed where polishing rate ratio of the filler to the dielectric film is one fifth or less. Thus, an active semiconductor layer in which where elements are to be formed can be provided with good productivity, state where the flatness thereof is good and the layer thickness is uniformly and precisely controlled.

Abstract: A quantum effect device implementation of the Shannon Decomposition Function in the form of a Shannon Cell is provided in which a first quantum dot logic unit (50) is coupled between the X input and the output of the Shannon Cell. A second quantum dot logic unit (52) is coupled between the Y input and the output of the Shannon Cell. The control input to the Shannon Cell is coupled to both the first and second quantum dot logic units (50 and 52) such that current flows through the appropriate quantum dot logic unit (50 or 52) depending upon the logic state of the control input.

Abstract: A semiconductor device includes an N.sup.- type semiconductor layer (2). The N.sup.- type semiconductor layer (2) includes a triangular pole trench (10), an apex portion thereof contains a gate electrode (5). The trench (10) penetrates the semiconductor layer (2) and a P type well region (3) and projects into an N.sup.+ type source region (4). A source electrode (7) is disposed so as to be insulated from the semiconductor layer (2) by an oxide film (9) and in contact with the well region (3) and the source region (4). A drain electrode (8) is connected to the semiconductor layer (2) through an N.sup.+ type semiconductor substrate (1). With higher potential at the gate electrode (5) than at the source electrode (7), the well region (3) is partially inverted into N type near the trench (10). Thus, the semiconductor device is turned on due to a channel created associated to the conductivity type inversion. Most of current flow allowed in the semiconductor layer (2) by the channel flows near the trench (10).

Abstract: A conductive layer is formed on a semiconductor substrate, and is etched so that a side face of the conductive layer is reversely-tapered. Also, a sidewall insulating layer is formed on the side face of the conductive layer. Then, a groove is formed within the semiconductor substrate with a mask of the sidewall insulating layer, and an isolation insulating layer is buried within the groove.

Abstract: A dielectrically isolated substrate is comprised of a single-crystal silicon substrate or bond substrate and a single-crystal silicon substrate or base substrate bonded together into a composite structure. The bond substrate has a (110) plane as a main crystal plane and is provided with vertically walled moats and substantially squared islands positioned adjacent to the moats. The moats and islands result from anisotropic etching using a specific mask pattern. Also disclosed is a process for producing the composite structure.

Abstract: An SOI wafer has a device layer of initial thickness that is formed into a set of mesas in the interval between which a temporary layer of polysilicon is deposited to a precisely controlled thickness. This polysilicon is entirely converted in a self-limiting process to an oxide etch stop having a thickness much smaller than the initial thickness. The mesas are thinned by a chemical mechanical polishing technique until the mesa is the same level as the top surface of the new oxide. The etch stop layer of oxide is not removed but serves both as an isolating layer to provide dielectric isolation between mesas in the final circuit and also as a visual gauge to determine the time when the polishing process should stop.

Abstract: Photoconductive semiconductor material is injected into narrow and closely paced cylindrical channels in an insulating matrix plate to form pixel elements of a high resolution photodetector array. A transparent conductive layer is deposited on one surface of the photoconductor array while light reflecting pads are formed on the elements at the opposite surface. Subsequently, a layer of light modulating material and a transparent conductive layer are deposited on the opposite surface to obtain a high resolution spatial light modulator.

Abstract: A metal connection for an integrated circuit device is effectively "cast" in place at any level of an integrated circuit. The "mold" for the connection is formed by depositing and patterning a sacrificial material, such as aluminum oxide or other metal oxides, and covering the sacrificial material with a protective material such as silicon dioxide or other insulators. After forming bore holes to the deposit of sacrificial material through the protective layer, the sacrificial material is removed by isotropic etching to form a cavity beneath and at least partially overlaid by the protective layer. Alternatively, a defect may be produced below the protective layer and filled with metal either with or without enlargement by further removal of material. This cavity is then filled with metal by deposition of the metal by, for instance, evaporation, sputtering and chemical vapor deposition or combinations thereof.

Abstract: A method is disclosed for producing integrated circuit apparatus in which electroconductive interconnection films are disposed adjacent to each other and have an insulating film sandwiched therebetween. The electroconductive films are electrically connected with each other via a through-hole formed in the insulating film. First, a through-hole is formed in an insulating film so as to extend to the surface of a first electroconductive interconnection film. Then, extraneous materials existing on the surfaces of the insulating film and the electroconductive film exposed in the through-hole are removed by a sputter etching method. Next, an insulating film covering film ("covering film") is formed by a sputtering method on said insulating film by using a material which is the same material that is used for forming a second electroconductive interconnection film. Subsequently, the sputter etching method is used again to remove the covering film.

Abstract: A reactive ion etching process is used for the fabrication of submicron, single crystal silicon, movable mechanical structures and capacitive actuators. The reactive ion etching process gives excellent control of lateral dimensions while maintaining a large vertical depth in the formation of high aspect-ratio freely suspended single crystal silicon structures. The silicon etch process is independent of crystal orientation and produces controllable vertical profiles.

Abstract: An improved process for planarizing an isolation barrier in the fabrication of a semiconductor chip involves reducing the etch rate of the field oxide independently of the sacrificial oxide layer. The field oxide layer is implanted with nitrogen ions and then thermally annealed resulting in a hardened and densified field oxide. In subsequent operations, a sacrificial oxide layer is formed on the semiconductor top surface by thermal oxidation. Upon etching with HF, the etch rate of the hardened field oxide is significantly reduced relative to untreated field oxide. Thus, the exposed hardened field oxide is etched at about the same rate as the sacrificial oxide layer. In the example given, the etch rate of untreated densified TEOS field oxide in 10:1 HF is 6.90 .ANG./sec, while the etch rate of TEOS field oxide hardened according to the processes of this invention is 5.90 .ANG./sec. After planarization using the hardened field oxide, depressions in the isolation barrier are eliminated.

Abstract: The process of making a registration mark on an integrated-circuit substrate wherein photoimaging first is used to define an optically-recognizable mark on a predetermined position of the substrate, and the substrate then is covered with silicon dioxide. Photoresist then is applied over the substrate and selectively removed except over the mark. Etchant then is applied to remove all silicon dioxide except over the photoresist-covered mark. An epitaxial layer thereafter is grown over the substrate. The silicon dioxide over the mark prevents epitaxial growth in that region, so that the mark remains clear and optically visible for the rest of the IC processing.

Abstract: Various techniques of forming isolation structures between adjacent diffusion regions are disclosed. In one technique, a thermally-grown oxide isolation structure is gouged out, and subsequent poly extending into the gouged out isolation structure is substantially level with the diffusion 58 region. In another technique, a trench (bathtub) is formed, lightly oxidized, overfilled with polysilicon or amorphous silicon, gouged out, and thermally treated to form a substantially planar isolation structure. In another technique, an isolation structure exhibiting bird's-heads and bird's-beaks is polished until the bird's-beaks are removed. Gouging of the diffusion area may be permitted to occur. A bipolar transistor structure can be formed in the gouged diffusion area, and will exhibit reduced spacing between the intrinsic base and collector without proportionally reduced spacing between the extrinsic base and the collector.

Abstract: There is disclosed in the present invention a method for manufacturing a semiconductor device including an isolation region defined by trenches having different or equal widths respectively on a single semiconductor substrate comprising the steps of:forming insulating films on the semiconductor substrate and then forming an aperture on a passive region (isolation region);forming spacers of etch rate different from that of the insulating films on sidewalls of the aperture to define ring-shaped trench regions surrounding outline of active regions;forming another insulating film of etch rate different from that of the spacers on the substrate where the spacers are defined and removing the spacers by etching to expose the substrate within the etched spacers; andforming trenches on the exposed area of the substrate, forming an insulating film of equal character to that of the insulating films used at the time of the formation of the aperture to refill the trenches and forming the spacers on the sidewalls of the in

Abstract: A first insulating layer is deposited over the surface of a silicon substrate. Those portions of the first insulating layers not covered by a mask pattern are etched through to the silicon substrate so as to provide a plurality of wide and narrow openings exposing portions of the silicon substrate that will form the device isolation regions. A second insulating layer is deposited overlying the patterned first insulating layer. A layer of an aluminum-silicon alloy is deposited overlying the second insulating layer. The aluminum-silicon layer is etched away whereby silicon nodules are formed on the surface of the second insulating layer. The second insulating layer is etched through to the first insulating layer where it exists and to the silicon substrate surface where the substrate is exposed within the wide and narrow openings. A first set of narrow trenches is etched into the exposed portions of the silicon substrate within the wide and narrow openings using the silicon nodules as a mask.

Abstract: A method and the resulting product for isolating lightly doped silicon islands from each other and from a common substrate. The substrate is covered with a first heavily doped epi layer. The first layer is covered with a lightly doped second epi layer. A pair of spaced deep trenches are provided which extend from the top surface of the second layer, through the first layer and into the substrate. The interior walls of the trenches are lined with oxide. A pair of heavily doped reach-through diffusions extending from said top surface to the first layer is oriented perpendicularly to the deep trenches and fully extends between the trenches. The heavily doped reach-through diffusions and the contiguous first layer are removed by a single anisotropic etching step to yield silicon islands isolated by air except where the islands contact the oxide-lined deep trenches. The air isolation preferably is partially replaced with other dielectric material.

Abstract: The present invention provides a method of forming a semiconductor device mprising the steps of:forming a glass block of an acid inert glass having acid etchable glass rods extending therethrough, the acid etchable glass rods having an average diameter of less than 1 micron;partially etching one end of the acid etchable rods surface of the glass block to form cavities in the glass block on one surface thereof having an average diameter of less than 1 micron;depositing material(s) in the cavities to form a semiconductor device.The present invention also provides a method for forming a semiconductor device in which the acid etchable glass rods are completely etched and the deposition material(s) is deposited to fill the nanochannels formed by the etching.The present invention also provides semiconductor devices made by these methods.

Abstract: An isolation structure for bipolar and CMOS circuits formed during the same processing steps to optimize the integration of bipolar and CMOS circuits. A deep trench (46) is formed in a semiconductor circuit for providing deep isolation for bipolar circuits. A shallow recess (56) is then formed, which also forms a stepped sidewall structure of the deep trench. The recess (56) and the trench (46) are covered by an insulating oxide (60), and thereafter filled with an undoped polysilicon (62) to form the different isolating structures for the different types of circuits.

Abstract: A fabrication method for a microstructure having a vacuum sealed cavity therein including the process steps of forming an aluminum filled cavity in a body of silicon material and heating the structure such that the aluminum is absorbed into the silicon material leaving a vacuum in the cavity. In one embodiment of the invention a cavity is etched into a silicon wafer and filled with aluminum. A silicon dioxide layer is formed over the aluminum filled cavity and the structure is heated to produce the vacuum cavity.

Abstract: A pad silicon oxide layer is deposited over the surface of a silicon substrate. A silicon nitride layer is deposited overlying the pad silicon oxide layer. Portions of the silicon nitride and pad silicon oxide layers not covered by a mask pattern are etched through and into the silicon substrate so as to provide a plurality of wide and narrow trenches within the silicon substrate that will form the device isolation regions. Channel-stops are selectively ion implanted through the openings into the substrate underneath the trenches. The silicon nitride and pad oxide layers are removed. A thin silicon oxide layer is grown conformally on all surfaces of the substrate and within the trenches. A thick layer of silicon oxide is deposited over the surface of the substrate completely filling the trenches wherein the thick silicon oxide layer is planarized over the narrow trenches but is not planarized over the wide trenches.

Abstract: A semiconductor processing device isolation method includes: a) providing non-LOCOS insulating device isolation blocks by trench and refill technique on a substrate to define recessed moat volume therebetween; b) providing gate dielectric within the moat volume; c) providing a layer of electrically conductive material over the substrate and gate dielectric to a thickness sufficient to completely fill the moat volume between adjacent isolation blocks; d) chemical-mechanical polishing the layer of electrically conductive material to provide a planarized upper electrically conductive material surface; e) photopatterning and etching the layer of electrically conductive material to provide an electrically conductive runner which overlies a plurality of the isolation blocks and to selectively remove the electrically conductive material from within selected regions of moat volume to define field effect transistor gates within the moat volume; and f) providing conductivity enhancing impurity through the selected regi

Abstract: Expedient fabrication of fine-featured integrated circuits entails aperture pattern delineation to produce a masking layer atop a semiconductor body followed by insertion within a controlled atmosphere chamber within which device-functional layered material is epitaxially grown within apertures. Critical, device-consequential properties of epitaxial material is assured by removal of a thin surface layer of material revealed during delineation. Such removal, sufficient to eliminate meaningful contamination and/or crystalline damage introduced during delineation, is of sufficiently small quantity as to be accommodated within the chamber. Under most circumstances, the controlled atmosphere is at reduced pressure as required for e.g. MOMBE epitaxial growth.

Abstract: A semiconductor light emitting device includes a vertical aperture produced at a main surface of a semi-insulating or insulating substrate, a transverse aperture provided in the substrate communicating with the vertical aperture, a conducting semiconductor layer buried in the vertical aperture and the transverse aperture, a groove produced by etching the substrate from the surface thereof until reaching the conducting semiconductor layer at a portion of the transverse aperture, and a light emitting element produced in the groove, and the light emitting region of the element being buried in the groove and connected with the buried conducting semiconductor layer. Accordingly, no pn junction exists at the periphery of the light emitting region, and a semiconductor light emitting element of quite low parasitic capacitance is obtained at high yield. A planar structure in which two electrodes are produced at the same plane is obtained, resulting in ease of integration and enhancement of the integration density.

Abstract: According to a method for producing semiconductor chips, first grooves are formed in a semiconductor wafer at a front surface, dividing the semiconductor water into a plurality of regions, each region including a single device or an integrated circuit; a first metallization layer is formed in the first grooves; the semiconductor wafer is thinned to a desired thickness from the rear surface of the wafer; second grooves are formed in the semiconductor wafer at the rear surface at positions opposite the first grooves, exposing the first metallization layer; a second metallization layer is formed in the second grooves; a metal layer for heat radiation is formed on the rear surface of the wafer but not on the second metallization layer; and the first and second metallization layers in the first grooves are cut with a dicing blade to produce a plurality of semiconductor chips.

Abstract: A method of adjusting the temperature of a semiconductor wafer comprising mounting and attracting the wafer on a susceptor in a process chamber, exhausting and decompressing the process chamber, controlling the temperature of the wafer to become equal to a process temperature while cooling or heating the susceptor, supplying process gas into the chamber to process the wafer with this process gas, and introducing CF.sub.4 gas into interstices between the wafer and the susceptor through the susceptor to allow heat exchange to be achieved between them. CF.sub.4 gas includes same components as at least some of those of the process gas and it is more excellent in heat transmitting characteristic than helium gas. Even when CF.sub.4 gas is leaked into a process area, therefore, any influence is not added to the process.

Abstract: A trench mask containing SiO.sub.2 is produced on a substrate (1) of single-crystal silicon. After deposition of a first Si.sub.3 N.sub.4 layer, first Si.sub.3 N.sub.4 spacers (31) are formed by anisotropic etching, and a first trench is etched to a first depth (t.sub.1). After selective removal of passivation layers arising in the first trench etching and after deposition of a second Si.sub.3 N.sub.4 layer, second Si.sub.3 N.sub.4 spacers (41) are formed by anisotropic etching. A second trench is etched to a second depth (t.sub.2), whereby the trench structure (5) is formed to a total depth (t.sub.1 and t.sub.2).

Abstract: For making an isolation region on a semiconductor substrate without forming an unwanted bird beak, after forming an insulating film on the semiconductor substrate, the substate surface is covered with a resist mask. An LPD SiO.sub.2 film is deposited on the unmasked portion of the substrate surface, using a hydrofluoric acid solution containing silicon dioxide so as to be supersaturated. Thereafter, the mask is removed from the substrate surface. Further, after a groove is formed in the semiconductor substrate, it may be filled with the LPD SiO.sub.2 film to provide the isolation region in the substrate.

Abstract: A process for forming within a masking layer self-aligned narrow isolated spacings having a width that is substantially narrower than the space width that can be created directly using the maximum resolution of available photolithography and the process for utilizing said masking layer to form narrow isolated trenches in a semiconductor substrate.

Abstract: The method of the present invention introduces a fabrication method for providing capacitor cell polysilicon isolation from a polysilicon contact plug in a semiconductor fabrication process, by providing a contact opening through a first insulating layer, the cell polysilicon layer, and a second insulating layer, thereby exposing patterned edges of the cell polysilicon and providing access to an underlying diffusion area. The contact opening is then filled with a conductively doped polysilicon and an upper portion the polysilicon filler is removed until its top surface is recessed below the bottom surface of the cell polysilicon. Next, the cell polysilicon's patterned edges and the top of the first conductive material are oxidized which is followed by an anisotropic etch to remove the oxide only from the top of the polysilicon filler while retaining a major portion of the oxide on the cell polysilicon's patterned edges. Finally, the contact opening is refilled with conductively doped polysilicon.

Abstract: A method for forming field oxide regions includes the formation of cavities in a semiconductor substrate. A layer of thermal oxide is then grown on the substrate. A layer of planarizing material is deposited over the device, filling the cavities. The planarizing layer is etched back to expose a portion of the cavities. A conformal layer of undoped oxide or a layer of polycrystalline silicon that is converted to oxide is deposited over the device, followed by a second layer of planarizing material, The planarizing material and conformal layer are then etched back to expose the active areas in the substrate.

Abstract: A semiconductor device manufacturing process and a bias ECRCVD apparatus for the process. The semiconductor device manufacturing process comprises the steps of forming trenches in the surface of a substrate, forming an insulating film by bias ECRCVD over the surface of the substrate, etching the insulating film by lateral leveling etching so as to expand the width of grooves formed in portions of the insulating film which are formed in regions other than those corresponding to the trenches, masking the portions of the insulating film which fill the trenches and removing the portions of the insulating film formed in the regions other than those corresponding to the trenches.

Abstract: The present invention is directed to a technique for selectively oxidizing trench side walls in a silicon substrate. Each of the side walls can be oxidized individually and to different thicknesses according to the requirements of the trench IC.

Abstract: A process for forming an IC isolation trench pattern wherein the trenches have varying widths and are filled with near intrinsic single crystal silicon. Thus, the wiring that passes over the trenches has low capacitance and active circuit devices having improved high frequency performance can be fabricated into the silicon in the trenches. This increases the utilization of surface area thereby increasing active device density for VLSI applications.

Abstract: A semiconductor device is provided with an isolation region for isolating the semiconductor device from an adjacent semiconductor device provided commonly on a semiconductor substrate. The isolation region includes a groove extending to a predetermined depth of the substrate, a non-doped silicon oxide layer provided on a whole inner surface of the groove, and a BPSG (boro-phosho-silicate glass) layer filled in a remaining portion of the groove covered with the non-doped silicon oxide layer on the inner surface. An interconnection layer is provided on the isolating region selectively.

Abstract: According to this invention, an isolation trench is formed in a semiconductor substrate. A first insulating film is formed on a surface of the semiconductor substrate and an inner surface of the trench. A silicon oxide film containing phosphorus and boron is buried in the trench in which the first insulating film is formed. A second insulating film pattern having a width larger than that of the trench is formed on the trench and a peripheral portion of the trench. The second insulating film pattern prevents out-diffusion phosphorus and boron in the silicon oxide film. The first insulating film which is not covered with the second insulating film pattern is removed to form a first insulating film pattern. The surface of the semiconductor substrate which is not covered with the first and second insulating film patterns is thermally oxidized.

Abstract: The present invention relates to a method for forming an isolated film on a semiconductor device in the shape of a cylinder to shorten the heat treatment process and to prevent a micro-loading effect of filling of a field-isolated oxide film. The method comprises the step of forming a deep, narrow groove, then filling up the groove with an oxide film, and then oxidizing a polysilicon layer encircled by the groove to form an isolated film in the shape of a cylinder.

Abstract: A semiconductor processing method for forming a substrate isolation trench includes the following steps: a) providing a layer of selected material atop a substrate to a selected thickness; b) providing a sacrificial layer of a selected etch stop material to a selected thickness atop the layer of selected material; c) patterning and etching through the sacrificial layer and selected material layer, and into the substrate to define an isolation trench; d) depositing a trench filling material to a selected thickness atop the substrate and within and filling the isolation trench; e) planarize etching the trench filling material using the sacrificial layer as an effective etch stop for such planarize etching; f) etching the sacrificial layer from the substrate and thereby leaving a pillar of trench filling material projecting upwardly relative to an upper substrate surface; and g) selectively etching the projecting pillar relative to the upper substrate surface.

Abstract: The invention relates to a process for buried localized oxidation of a silicon substrate. The process consists in performing a) a sealing on the surface of the substrate (S), by a first nitriding, by growing a later of silicon nitride forming at least one surface layer, then in performing b) the etching (G1) of a trench (T) intended to receive the buried localized oxidation. A second nitriding is performed c) on the free area of the trench (T) in order to obtain a sealing sc of the walls of the trench (T). An etching (G2) is performed at d) on the bottom wall of the trench (T) by at least partial etching of the silicon nitride layer obtained by second nitriding in order to uncover the substrate material (S). A localized oxidation e) is performed to produce the buried oxidation (OE) of the substrate in the trench. Application to the production of integrated circuits.

Abstract: A dielectric buried layer is formed inside substrates which are directly bonded together. Firstly, a groove or a recess, or both are formed on the principal bonding plane of one of at least two kinds of semiconductor substrates to be bonded together. Once the semiconductor substrates are bonded together, the groove and recess form a space, which is filled with dielectric. Before forming the dielectric buried layer, the invention carries out a process of removing potential damage from corners of the groove and/or recess.

Abstract: A method of fabricating a semiconductor structure includes providing a substrate having at least one layer formed thereon. At least two trenches are formed through the layer and into the substrate wherein at least one trench is for isolation and at least one trench is for making contact to the substrate. After a trench liner is formed on the sidewalls of the trenches, the trenches are filled with doped semiconductor material. The doped semiconductor material in the trench for isolation is then anodized. After the anodization, the anodized trench fill material is oxidized.

Abstract: A process for fabricating isolation regions in a semiconductor substrate which does not depend upon pattern definition capability. In one embodiment a device isolation region (30) is formed in a semiconductor substrate (12) by first creating a trench (18) in the substrate (12). A single-crystal SiGe layer (24) is formed to overlie the wall surface (20) of the trench (18). A layer of selectively-deposited, single-crystal silicon (26) is formed in the trench (18) using both the bottom surface (22) of the trench (18) and the SiGe layer (24) as a nucleation site for the selective deposition process. After the single-crystal silicon layer (26) is formed, the SiGe layer (24) is selectively removed and the previously occupied space is filled with a dielectric material to form isolation region (30).

Abstract: A process for fabricating an electrically programmable read-only memory array having increased density includes forming recessed field oxide regions in a silicon substrate. Elongated parallel wordline stacks are then formed over the surface of the substrate. Source and drain regions are formed by ion implantation in the openings between these vertical stacks. These openings are then filled with a metal layer until the wafer is substantially planar. This metal layer is then patterned to form drain contact pads and V.sub.SS interconnect strips. The V.sub.SS interconnect strips contact adjacent source regions across field oxide regions that insulate adjacent memory cells.

Abstract: A process for making vertical electrical interconnections in a variety of integrated circuits and novel IC structures produced thereby wherein buried conductors are provided within a dielectric layer located above a silicon substrate having active or passive devices formed therein. Internal edges of only one or selected ones of the conductors are provided with an insulating coating, so that an adjacent via may be filled with a conductive material and still be electrically isolated from the one conductor or conductors. One or more vias are etched directly through the other buried conductor or conductors and also filled with a conductive material which electrically connects this buried conductor or conductors to both the substrate and to an upper level of metallization, and alternatively to intermediate conductors or other components.

Abstract: A method is provided for use with an integrated circuit which includes a npn bipolar transistor on which a variable thickness oxide layer has been formed, the method for improving the radiation hardness of the transistor comprising the steps of: removing the variable thickness oxide layer; and forming a new oxide layer on the transistor, the new oxide layer having less overall volume than the removed variable thickness oxide layer.

Abstract: A reactive ion etching process is used for the fabrication of submicron, single crystal silicon, movable mechanical structures and capacitive actuators. The reactive ion etching process gives excellent control of lateral dimensions while maintaining a large vertical depth in the formation of high aspect-ratio freely suspended single crystal silicon structures. The silicon etch process is independent of crystal orientation and produces controllable vertical profiles.

Abstract: A method for fabricating an isolation region in a semiconductor substrate that produces neither a "bird's beak" nor a "bird's head". A smooth substrate surface is provided, which is preferable for multi-layered wiring. The packing density of devices in a bipolar IC circuit can be increased. A sharp-edged isolation groove having a U-shaped cross-section is made by reactive ion etching. The inner surface of the isolation groove is coated by an insulating film. Then the groove is buried with polycrystalline semiconductor material. The polycrystalline material which is deposited on the surface of the substrate is etched off. At the same time the polycrystalline material in the groove is also etched to a specific depth from the surface. An insulating film is then deposited so as to again fill the groove. Then the substrate surface is polished or etched to provide a flat surface.