Fuse Patents (Class 148/DIG55)
  • Patent number: 5015604
    Abstract: The size of a fusible link (22C.sub.F) created from part of a metal layer (22) is controlled by an oxidation performed in a deposition chamber that is also used for depositing a dielectric layer (30) over the fuse structure. The metal layer serves as a diffusion barrier between semiconductor material (14 and 16) and another metal layer (24).
    Type: Grant
    Filed: August 18, 1989
    Date of Patent: May 14, 1991
    Assignee: North American Philips Corp., Signetics Division
    Inventors: Sheldon C. P. Lim, Julie W. Hellstrom, Ting P. Yen
  • Patent number: 5011791
    Abstract: A fusible link is fabricated using sidewall spacer technology. The fusible link of the present requires low fusing power because a fusible link having a small cross-sectional area is obtainable. A conductive or semiconductive, fusible sidewall spacer is formed around a platform or in a well of a dielectric layer. Each fusible link may have two fusible portions per site, resulting in a built-in redundancy. Alternatively, the packing density of the fusible links may be increased by using each side of the fusible sidewall spacer as a fusible link. This process is compatible with bipolar and BICMOS processes used in fabricating high performance memory devices.
    Type: Grant
    Filed: February 3, 1989
    Date of Patent: April 30, 1991
    Assignee: Motorola, Inc.
    Inventor: Sal T. Mastroianni
  • Patent number: 4931353
    Abstract: In a multi-chip module, a structure for selectively connecting two conductors. A switchable connector (36) is disposed between a first and second portion (30,32) of a copper conductor (28). The switchable connector comprises an amorphous silicon layer (58), which extends between two spacer pads (56) that are electrically connected to the first and second portions of the copper conductor. A barrier layer (60) is formed atop the amorphous silicon, physically separating it from a reactive metal layer (62). The reactive metal layer is coated with an antireflective coating (64). Interaction of the reactive metal layer with the amorphous silicon layer is prevented by the barrier layer until the barrier layer is heated above 500.degree. C. A laser beam (66) is focused on opposite edges of the switchable connector, causing the barrier layer and reactive metal layer to diffuse into the amorphous silicon, forming electrically conductive silicides.
    Type: Grant
    Filed: November 22, 1989
    Date of Patent: June 5, 1990
    Assignee: The Boeing Company
    Inventor: Minas H. Tanielian
  • Patent number: 4849365
    Abstract: A bipolar transistor with a laterally elongated emitter and base so a laser can diffuse dopant from that emitter through that base to the corresponding collector.
    Type: Grant
    Filed: February 16, 1988
    Date of Patent: July 18, 1989
    Assignee: Honeywell Inc.
    Inventor: David R. Gifford
  • Patent number: 4826785
    Abstract: A metallic interconnect includes a fuse portion that is readily vaporized upon exposure to the radiant energy of a laser. A layer of optically absorptive material is formed on top of an aluminum based metallic interconnect and together they are formed by a photolithographic and etch technique into a fuse portion. A low energy laser having a Gaussian energy distribution focused on the absorptive layer produces heat in the absorptive layer. The heat is transferred to the underlying aluminum based interconnect. The concentration of energy made possible by the absorptive layer allows the low energy laser to blow the fuse thereby producing an electrical open in the interconnect without damaging surrounding silicon substrate and/or polysilicon structures below or nearby the metal fuse.
    Type: Grant
    Filed: January 27, 1987
    Date of Patent: May 2, 1989
    Assignee: INMOS Corporation
    Inventors: Paul J. McClure, Robert E. Jones, Jr.
  • Patent number: 4801558
    Abstract: The disclosure relates to a system for protecting HgCdTe and the like MIS arrays from breakdown during fabrication due to electrostatic charge buildup on the array capacitors. This is accomplished by building into the structure a short circuit across the capacitor plates with a fuse region therein that will evaporate when a voltage is placed thereacross which is sufficient to cause evaporation and low enough not to damage the capacitors.
    Type: Grant
    Filed: July 29, 1987
    Date of Patent: January 31, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Arturo Simmons, Shawn T. Walsh, Charles G. Roberts
  • Patent number: 4783424
    Abstract: A semiconductor device comprising a first conductor having first and second portions which are electrically disconnected from each other, and a second conductor, formed on an insulating film separating it from the first conductor, which is electrically conductive. A radiated energy beam renders the second conductor non-conductive, while simultaneously electrically connecting the first and second portions, rendering the first conductor conductive, as needed.
    Type: Grant
    Filed: February 21, 1986
    Date of Patent: November 8, 1988
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Jun-ichi Ohno, Satoshi Konishi
  • Patent number: 4751197
    Abstract: A semiconductor device is programmed by a laser beam which causes an insulator between two conductors on a silicon substrate to be permanently altered, as by breakdown of the insulator. The conductors may be metals such as aluminum or tungsten, and the insulator is a layer of deposited or thermal silicon oxide. The breakdown may be enhanced by voltage applied between the conductors while the laser beam is focused on the structure.
    Type: Grant
    Filed: September 24, 1986
    Date of Patent: June 14, 1988
    Assignee: Texas Instruments Incorporated
    Inventor: Kendall S. Wills
  • Patent number: 4679310
    Abstract: A method of making an improved metal silicide fuse of controlled thickness for an integrated circuit structure is disclosed. The metal silicide fuse is formed by first forming a layer of known thickness of a metal capable of reacting with silicon to form a metal silicide. A layer of amorphous silicon is then formed over the metal and patterned to form the desired fuse dimensions prior to formation of the silicide. The structure is then sintered to form the metal silicide. Excess silicon remaining over the metal silicide fuse layer is then removed as is unreacted metal from areas where no silicon was present to react with the metal to form the silicide. Control of the thickness of the metal layer which subsequently reacts to form the silicide controls the thickness of the subsequently formed silicide layer to thereby form a fuse of reproducible thickness.
    Type: Grant
    Filed: October 31, 1985
    Date of Patent: July 14, 1987
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Govardhan Ramachandra, Kiran M. Bhatt
  • Patent number: 4651409
    Abstract: A fuse programmable ROM includes a wafer for a CMOS-type structure having an emitter, which emitter is overlain by a fuse pad of an undoped polysilicon and a conductive layer. There is a layer of barrier oxide disposed on the conductive top layer of the fuse pad and a sidewall oxide surrounding the periphery of the fuse pad both of which are overlain by the metallic electrical connection.The process of producing the fuse programmable ROM includes wide utilization of standard CMOS fabrication techniques with which are included the steps of depositing fuse material of undoped polysilicon, forming the fuse material into a fuse pad, and then making an electrical connection with the fuse pad.
    Type: Grant
    Filed: September 3, 1985
    Date of Patent: March 24, 1987
    Assignee: NCR Corporation
    Inventors: Daniel L. Ellsworth, Paul A. Sullivan
  • Patent number: 4646427
    Abstract: In a method of electrically altering the characteristics of a semiconductor device, a lateral polysilicon zener diode's zener knee voltage may be shifted either to a higher or lower voltage. An electrical potential may be applied in the forward direction to shift the zener knee to a higher voltage level. An electrical potential may be applied in the reverse bias direction to shift the zener knee to a lower voltage. In the limit, the zener may be changed into a forward diode of reverse polarity with respect to the original zener. The electrical potential used should be of appropriate magnitude to melt the polysilicon without damage to the zener's terminals. This induces migration of the impurities causing a rediffusion of impurities thereby altering the characteristics of the diode. This method may be used to program a PROM by either converting the zener to a diode or not to program each binary bit.
    Type: Grant
    Filed: June 28, 1984
    Date of Patent: March 3, 1987
    Assignee: Motorola, Inc.
    Inventor: James T. Doyle
  • Patent number: 4630355
    Abstract: Circuit assemblies are disclosed which include a supporting substrate, a plurality of conductive lines supported on the substrate and a deposited phase-change material capable of an energy induced phase change from an initially high resistance state to a relatively low resistance state placed in electrical contact with the conductive lines. The assemblies also include contact receiving means connected to the conductive lines at preselected discrete locations to receive externally applied contact means, such as electric probes, for applying voltages across selected portions of the conductive lines. The application of such voltages can induce a phase change in portions of the phase-change material which bridge breaks in the conductive lines of such circuit subassemblies, changing such portions from their high resistance state to their low resistance state, thereby forming electrically shunting conductive paths around such open circuits. There are also disclosed methods of making such circuit assemblies.
    Type: Grant
    Filed: March 8, 1985
    Date of Patent: December 23, 1986
    Assignee: Energy Conversion Devices, Inc.
    Inventor: Robert R. Johnson
  • Patent number: 4628590
    Abstract: This invention discloses a semiconductor device, and method of manufacturing such device, which provides a high degree of moistureproofing, provides a high production yield, and in which defective elements can be replaced by the use of fuses. A circuit test of the device is conducted while at least part of each of a fuse and a bonding pad is exposed through a first passivation film covering a semiconductor substrate on which circuit elements such as MISFETs and capacitors are formed, and any defective elements are replaced by the use of fuses. Contamination of and damage to the elements during the test can thus be prevented. Thereafter, a second passivation film is formed so as to cover all the essential portions of the fuses and bonding pads. The exposure of cracks in the fuses and bonding pads is thus prevented, and the invasion of moisture, etc., into the lower layers below the fuses and bonding pads is also prevented, thereby improving the moistureproofing and reliability of the device.
    Type: Grant
    Filed: September 13, 1984
    Date of Patent: December 16, 1986
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering, Ltd.
    Inventors: Shinji Udo, Masanori Tazunoki
  • Patent number: 4602420
    Abstract: A method of manufacturing a semiconductor device including the steps of forming a passivation film, which has an opening exposing that region of the interlayer insulation film formed on the fuse element, which corresponds to the region to be melted of fuse element, melting the region of the fuse element to be melted by radiating a laser beam on the exposed region of the interlayer insulation film through the opening, and the step of forming a protective resin layer on the whole main surface of the resultant structure after melting is completed.
    Type: Grant
    Filed: December 13, 1984
    Date of Patent: July 29, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shozo Saito
  • Patent number: 4598462
    Abstract: A semiconductor device and method for making same having dielectrically isolated individual elements such as transistors, diodes, et al. Some of the isolated elements having fuses formed integral thereto.
    Type: Grant
    Filed: March 22, 1985
    Date of Patent: July 8, 1986
    Assignee: RCA Corporation
    Inventor: Hosekere S. Chandrasekhar
  • Patent number: 4569121
    Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor impurity is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction laterally bounded by the island's side boundaries. A highly resistive amorphous semiconductive layer (58) which is irreversibly switchable to a low resistive state is deposited above the region in such a manner as to be electrically coupled to the region. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.
    Type: Grant
    Filed: March 7, 1983
    Date of Patent: February 11, 1986
    Assignee: Signetics Corporation
    Inventors: Sheldon C. P. Lim, Douglas F. Ridley, Saiyed A. Raza, George W. Conner
  • Patent number: 4569120
    Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction with adjacent semiconductive material of the island. Ions are implanted to convert a surface layer (60) of the region into a highly resistive amorphous form which is irreversibly switchable to a low resistance state. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.
    Type: Grant
    Filed: March 7, 1983
    Date of Patent: February 11, 1986
    Assignee: Signetics Corporation
    Inventors: William T. Stacy, Sheldon C. P. Lim, Kevin G. Jew
  • Patent number: 4536948
    Abstract: A blowable fuse is provided over a part of its length separately from the walls of an enveloping cavity and separated from a supporting member. As a result of this the fuse is readily thermally isolated so that it fuses more rapidly and with less energy. In addition, a semiconductor circuit element, for example a Schottky diode, can be realized below a bridging part of a conductor which serves as an upper wall of the cavity, which results in a high bit density.
    Type: Grant
    Filed: April 23, 1984
    Date of Patent: August 27, 1985
    Assignee: U.S. Philips Corporation
    Inventors: Ties S. Te Velde, Arie Slob