Abstract: The present invention relates to the formation of multiple gettering structures within a semiconductive substrate by ion implantation through recesses in the semiconductive substrate. A preferred embodiment of the present invention includes forming the recesses by using a reactive anisotropic etching medium, followed by implanting a gettering material. The gettering material is implanted by changing the gettering material for the reactive anisotropic etching medium. An advantage of the method of the present invention is that gettering structures are formed without the cost of an extra masking procedure and without the expense of MeV implantation equipment and procedures. As a result, metallic contaminants will not move as freely through the semiconductive substrate in the region of an active area proximal to the gettering structures.

Abstract: Reduction in the net charge at the interface of a dielectric and a semiconductor material is achieved by placing atomic species in the dielectric near the interface. Preferably, these species are selected from the group of alkaline earth metals. The presence of these atoms results in a redistribution of the electronic density near the interface. The placement of the atoms is effected by ion implantation followed by multiple annealing steps at alternating low and high temperatures.

Abstract: In one aspect, the invention pertains to a method of forming a gettering region within an Si semiconductor wafer, the method including: a) providing a semiconductor material wafer; b) providing a background region within the semiconductor material wafer, the background region being doped with a first-type conductivity enhancing dopant, the first-type conductivity enhancing dopant being either n-type or p-type; c) implanting a second-type conductivity enhancing dopant into the background region to form a second-type implant region entirely contained within the background region, the second-type conductivity enhancing dopant being of an opposite type than the first-type conductivity enhancing dopant of the background region; and d) implanting a neutral-conductivity-type conductivity enhancing dopant into the second-type implant region to form a metals gettering damage region entirely contained within the second-type implant region. The invention also pertains to gettering region structures.

Abstract: In a silicon wafer having a CVD film formed on one main face and having the other main face mirror-polished, the components and/or composition of the CVD film change in the thicknesswise direction of the film. This makes it possible to provide a silicon wafer having a thin film provided on the back surface, which thin film has excellent and persistent gettering capability that can remove a greater variety of types of elements and can prevent autodoping.

Abstract: Dopant atoms have coefficients of diffusion that vary due to implant damage. Damaged regions are selected and created by implanting silicon atoms into a silicon substrate prior to formation of a gate electrode. The silicon atoms act as a getter for attracting selected dopants that are trapped in the silicon substrate. Dopants are implanted in the vicinity of the damaged regions and diffused by transient-enhanced diffusion (TED) into the damaged regions by thermal cycling to accumulate dopant atoms. Transient-enhanced diffusion improves the doping of a substrate by enhancing the diffusion of dopants at relatively low anneal temperatures. Dopant accumulation sets particular selected electrical properties without placing an excessive amount of dopant in regions adjacent to junctions for purposes including threshold control for a field device, threshold setting for a transistor, and prevention of device punchthrough.

Abstract: A semiconductor device in accordance with the present invention, for example, is a thin film transistor provided on a transparent substrate. The semiconductor device made of a polysilicon film is provided with (1) a semiconductor layer having a source region and a drain region and (2) a gate electrode provided on a region between the source region and the drain region of the semiconductor layer via a gate insulating film. The semiconductor device is further provided with an organic insulating film made of a condensation polymer having an imide ring such that the organic insulating film covers the gate electrode, the source region, and the drain region.

Abstract: A silicon semiconductor substrate including a silicon semiconductor layer at one of upper and lower surfaces thereof, the silicon semiconductor layer being composed of polysilicon or noncrystal silicon and containing oxygen in the range of 2 atomic % to 20 atomic % both inclusive, nitrogen in the range of 4 atomic % to 20 atomic % both inclusive, or both nitrogen at 2 atomic % or greater and oxygen at 1 atomic % or greater. The polysilicon or noncrystal silicon semiconductor layer acts as a core for extrinsic gettering. In the silicon semiconductor substrate, the gettering performance is not deteriorated, even if the silicon semiconductor substrate experiences thermal treatment. Thus, it is possible to get rid of contamination caused by heavy metals in the silicon semiconductor substrate.

Abstract: A process for the preparation of silicon wafers having a non-uniform distribution of oxygen precipitate nucleation centers. Silicon wafers having a controlled distribution of oxygen precipitate nucleation centers are prepared by heating the wafer in a manner to create a temperature gradient across the thickness of the wafer for a period of time. Upon a subsequent oxygen precipitation heat treatment, those regions of the wafer which were rapidly heated to a temperature in excess of about 900.degree. C. will form a denuded zone whereas those regions of the wafer which did not achieve a temperature in excess of about 900.degree. C. during the rapid heating will form oxygen precipitates.

Abstract: A process for reducing halogen concentration in a material layer (56) includes the deposition of a dielectric layer (58) overlying the material layer (56). An annealing process is carried out to diffuse halogen atoms from the material layer (56) into the overlying dielectric layer (58). Once the diffusion process is complete, the dielectric layer (58) is removed.

Abstract: In one aspect, the invention pertains to a method of forming a gettering region within an Si semiconductor wafer, the method including: a) providing a semiconductor material wafer; b) providing a background region within the semiconductor material wafer, the background region being doped with a first-type conductivity enhancing dopant, the first-type conductivity enhancing dopant being either n-type or p-type; c) implanting a second-type conductivity enhancing dopant into the background region to form a second-type implant region entirely contained within the background region, the second-type conductivity enhancing dopant being of an opposite type than the first-type conductivity enhancing dopant of the background region; and d) implanting a neutral-conductivity-type conductivity enhancing dopant into the second-type implant region to form a metals gettering damage region entirely contained within the second-type implant region. The invention also pertains to gettering region structures.

Abstract: Provided is a process for producing a semiconductor silicon wafer by which an intrinsic gettering effect can be improved and at the same time the top side can be made free from faults. A silicon ingot is produced and sliced to obtain silicon wafers. Then, a polycrystal silicon depositing film is formed on one side of a silicon wafer, which is subjected to a heat treatment in an inert gas, a reducing gas or a mixture thereof to discharge oxygen from the vicinity of the other side. Alternatively, after discharging oxygen from the silicon wafer by a heat treatment, a polycrystal silicon depositing film may be formed on one side of the silicon wafer.

Abstract: Method of fabricating a semiconductor device, such as a thin-film transistor, having improved characteristics and improved reliability. The method is initiated with formation of a thin amorphous silicon film on a substrate. A metallization layer containing at least one of nickel, iron, cobalt, and platinum is selectively formed on or under the amorphous silicon film so as to be in intimate contact with the silicon film, or these metal elements are added to the amorphous silicon film. The amorphous silicon film is thermally annealed to crystallize it. The surface of the obtained crystalline silicon film is etched to a depth of 20 to 200 .ANG., thus producing a clean surface. An insulating film is formed on the clean surface by CVD or physical vapor deposition. Gate electrodes are formed on the insulating film.

Abstract: The evaluation of the oxide film dielectric breakdown voltage of a silicon semiconductor single crystal is caried out by cutting a wafer out of the single crystal rod, etching the surface of the wafer with the mixed solution of hydrofluoric acid and nitric acid thereby relieving the wafer of strain, then etching the surface of the wafer with the mixed solution of K.sub.2 Cr.sub.2 O.sub.7, hydrofluoric acid, and water thereby inducing occurrence of pits and scale-like patterns on the surface, determining the density of the scale-like patterns, and computing the oxide film dielectric breakdown voltage by making use of the correlating between the density of scale-like patterns and the oxide film dielectric breakdown voltage. This fact established the method of this invention to be capable of effecting an evaluation equivalent to the evaluation of the oxide film dielectric breakdown voltage of a PW wafer prepared from the single crystal rod.

Abstract: After a pattern is transferred on silicon film crystallized by annealing, the silicon film is annealed by radiation of intense rays for a short time. Especially, in the crystallizing process by annealing, an element which promotes crystallization such as nickel is doped therein. The area not crystallized by annealing is also crystallized by radiation of intense rays and a condensed silicon film is formed. After a metal element which promotes crystallization is doped, annealing by light for a short time is performed by radiating intense rays onto the silicon film crystallized by annealing in an atmosphere containing halide. After the surface of the silicon film is oxidized by heating or by radiating intense rays in a halogenated atmosphere and an oxide film is formed on the silicon film, the oxide film is then etched. As a result, nickel in the silicon film is removed.

Abstract: A method is provided for pre-process denudation and process-induced gettering of a CZ silicon wafer having one or more monolithic devices embodied therein. Pre-process denudation is performed in a hydrogen ambient to out-diffuse oxygen as well as to maintain interstitial silicon flux away from the substrate surface. Process-induced gettering is performed at a low temperature to ensure stacking faults and surface irregularities do not arise from interstitial silicon bonding at the surface prior to gate oxidation. The third step of the denudation/gettering cycle involving precipitate growth is thereby delayed or forestalled until the field oxide is grown. Any changes or movement in oxygen and/or interstitial silicon within or near the substrate surface occurring after polysilicon deposition will have minimal effect upon the established gate oxide. Accordingly, gate oxide integrity (e.g., breakdown voltage and uniformity) are enhanced by the present process.

Abstract: In a semiconductor device and a method of manufacturing the same according to the present invention, after As and C are introduced to a semiconductor substrate, a semiconductor layer is formed on the semiconductor substrate. When first and second semiconductor layers are to be sequentially formed on a semiconductor substrate, an impurity concentration of As or Sb serving as an impurity of the first semiconductor layer is 10 times or more an impurity concentration of the second semiconductor layer, and the second semiconductor layer has a thickness of 4 to 10 .mu.m.

Abstract: A method of manufacturing a semiconductor substrate in which a damage layer is formed on one surface of a wafer. An etching protection film is formed on the damage layer. An epitaxial layer is formed on the other surface of the wafer. Thereafter, the etching protection film is removed to expose the damage layer. The exposed damage layer enhances gettering ability.

Abstract: A method of manufacturing a semiconductor device, which comprises the steps of providing a semiconductor substrate having a first primary surface which is designated to form the semiconductor device and a second primary surface opposite from the first primary surface, the substrate containing contaminants therein; forming a boron-doped layer on the second primary surface of the substrate; and absorbing the contaminants into the boron-doped layer.

Abstract: A semiconductor substrate is denuded using a reducing gas mixture including carbon monoxide and carbon dioxide. Use of the reducing gas mixture allows very low oxygen partial pressure to be achieved in a furnace tube during the step of denuding. Oxygen partial pressure lower than 1E-9 atmosphere may be achieved by adjusting the relative ratio of carbon monoxide and carbon dioxide. Precipitates are grown after forming nucleating sites. Both CZ and FZ substrates may use the process, and the process can be used with silicon, germanium, or other semiconductor materials.

Abstract: A semiconductor device is produced by a process for intrinsic gettering heat treatment of a silicon crystal in which the concentration of C--O complex defects destined to form seeds for oxygen precipitation in the silicon crystal is increased or an amount of oxygen precipitate in the silicon crystal is controlled, to thereby eliminate the dispersion of the amount from one crystal to another. In the heat treatment of the silicon crystal, the amount of oxygen precipitation can be controlled with a high accuracy.

Abstract: A frontside gettering method for removing metallic contamination from a thin film SOI or SOS silicon device. Damage sites are created by ion implantation into inactive regions of a silicon substrate. An annealing step causes metallic contamination to diffuse from the active device region to the inactive region. The inactive region material is removed prior to subsequent processing steps.

Abstract: A mobile ion getterer is added to metalization layers on an integrated circuit or discrete device to reduce mobile ion contamination therein. Preferably, chromium is used as the mobile ion getterer and is added to an aluminum target used as the metal source for sputtering the chromium and aluminum onto the integrated circuit or discrete device. This technique removes the need for ultrahigh purity aluminum conductors or gettering material (P-glass) in contact with the metal conductors. This technique may be used with virtually all metalization apparatus and processes used for depositing metal onto semiconductor devices.

Abstract: A gettering treatment process comprises the step of irradiating an ultraviolet light onto an insulating layer (a silicon oxide thin layer formed by thermally oxidizing silicon), in a chlorine-containing gas atmosphere. The ultraviolet light excites and dissociates the chlorine-containing gas thereby to generate chlorine radicals which uniformly penetrate the insulating layer, and serve to trap metal impurities within the silicon oxide thin layer.

Abstract: A substrate has a semiconductor-on-insulator structure. The substrate has a base substrate, an insulator layer provided on the base substrate, an active substrate provided on the insulator layer and having gettering sites, and an active layer provided on the active substrate and made of a semiconductor. The gettering sites under the active layer eliminate crystal defects and impurities generated in the active layer during the semiconductor device production in which elements are formed in the active layer.

Abstract: A gettering site is formed on the backside of a wafer, contaminant impurities are trapped in the gettering site by heat treatment, a contaminated layer of the gettering site including the impurities is removed. The impurities are thus prevented from being freed from the gettering site into the wafer. A new gettering site is then formed on the backside of the wafer. Such a gettering operation has therefore a refresh function.

Abstract: A method of gettering unintentional mobile impurities starts with production of an damaged portion on the reverse side of a silicon wafer, and the silicon wafer is placed in a high temperature vacuum ambience so that the unintentional mobile impurities are firstly trapped by the damaged portion and, then, evacuated to the high temperature vacuum ambience.

Abstract: In a method for heat process of silicon, a single crystal silicon produced by the Czochralski process is thermally processed at a low temperature ranging from 400.degree. C. to 550.degree. C. Outside this temperature range, the oxygen precipitate is not adequate. The result is that a predetermined oxygen precipitate can be obtained uniformly in the crystal growth direction without any reduction especially at the crystal bottom part. The resulting silicon is particularly suitable for manufacture of LSI.

Abstract: The switching speed of bipolar power rectifiers is increased by formation of misfit dislocations in the depletion region, spaced from the substrate/epitaxial layer interface, in order to reduce minority carrier lifetime. The misfit dislocations are formed by the introduction of germanium during epitaxy, and are distributed along the silicon/silicon-germanium interface. Preferably, the germanium containing layer is located proximate the center of the depletion region.

Abstract: Disclosed is a method of producing a semiconductor wafer through gettering by means of sand blasting in a semiconductor wafer fabrication process. The method includes blasting abrasives each having a configuration at least similar to a sphere against a back surface of the semiconductor wafer, causing shear stress having a maximum point in the interior of the wafer to be generated, whereby damage is produced mainly in the interior of the wafer.

Abstract: A method of fabricating a semiconductor heterostructure includes the growth of a quantum well active region that is highly lattice-mismatched relative to a substrate. A buffer layer having a thickness above a critical value is grown on the substrate whereby the stress due to a lattice constant mismatch between the buffer layer and substrate is relieved through the formation of misfit dislocations. A strained superlattice structure is grown on the buffer layer in order to terminate any upwardly-propagating dislocations. An unstrained barrier layer is subsequently grown on the superlattice structure. The fabrication method concludes with the growth of a quantum well structure on the unstrained layer wherein a lattice constant mismatch between the quantum well structure and the unstrained barrier layer is smaller than the lattice constant mismatch between the quantum well structure and the substrate.

Abstract: A method of backside damaging a silicon semiconductor wafer by abrading the wafer in an abrasive powder is disclosed. The wafer is rotated or translated in the powder while the powder is being vibrated. A fixture holds one or more semiconductor wafers during the processing and allows the wafer to be rotated during processing if desired.

Abstract: A complementary bipolar transistor structure having one symmetrical intrinsic region for both the NPN and PNP transistors and a method for fabricating the structure. The transistor structure includes a vertical NPN transistor operating in the upward direction and a vertical PNP transistor operating in a downward direction. In the method, the sub-emitter and the sub-collector regions are formed by depositing a first epitaxial layer of semiconductor material of a first conductivity type on the surface of a semiconductor substrate of a second conductivity type, and forming the sub-collector by etchig a shallow trench in the first layer and depositing semiconductor material of a second conductivity tyep by LTE and planarizing.

Abstract: A method of gettering heavy metal impurities from p-type silicon substrates comprises the prior step of forming an intrinsic gettering layer covered with a surface denuded zone in the silicon substrate by subjecting the substrate to heat treatments which form the intrinsic gettering layer having a large density of crystal microdefects compared to the density of crystal microdefects in the denuded zone; then the step of performing most of the required wafer processes other than the step of forming a metal layer; and subsequently the gettering step of heating the silicon substrate to a predetermined temperature and simultaneously irradiating the substrate with light rays, the predetermined temperature being selected to be within the temperature range 150.degree. C. to 220.degree. C., preferably around 200.degree. C.

Abstract: A method of heat treatment for purifying a Groups II-VI compound semiconductor and for producing a purity Groups II-VI compound semiconductor crystal using a sealed container placed a Groups II-VI compound semiconductor crystal as a raw material is disclosed. The process includes heating means applied to the sealed container having a temperature difference which has a high-temperature zone and a low-temperature zone into the sealed container, placing the raw material into the high-temperature zone of the sealed container, using a heat atom making an atmosphere of either a Group II element or a Group VI element, or a mixed atmosphere of either which is necessary to treat the Groups II-VI compound semiconductor into the sealed container, and using a Groups II-VI compound semiconductor as raw material.

Abstract: A semiconductor substrate including a top epitaxial compound layer comprising: a single-crystalline semiconductor wafer substrate; a strained layer superlattice (SLS) structure layer having a lattice constant varying from that of the wafer substrate to that of the top compound semiconductor layer and formed on the wafer substrate; a semiconductor buffer layer having the same lattice constant as that of the top compound semiconductor layer and formed on the SLS structure layer; another SLS structure layer for filtering dislocations having a fixed lattice constant equal to that of the top semiconductor layer and formed on the buffer layer; and the top semiconductor layer formed on the another SLS structure layer.

Abstract: A post dry etching process for restoring wafers damaged by dry etching such as RIE, comprising the steps of removing any dry etch residue layer from the etched portions of the wafer and forming an oxide on those etched portions; rapid thermal annealing the wafer to drive the oxygen from the oxide layer down into the wafer by a small amount, to getter impurities to this oxide layer, and to restore crystallinity below the oxide layer; and removing the oxide layer via an HF bath or a low powder dry etch process.

Abstract: A semiconductor substrate and process for making are disclosed. The substrate is suitable for use in manufacturing large scale integrated circuits. The process comprises the steps of heating a semiconductor substrate at a temperature not lower than 1100.degree. C., implanting electrically inert impurities into the major surface of the substrate, heating the substrate at a temperature ranging from 600.degree. to 900.degree. C. and providing a single crystal semiconductor layer.

Abstract: The concentration of internal gettering sites within a semiconductor wafer is controlled by two-step thermal processing. In a concentration reduction phase, the wafer is rapidly heated to an elevated temperature in the range from about 900.degree. to 1350.degree. C., resulting in the partial or total dissolution of precipitable impurities within the wafer. In a concentration enhancement step, the wafers are subjected to a relatively low temperature anneal process where the density of potential internal gettering sites is increased. By properly controlling the processing temperatures and treatment times, the two steps may be performed in either order to obtain wafers having internal gettering site concentrations within a desired range.

Abstract: A method of manufacturing a semiconductor device includes the steps of (a) forming a first conductive pattern on a semiconductor substrate, (b) forming a first interlayer insulating film, covering the first conductive pattern, (c) forming a second conductive pattern, composed of a refractory metal, on the first interlayer insulating film, (d) forming a contact hole reaching the first conductive pattern through the second conductive pattern and the first interlayer insulating film at a predetermined position, (e) performing an annealing step before or after formation of the contact hole in step (d), and (f) covering in the contact hole with a metal film, after annealing step (e), to connect the second conductive pattern to the first conductive pattern. In this method, annealing step--for example, gettering--is performed before the wiring layer of the refractory metal is placed in contact with the semiconductor layer.

Abstract: The concentration of internal gettering sites within a semiconductor wafer is controlled by two-step thermal processing. In a concentration reduction phase, the wafer is rapidly heated to an elevated temperature in the range from about 900.degree. to 1350.degree. C., resulting in the partial or total dissolution of precipitable impurities within the wafer. In a concentration enhancement step, the wafers are subjected to a relatively low temperature anneal process where the density of potential internal gettering sites is increased. By properly controlling the processing temperatures and treatment times, the two steps may be performed in either order to obtain wafers having internal gettering site concentrations within a desired range.

Abstract: A photoconductive layer of an electrophotographic photoreceptor has a super lattice structure obtained by alternately stacking thin layers (the thickness falls within the range of 30 to 200 .ANG.) of at least two types of amorphous semiconductors having different optical band gaps. In the super lattice structure, when the layer having a narrow bandgap is sandwiched between the layers having wide bandgaps, a quantum well is formed. By the quantum effect, electrons in the well are shifted to cause high mobility of carriers. When the super lattice structure is applied to the photoconductive layer of the electrophotographic photoreceptor, the number of carriers generated at the interface between the thin layers is large.

Abstract: Sealing the backside of a semiconductor wafer prevents evaporation of the dopant (typically boron) when an epitaxial layer is grown on the front (active) side, thereby preventing autodoping of the epitaxial layer with excess dopant. The present technique deposits an oxide layer during the ramp-up of the furnace that also deposits the nitride cap, thereby avoiding an extra process step. It also avoids the higher temperatures required for the prior-art technique of growing the oxide layer, resulting in lower oxygen precipitation due to the capping process and a greater yield of usable wafers.

Abstract: A photovoltaic solar cell comprises a piece of semiconductor material incorporating a p-type region, an n-type region, a p-n junction between the two, electrodes contacting the two regions, and within its body a lattice defect denuded zone and a lattice defect gettering zone.The defect gettering zone may be a precipitate-rich zone or a region of lattice damage. The denuded zone may include the p-n junction.The semiconductor material may be Si, GaAs or InP.Methods for making the solar cell are described, involving heat treatment steps to produce a denuded zone, nucleating precipitates and generating precipitates. Alternatively precipitation may be nucleated, or a lattice damage zone may be generated, by proton bombardment.

Abstract: A dopant gettering semiconductor processing technique is disclosed for selectively activating an otherwise benign reactant to remove dopant from a semiconductor wafer substrate. Excimer pulsed ultraviolet laser radiation is provided at a discrete designated pulsed wavelength corresponding to a discrete designated gettering excitation energy of the otherwise benign reactant photochemically breaking bonds of the reactant such that the reactant is photolytically activated to remove dopant from the substrate, without thermally driven pyrolytic reaction. The bonds of a reactant gas are photochemically broken to produce gettering agents reacting with the substrate to remove dopant by forming a gaseous compound liberated from the substrate and benign to and unactivated by the discrete designated wavelength of the excimer pulsed ultraviolet laser radiation.

Abstract: Semiconductor substrate materials, such as silicon, useful in the manufacture of electronic devices, such as integrated circuits, having a 0.05 to 2.0 micron thick layer of polysilicon on the backside to improve gettering capabilities of defects, contaminants and impurities away from the active device region of the substrate are provided with a 10 to 40 micron deep region from the surface having reduced oxygen concentration. The oxygen denuding is accomplished by heating the substrate material at a temperature of 1050.degree. to 1250.degree. C. first in the presence of oxygen to break up oxygen nuclei, secondly in the presence of oxygen and halogen to permit stacking fault retrogrowth and oxygen outdiffusion, and thirdly in the presence of oxygen, nitrogen and/or argon.

Abstract: The inventive method of manufacturing a semiconductor device is carried out by slicing a silicon single crystal grown by a Czochralski method, thereby to provide a wafer (1), annealing the wafer (1) at a temperature range of 600.degree. C. to 800.degree. C. in an atmosphere including an inert gas and a small amount of oxygen for approximately 2 to 6 hours, thereby to precipitate oxygen (2) in the whole wafer (1), and then annealing the wafer (1) in the temperature range of 1000.degree. C. to 1100.degree. C. in a water vapor atmosphere including chlorine, thereby to form an oxide film (3) on the surface of the wafer (1), whereby a denuded zone (4) is formed beneath the oxide film (3) while crystal defects (5a-5d, 6) serving as a getter of impurities such as metals are formed beneath the denuded zone.

Abstract: Disclosed is a silicon semiconductor substrate for a semiconductor integrated circuit such as LSI or VLSI. The silicon semiconductor substrate has an oxygen concentration ranging from 3.times.10.sup.17 cm.sup.-3 to 7.times.10.sup.17 cm.sup.-3 and a gettering layer on its backside. This gettering layer may comprise a nonsingle crystalline silicon layer such as polycrystalline silicon layer or amorphous silicon layer, or a layer having stacking fault density of more than 3.times.10.sup.4 cm.sup.-2.

Abstract: Disclosed is a method of stabilizing and standardizing semiconductor wafers obtained from a plurality of vendor sources for use in both unipolar and bipolar device manufacturing lines. Based on measured initial oxygen concentration, the as-received wafers are grouped into lots. Next, based on measured oxygen precipitation rate of each lot, the wafer lots are grouped into classes, regardless of their vendor origin. Typically, the grouping consists of three classes corresponding to low, intermediate and high oxgen precipitation rate.The wafers of each class are then subjected to a thermal adaptation cycle tailored to the class to generate in each wafer clusters of a concentration corresponding to a predetermined cluster concentration range and a defect-free zone corresponding to a predetermined defect-free zone range. The thermal adaptation cycle is different from class to class, but identical for wafers of a given class.

Abstract: N+ type semiconductor substrates containing oxygen are thermally treated to enhance internal gettering capabilities by heating at 1050.degree. to 1200.degree. C., then at 500.degree. to 900.degree. C. and finally at 950.degree. to 1250.degree. C.

Abstract: Semiconductor substrate materials, such as silicon, useful in the manufacture of electronic devices, such as integrated circuits, employing low temperature, i.e., below 1025.degree. C. processing cycles are provided with a 0.05 to 2.0 micron thick layer of polysilicon on the backside to improve gettering capabilities of defects, contaminants and impurities away from the active device region of the substrate.