Abstract: This is a method of fabricating a heterojunction bipolar transistor on a wafer. The method can comprise: forming a doped subcollector layer 31 on a semiconducting substrate 30; forming a doped collector layer 32 on top of the collector layer, the collector layer doped same conductivity type as the subcollector layer; forming a doped base epilayer 34 on top of the collector layer, the base epilayer doped conductivity type opposite of the collector layer; forming a doped emitter epilayer 36, the emitter epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming a doped emitter cap layer 37 on top of the emitter epilayer, the emitter cap layer doped same conductivity as the emitter epilayer; forming an emitter contact 38 on top of the emitter cap layer; forming a base contact on top of the base layer; forming a collector contact on top of the collector layer; and selective etching the collector layer to produce an undercut 45 beneath the base layer.

Abstract: A method of making a transistor comprising the steps of providing a structure having a collector layer 3, a base layer 5, and an emitter layer 7, one atop the other, forming a contact 9 on the emitter layer, removing a portion of the emitter layer to leave a relatively thick mesa region 13 with the contact thereon, a surrounding relatively thin ledge region 11 and an exposed portion of the base layer 5 and forming a contact on the exposed portion of the base layer 5. The emitter layer 7 is preferably GaInP, and preferably Ga.sub.x In.sub.1-x P, wherein x is in the range of approximately 0.50 to 0.52, and the base 5 is preferably GaAs. The ledge portion 11 has a thickness of about 700 Angstroms.

Abstract: On a semi-insulating substrate, an emitter layer (or a collector layer), a base layer, a compound semiconductor layer containing In and a collector layer (or an emitter layer) are provided. The collector layer (or the emitter layer) is patterned to form a collector region (or an emitter region). When the base surface is revealed by a reactive ion beam etching, the etching will be stopped at the compound semiconductor layer that contains In. Consequently, the nonuniformity in the base resistance that depends on the thickness of the base lead-out region can be reduced.

Abstract: A semiconductor device comprises a substrate having a stepped upper major surface, an emitter layer of a semiconductor material provided on the stepped upper major surface of the substrate and having a corresponding stepped upper major surface, a base layer provided on stepped upper major surface of the emitter layer and comprising a plurality of channels of carriers and a plurality of control regions for controlling the passage of carriers through the control regions, and a collector layer of a semiconductor material provided on the base layer for collecting the carriers that have passed through the channels. Each channel extends from the emitter layer to the collector layer, and at least one channel and one control region are provided adjacent with each other in correspondence to each step of the upper major surface of the emitter layer.

Abstract: A high electron mobility transistor is disclosed, which takes advantage of the increased mobility due to a two dimensional electron gas occurring in GaN/Al.sub.x Ga.sub.1-x N heterojunctions. These structures are deposited on basal plane sapphire using low pressure metalorganic chemical vapor deposition. The electron mobility of the heterojunction is approximately 620 cm.sup.2 per volt second at room temperature as compared to 56 cm.sup.2 per volt second for bulk GaN of the same thickness deposited under identical conditions. The mobility of the bulk sample peaked at 62 cm.sup.2 per volt second at 180.degree. K. and decreased to 19 cm.sup.2 per volt second at 77.degree. K. The mobility for the heterostructure, however, increased to a value of 1,600 cm.sup.2 per volt second at 77.degree. K. and saturated at 4.degree. K.

Abstract: Complementary heterostructure field effect transistors (30) with complementary devices having complementary gates (40, 50) and threshold adjusting dopings are disclosed. Preferred embodiment devices include a p.sup.+ gate (50) formed by diffusion of dopants to convert n.sup.+ gate material to p.sup.+, and a pulse-doped layer adjacent the two-dimensional carrier gas channels to adjust threshold voltages. Further preferred embodiments have the conductivity-type converted gate (50) containing a residual layer of unconverted n.sup.+ which cooperates with the pulse-doped layer threshold shifting to yield threshold voltages which are small and positive for n-channel and small and negative for p-channel devices.

Abstract: A method of manufacturing heterojunction transistors having self-aligned contacts. In manufacturing a heterojunction bipolar transistor, a collector and a base layer are deposited on a substrate. A masking layer is deposited on the base layer and selectively etched to form an aperture therein, exposing the base layer. An emitter having a mesa structure is grown epitaxially on the exposed base layer to produce lateral overhang portions. The overhang portions may be formed by continuing the epitaxial growth to form lateral overgrowth portions overlapping the masking material. The masking layer is removed and self-aligned contacts are formed to the base and emitter regions using the lateral overhang portions which provide separation between the emitter structure and the contacts to the base layer.

Abstract: A heterojunction between In-containing compound semiconductors in which the interface thereof is controlled at an atom level is provided by a process of atomic layer epitaxy (ALE) in which hydrogen gas is utilized as a carrier gas and as a purge gas for a separation of source gases. The time for which the purge gas is supplied can be utilized for controlling the ALE.

Abstract: An image reversal process for self-aligned implants in which a mask opening and plug in the opening are used to enable one implant in the mask opening, another self-aligned implant in the region surrounding the opening, and a self-aligned electrode to be formed in the opening.

Abstract: A method of manufacturing a heterojunction bipolar transistor is disclosed. On a base layer of a first semiconductor which contains at least one of gallium and arsenic as a constituent element, an emitter layer of a second semiconductor is formed which contains as a constituent element at least one of gallium and arsenic and which has a band gap larger that of the first semiconductor. Predetermined regions of the emitter layer and an upper portion of the base layer are removed to form a mesa structure. Then, a surface of a junction region of the base layer and the emitter layer of the formed mesa structure is treated using a phosphate etchant and a sulfur or sulfide passivating agent. After the surface treatment, the surface of the junction is covered with an insulating film.

Abstract: Disclosed is a method for fabricating complementary heterojunction bipolar transistors on a common substrate. The method comprises the steps of depositing a PNP profile by molecular beam epitaxy on an appropriate substrate and then depositing a layer of silicon nitride on the PNP profile just deposited. The substrate is then heated in a vacuum in order to densify the silicon nitride. A mask and resist layer are used to produce the desired PNP profile patterns. The NPN profile is deposited on the area of the substrate etched away as well as on the silicon nitride layer protecting the already deposited PNP layers. The NPN profile is then patterned using a resist and masking process. The polycrystalline NPN area on top of the silicon nitride layer and the remaining silicon nitride layer are etched away forming two adjacent complementary NPN and PNP profiles on a common substrate.

Abstract: Generally, and in one form of the invention, an integrated circuit is disclosed for providing low-noise and high-power microwave operation comprising: an epitaxial material structure comprising a substrate 10, a low-noise channel layer 14, a low-noise buffer layer 16, a power channel layer 18, and a moderately doped wide bandgap layer 20; a first active region 24 comprising a first source contact 32 above the wide bandgap layer 22, a first drain contact 36 above the wide bandgap layer 22, wherein the first source contact 32 and the first drain contact 36 are alloyed and thereby driven into the material structure to make contact with the low-noise channel layer 14, and a first gate contact 28 to the low-noise buffer layer 16; and a second active region 26 comprising a second source contact 34 above the wide bandgap layer 22, a second drain contact 38 above the wide bandgap layer 22, wherein the second source contact 34 and the second drain contact 38 are alloyed and thereby driven into the material structure t

Abstract: A pre-processed substrate structure for a semiconductor device. A subcollector layer is spaced apart from a substrate by a dielectric. A relatively small, lightly-doped epitaxial feed-through layer extends through the dielectric between the substrate and the subcollector. A transistor constructed over the subcollector has very low collector-to-substrate capacitance. A plurality of devices on a common substrate are electrically isolated from each other by channel stops formed in the substrate around each device.

Abstract: There is provided a method of fabricating a semiconductor device. This method includes the steps of: forming a collector layer, a base layer, an emitter layer, and a dummy layer; patterning the dummy layer and the emitter layer into a mesa structure; forming a base electrode on the base layer in self-alignment to the mesa structure, and simultaneously forming a base electrode material on the dummy layer; forming a surface planarization film on the base layer to cover sides of the mesa structure; and removing the base electrode material and the dummy layer. The removal of the dummy layer is performed by subjecting the dummy layer to an etchant through an opening in the base electrode material.

Abstract: A method for making a heterojunction bipolar transistor in which the collector (46) is epitaxially grown on the subcollector layer (36) through a hole (42) formed in a layer of insulating material (40) deposited on the subcollector layer (36). A base (48) is epitaxially grown on the collector (46). Because of unequal lateral and vertical growth rates, the peripheral region of the base extends over the layer of insulating material. The n and n.sup.+ layers (50, 52) of the second type of semiconducting material are sequentially grown on the base and an n.sup.+ layer (54) of the first type of semiconducting material is grown on the sequentially grown layers (50, 52). The n.sup.+ layer (54) and the sequentially grown layer (50, 52) are etched to form an emitter mesa over the collector (46) leaving exposed the peripheral portion of the base (48) extending over the layer of insulating material surrounding the hole (42).

Abstract: Integrated circuits and fabrication methods incorporating both NPN (192, 194, 210) and PNP (196, 121, 124) heterojunction bipolar transistors together with N channel (198, 200, 216, 218) and P channel (202, 204, 220, 222) JFETs on a single substrate as illustrated in FIG. 10. MESFETs may be also be integrated on the substrate.

Abstract: Heterostructures having a large lattice mismatch between an upper epilayer and a substrate and a method of forming such structures having a thin intermediate layer are disclosed. The strain due to a lattice mismatch between the intermediate layer and the substrate is partially relieved by the formation of edge type dislocations which are localized and photoelectrically inactive. Growth of the intermediate layer is interrupted before it reaches the thickness at which the left over strain is relieved by 60 degree type threading dislocations. The upper epilayer is then grown in an unstrained and defect-free condition upon the intermediate layer where the unstrained lattice constant of the epilayer is about the same as the partially relieved strain lattice constant or the intermediate layer. An unstrained defect-free epilayer of InGaAs has been grown on a GaAs substrate with an intermediate layer 3-10 nm in thickness of InAs.

Abstract: A method of manufacturing a transmitter optoelectronic integrated circuit (10) which comprises a double heterostructure optical emission device (11) and drive circuitry (16). The optical emission device (11) comprises a plurality of optical emission loci (21) distributed throughout an active layer (12) of the optical emission device (11). Drive circuit (16) comprises a plurality of first portions (17) and a second portion (18) wherein the plurality of first portions (17) are above the plurality of emission loci (21). Second portion (18) is integrated in a lateral orientation with respect to the plurality of first portions (17). The chemical composition of the plurality of first portions (17) are such that they are nonabsorbing to optical emissions from the optical emission device (11).

Abstract: It is desirable to implement complementary field effect transistors in group III/group V compound semiconductors, especially on InP substrates. Outstanding n-channel performance has been demonstrated in InGaAs channel devices on InP substrates. Preliminary experiments indicate that GaAsSb channel devices will result in optimal p-heterostructure FETs (HFETs). This disclosure teaches a technique to fabricate both n- and p-channel devices on the same substrate, allowing the demonstration of (C-HFET) technology. The HFET structure contains a channel region and the barrier region. The channel region consists of two distinctive parts: the p-channel and the n-channel areas. The p-channel area consists of GaAsSb, lattice matched to the InP substrate. In n-channel FETs, and ohmic contacts are formed by first doping the contact areas with Si by ion implantation, annealing the structure and then depositing and annealing the ohmic metal.

Abstract: There is provided a method for the production of a semiconductor laser device which emits laser light from an end facet thereof.

Abstract: Generally, and in one form of the invention, a multiple layer collector structure is provided which comprises a relatively thin, highly doped layer 12 and a relatively thick, low doped or non-intentionally doped layer 14.

Abstract: Generally, and in one form of the invention, a semi-insulating semiconductor substrate 10 is provided having a first surface. An HBT subcollector region 12 of a first conductivity type is implanted in the substrate 10 at the first surface. Next, an i-layer 16 is grown over the first surface, over which an HFET electron donor layer 18 of the first conductivity type is grown, the electron donor layer 18 having a wider energy bandgap than the i-layer. Subsequently, an HFET contact layer 20 of the first conductivity type is grown over the HFET donor layer 18. Next, the HFET contact 20 and donor 18 layers are etched away over the HBT subcollector region 12, after which an HBT base layer 22 of a second conductivity type is selectively grown on the i-layer 16 over the HBT subcollector region 12. Then, an HBT emitter layer 24/26/28 of the first conductivity type is selectively grown over the HBT base layer 22, the HBT emitter layer 24/26/28 having a wider energy bandgap than the HBT base layer 22.

Abstract: A dummy emitter is formed in the portion corresponding to an emitter region, on a multiplayer structural material comprising layers for forming emitter, base and collector, and using it as mask, an external base region is exposed by etching, and a projection of emitter region is formed, while the dummy emitter is inverted into an emitter electrode, thereby forming an emitter electrode metal layer to cover the whole upper surface of the emitter. Using thus formed emitter electrode metal layer, a base electrode metal layer is formed, by self-alignment, adjacently to the emitter.

Abstract: A semiconductor device and processing technique is provided for monolithic integration of a single crystal compound element semiconductor on a ceramic substrate. A high resistivity semi-insulating buffer layer is epitaxially grown on the ceramic substrate and has an elastically transitional lattice constant matching at its lower surface the lattice constant of the ceramic substrate, and matching at its upper surface the lattice constant of the semiconductor layer.

Abstract: A bipolar transistor with improved high-frequency performance is invented. The improvement is attained by eliminating a parasitic base-collector capacitance. The invented transistor is constructed upon a semi-insulating substrate, and wherein a region which underlies an extrinsic base region is semi-insulative such that the extrinsic base region does not substantially overlap the collector contact region and the collector region when viewed in the direction perpendicular to the substrate. Here, it's worthwhile to point out that a portion under the extrinsic base region is made completely semi-insulative down to the substrate. As a result, the transistor has substantially no parasitic base-collector capacitance.

Abstract: `Unintentionally` doped P type GaAs is grown on silicon by a metal organic chemical vapor deposition process in which the molecular ratio of arsenic to gallium in the growth ambient is reduced to a value that is sufficiently low to cause the creation of donor (As) site vacancies in the grown GaAs layer, which become occupied by acceptor (carbon) atoms in the metal organic compound, thereby resulting in the formation of a buffer GaAs layer having a P type majority carrier characteristic. Preferably, the silicon substrate has its growth surface inclined from the [100] plane toward the [011] direction is initially subjected to an MOCVD process (e.g. trimethyl gallium, arsine chemical vapor deposition) at a reduced temperature (e.g. 425.degree. C.) and at atmospheric pressure, to form a thin (400 Angstroms) nucleation layer. During this growth step the Group V/Group III mole ratio (of arsenic to gallium) is maintained at an intermediate value. The temperature is then ramped to 630.degree. C.

Abstract: A bipolar transistor is provided with an external base region.

Abstract: A method of fabricating heterojunction structures includes providing a semiconductor substrate and forming a plurality of semiconductor layers thereon. Ohmic and gate contacts are then formed on the plurality of semiconductor layers and portions of at least one of the semiconductor layers disposed between the ohmic and gate contacts are removed. Gate metal is then formed on the gate contacts. Source and drain regions are formed in the semiconductor layers and the formation is self-aligned to the gate metal. Following the formation of the source and drain regions, ohmic metal is formed on the ohmic contacts.

Abstract: A novel method of making a semiconductor device that comprises p-type III-V semiconductor material is disclosed. The method comprises heating of a graphite body such that the body serves as a sublimation source of carbon atoms that are incorporated into the III-V semiconductor material. Exemplarily, the carbon doped material is the base of a GaAs-based HBT.

Abstract: In the monolithic integration of HFET and DOES device, a wide band gap carrier confining semiconductor layer is provided only at predetermined locations where DOES devices are desired. This layer is not provided at other predetermined locations where HFET devices are desired as it would constitute a shunt path which would degrade the high frequency operation of the HFET devices. The invention is particularly useful where monolithic integration of optical sources, optical detectors, and electronic amplifying or switching elements is desired.

Abstract: A semiconductor device comprising a plurality of elemental active devices being operable with different threshold voltages is disclosed. Each of the elemental active devices, e.g. D made and E made HEMT, is formed of each of different active layers epitaxially grown on each of different regions of a semiconductor substrate. Since the different regions have different surface orientations or surface areas, each of the different active layers have different carrier densities corresponding to the surface orientation or the surface areas.

Abstract: A semiconductor light emitting device includes a vertical aperture produced at a main surface of a semi-insulating or insulating substrate, a transverse aperture provided in the substrate communicating with the vertical aperture, a conducting semiconductor layer buried in the vertical aperture and the transverse aperture, a groove produced by etching the substrate from the surface thereof until reaching the conducting semiconductor layer at a portion of the transverse aperture, and a light emitting element produced in the groove, and the light emitting region of the element being buried in the groove and connected with the buried conducting semiconductor layer. Accordingly, no pn junction exists at the periphery of the light emitting region, and a semiconductor light emitting element of quite low parasitic capacitance is obtained at high yield. A planar structure in which two electrodes are produced at the same plane is obtained, resulting in ease of integration and enhancement of the integration density.

Abstract: In a method for manufacturing a heterojunction bipolar transistor using a silicon microcrystal as an emitter, a mask 4 having an opening on an element forming region of the main surface of an n-type silicon monocrystal substrate 1 serving as a collector, a p-type outer base 5 is formed on a part of the element forming region of the main surface of the substrate via the opening of the mask 4 by ion-implanting p-type impurity therein, a p-type inner base 6 is formed on the entire surface of the element forming region of the substrate 1 by ion-implanting p-type impurity therein after removing the mask 4, and an n-type emitter 8 is formed by depositing an n-type silicon microcrystal layer on the inner base 6 at a growth velocity of 15 .ANG./sec by a plasma chemical vapor deposition method in a state that the temperature of said substrate 1 is maintained at a constant temperature between 460.degree. to 550.degree. C.

Abstract: A semiconductor laser includes a groove in a GaAs first current blocking layer, which extends to an Al.sub.x Ga.sub.(1-x) As second clad layer beneath the first blocking layer. The width of the groove periodically changes along the length of the resonator. Over the regions of the first current blocking layer where the groove has a smaller width, a Al.sub.z Ga.sub.(1-z) As second current blocking grating layer is formed. An Al.sub.x Ga.sub.(1-x) As third current blocking layer is disposed on the second current blocking layer and the portions of the first current blocking layer not covered by the second current blocking layer. The variation of the width of the groove is achieved by selective etching in gaseous hydrogen chloride by irradiation with an arsenic molecular beam, or by placing a liquid-phase solvent.

Abstract: This is a method for fabricating integrated heterojunction bipolar transistors (HBTs) and heterojunction field effect transistors (HFETs) on a substrate. The method comprises: forming a subcollector layer 12 over the substrate 10; forming a collector layer 14 over the subcollector layer; forming a base layer 16 over the collector layer; etching the base layer to form one or more base pedestals 16 over a portion of the collector layer; forming a buffer region 18 in a portion of the collector layer over which one or more HFETs are fabricated; forming one or more channel regions 20,22 over the buffer region; forming a wide bandgap material emitter/gate layer 26 over the base pedestal and the channel region; forming isolation regions 30,32, whereby there is one or more separate HBTs and one or more separate HFETs over the substrate utilizing an epitaxially grown emitter/gate layer to form both an HBT emitter and an HFET gate. Other devices and methods are also disclosed.

Abstract: The invention relates to a method of manufacturing a non-planar HBT transistor comprising first the step of forming the emitter, the step of etching the device around the emitter as far as the level of the base layer, exposing a region for the collector contact, the emitter being protected, and then the step of forming the base contact by self-alignment on the emitter and the collector. This method utilizes steps of profile inversion, during which two dielectric layers of different materials are successively deposited, the first of which has a uniform thickness and the second of which has a non-uniform thickness and which are etched at different rates in order to cause chosen patterns to appear. The invention moreover permits forming concomitantly buried resistors. The device obtained is particularly compact and performant and the method requires only a very limited number of masking steps, which can be realized with a non-critical resolution.

Abstract: An integrated circuit bipolar transistor is described wherein the relative semiconductor electrode areas are established by an electrode pedestal that includes a base contact positioning feature and wiring constraints are relaxed by a base pedestal that facilitates the positioning of contact wiring that is independent of contact location. A heterojunction bipolar transistor having a base area less than twice as large as the emitter area is described.

Abstract: There is disclosed a method of manufacturing an integrated circuit, comprising: the first step of growing a first epitaxial crystal on a compound semiconductor substrate, removing an unnecessary region of the first epitaxial crystal to form a residual portion, and covering the residual portion with a selective growth mask, the second step of growing a second epitaxial crystal on an exposed substrate portion, removing an unnecessary portion of the second epitaxial crystal to form a residual portion of the second epitaxial crystal, and covering the residual portion of the second epitaxial crystal with a selective growth mask, and third step of growing a third epitaxial crystal on an exposed substrate portion and removing an unnecessary region of the third epitaxial crystal, wherein the first to third epitaxial crystal form any one of a pin photodiode crystal, a heterojunction bipolar transistor crystal, and a high electron mobility transistor crystal, and are different from each other.

Abstract: A heterostructure bipolar transistor is formed by a process of steps of holding an N-type gallium arsenide body using as an emitter region in a high vacuum of 10.sup.-9 torr to 10.sup.-13 torr at a first temperature of 400.degree. C. to 1,000.degree. C. where arsenic on a surface of the gallium arsenide body drifts away, lowering the first temperature to a second temperature of 300.degree. C. to 400.degree. C. to start a molecular beam epitaxial growth of a germanium, and forming an N-type germanium layer using as a collector region.

Abstract: A process for manufacturing selectively doped heterostructure field-effect transistors (SDHTs), a desired wafer structure for SDHT fabrication and a method for isolating SDHTs on the wafer are disclosed herein. The wafer has epitaxial layers grown on a substrate. The layers are: a buffer layer of GaAs, a first spacer layer of AlGaAs, a donor layer of AlGaAs, a second spacer layer of AlGaAs, a first cap layer of GaAs, an etch-stop layer of AlGaAs and a second cap layer of GaAs. A protective layer of AlGaAs may then be grown on the second cap layer to protect the second cap layer from contamination or damage. Also a superlattice may first be grown on the substrate.This invention was made with Government support under contract No. F29601-87-R-0202 awarded by the Defense Advanced Research Projects Agency, and under contract No. F33615-84-C-1570 awarded by the Air Force Wright Aeronautical Laboratories. The Government has certain rights in this invention.

Abstract: A method of producing a quasi-flat semiconductor device capable of a multi-wavelength laser effect and the device thus produced.On the basis of a double heterostructure stack supported by a substrate comprising steps, following levelling of the stack and diffusion through a flat surface, a semiconductor device is obtained which is capable of a multi-wavelength laser effect, of which the different junctions are situated in a plane parallel with the base of the substrate.

Abstract: A semiconductor device of a multilayer structure comprising semiconductor materials of different properties manufactured by using at least a step of epitaxially forming a semiconductor material layer on a substrate and a passivation film layer thereover, a step of introducing impurities into specific portions of the epitaxially formed semiconductor material layer and a step of removing the passivation film layer formed directly above the epitaxially formed semiconductor material layer within an epitaxial device and then applying epitaxial growing. Impurities introduced additionally to specific portions of the layer inside are substantially eliminated at the boundary adjacent the layer above the region introduced with impurities and the properties of the thus-produced semiconductors vary abruptly at the boundary between the layer in which the impurities are introduced and the layer thereabove.

Abstract: For improvement in a transit time of electrons, there is disclosed a heterojunction field effect transistor fabricated on a semi-insulating GaAs substrate, comprising a first layer overlying the semi-insulating substrate and formed of a high-purity GaAs, a second layer overlying the first layer and formed of an n-type AlGaAs which is smaller in electron affinity than the high-purity GaAs, a source region penetrating from the first layer into the second layer so as to be in contact with the active channel layer formed in the first layer and formed of an gallium-rich AlGaAs, a drain region, and a gate electrode formed on the second layer, an energy gap takes place between the source region and the first layer due to a lower edge of the conduction band thereof higher in energy level than that of the high-purity GaAs, thereby accelerating electrons supplied from the source region to the active channel layer.

Abstract: A quaternary semiconductor diffraction grating, such as an InGaAsP grating suitable for a DFB laser, is embedded in a semiconductor substrate, such as InP. In one embodiment, the grating is fabricated by(1) forming on the top surface of an InP substrate body an epitaxial layer of InGaAsP coated with an epitaxial layer of InP;(2) forming a pattern of apertures penetrating through the layers of InP and InGaAsP; and(3) heating the body to a temperature sufficient to cause a mass transport of InP from the InP epitaxial layer, the thickness of the InP layer being sufficient to bury the entire surface of the InGaAsP layer with InP.

Abstract: Disclosed is a semiconductor device including a heterojunction bipolar transistor in which the front surface of a base layer and the surface of an emitter-base junction are covered with a high-resistivity layer of compound semiconductor containing at least one constituent element common to an emitter layer and the base layer.

Abstract: A heteroepitaxial growth method wherein a III-V group compound semiconductor is formed on a silicon substrate. A first amorphous III-V group compound semiconductor layer is formed on the silicon substrate before forming a III-V group compound semiconductor crystal layer on the amorphous III-V group compound semiconductor layer. A second amorphous III-V group semiconductor layer having a thickness greater than the crystal layer is formed on the III-V group compound semiconductor crystal layer and subjected to a solid phase epitaxial growth whereby the second amorphous III-V group compound semiconductor layer is made a single crystalline layer.

Abstract: In situ removal of selected or patterned portions of semiconductor layers is accomplished by induced evaporation enhancement to form patterned buried impurity layers in semiconductor devices, such as heterostructure lasers and array lasers, which function as buried impurity induced layer disordering (BIILD) sources upon subsequent annealing. These layers may be formed to either function as buried impurity induced layer disordering (BIILD) sources or function as a reverse bias junction configuration of confining current to the active region of a laser structure. Their discussion here is limited to the first mentioned function.

Abstract: A method for planarizing surfaces in multi-layered semiconductor structures using elevated features in the form of semiconductor materials, such as for forming heterojunctions, or interconnection metal. A process of forming the features includes leaving residual photoresist on the features. After feature formation and definition of transistor or other structure locations, dielectric material is deposited across the structure. Remaining photoresist is subsequently removed along with dielectric deposited thereon leaving dielectric between the features. A layer of polyimide is spun on the structure and into depressions between the dielectric and features. Typically material deposition, etching, dielectric backfilling and spin-coating steps are repeated until a predetermined number of contact or conductivity regions or interconnection metal layers are formed in the desired multi-layered structure.

Abstract: A method for growing high quality epitaxial films using low pressure MOCVD that includes providing a substrate that is misoriented from a singular plane, placing the substrate into an MOCVD reactor at a total pressure of less than 0.2 atmospheres and then growing an epitaxial film on the substrate. When providing a misoriented gallium arsenide substrate, the MOCVD reactor is set at a temperature in the range of 650 to 750 degrees centigrade to grow an aluminum gallium arsenide film. This temperature is substantially lower than that at which aluminum gallium arsenide epitaxial films are commonly grown and the resulting film has a smooth surface morphology and enhanced photoluminesence properties.

Abstract: The mobility of a relatively narrow bandgap semiconductor material can be significantly enhanced by incorporating it into a multilayered structure (10) comprising a first plurality of relatively narrow bandgap layers (12) of the material and a second plurality of wider bandgap semiconductor layers (14) interleaved with and contiguous with the first plurality. The wide bandgap and narrow bandgap layers are substantially lattice-matched to one another, and the wide bandgap layers are doped such that the impurity concentration-thickness product therein is greater than the same product in the narrow bandgap layers. The fabrication of the structure by MBE to enhance the mobility of GaAs is specifically described. In this case, the narrow bandgap layers (12) comprise GaAs and are unintentionally doped to about 10.sup.14 /cm.sup.3, whereas the wide bandgap layers (14) comprise AlGaAs doped n-type to about 10.sup.16 to 10.sup.18 /cm.sup.3. The incorporation of this structure in an FET is also described.