With Mechanical Mask, Shield Or Shutter For Shielding Workpiece Patents (Class 156/345.3)
  • Patent number: 8273211
    Abstract: Disclosed herein is a flat panel display manufacturing apparatus in a predetermined process is performed using plasma generated therein. In such a flat panel display manufacturing apparatus, a process gas is supplied into a chamber in an evenly diffused state to generate even plasma inside a symmetrical interior space of the chamber. Consequently, the flat panel display manufacturing apparatus can appropriately control flow rate of the plasma, thereby being capable of performing even processing on a large-scale substrate. In the flat panel display manufacturing apparatus, a substrate pedestal thereof is provided with a combination of vertical and horizontal shielding members, thereby being entirely protected from attack of the plasma, resulting in an increased life-span.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: September 25, 2012
    Assignee: Advanced Display Process Engineering Co., Ltd.
    Inventors: Gwang Ho Hur, Jun Young Choi, Cheol Won Lee, Hyun Hwan Ahn, Young Joo Hwang, Chun Sik Kim
  • Publication number: 20120234793
    Abstract: In a method for the treatment of a substrate surface of a flat substrate with a process medium at the substrate underside, the process medium has a removing or etching effect on the substrate surface. The substrates are wetted with the process medium from below in a manner lying horizontally. The upwardly facing substrate top side is wetted or covered with water or a corresponding protective liquid over a large area or over the whole area as protection against the process medium acting on the substrate top side.
    Type: Application
    Filed: July 28, 2010
    Publication date: September 20, 2012
    Inventor: Christian Schmid
  • Publication number: 20120238100
    Abstract: Provided is an etching method capable of etching even a silicon film that is included in a multi-layered structure by using a resist film or an organic film as a mask, and also capable of integrally etching the silicon film and a silicon oxide film disposed under the silicon film. The etching method which etches the multi-layered structure including the silicon oxide film and the silicon film formed on the silicon oxide film, includes: integrally etching the silicon film and the silicon oxide film included in the multi-layered structure by using a resist film or an organic film as an etching mask and using an etching gas containing a CH2F2 gas as an etching gas, when the silicon film and the silicon oxide film in the multi-layered structure are etched.
    Type: Application
    Filed: March 14, 2012
    Publication date: September 20, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Aki AKIBA
  • Patent number: 8268116
    Abstract: Apparatus and methods protect a central process exclusion region of a substrate during processing of an edge environ region of process performance. Removal of undesired materials is only from the edge environ region while the central device region is protected from damage. Field strengths are configured to protect the central region from charged particles from plasma in a process chamber and to foster removal of the undesired materials from only the edge environ region. A magnetic field is configured with a peak value adjacent to a border between the central and edge environ regions. A strong field gradient extends from the peak radially away from the border and away from the central region to repel the charged particles from the central region. The strength and location of the field are adjustable by axial relative movement of magnet sections, and flux plates are configured to redirect the field for desired protection.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: September 18, 2012
    Assignee: Lam Research Corporation
    Inventors: Andrew D. Bailey, III, Yunsang Kim
  • Publication number: 20120223051
    Abstract: Methods for fabricating sublithographic, nanoscale microchannels utilizing an aqueous emulsion of an amphiphilic agent and a water-soluble, hydrogel-forming polymer, and films and devices formed from these methods are provided.
    Type: Application
    Filed: May 17, 2012
    Publication date: September 6, 2012
    Inventor: Dan B. Millward
  • Publication number: 20120219759
    Abstract: A micro structure which is preferred as an original plate of an antireflection, a mold of nano imprint or injection molding is obtained by a single particle film etching mask on which each particle is precisely aligned and closest packed in two dimensions. A single particle film etching mask is produced by a drip step wherein a dispersed liquid in which particles dispersed in a solvent are dripped onto a liquid surface of a water tank, a single particle film formation step in which a single particle film which consists of the particles by volatizing a solvent is formed, and a transfer step in which the single particle film is transferred to a substrate. The single particle film etching mask on which particles are closest packed in two dimensions, has a misalignment D(%) of an array of the particles that is defined by D(%)=|B?A|×100/A being less than or equal to 10%. However, A is the average diameter of the particles, and B is the average pitch between the particles in the single particle film.
    Type: Application
    Filed: May 9, 2012
    Publication date: August 30, 2012
    Applicant: OLI PAPER CO., LTD.
    Inventor: Kei Shinotsuka
  • Patent number: 8252140
    Abstract: The embodiments provide structures and mechanisms for removal of etch byproducts, dielectric films and metal films on and near the substrate bevel edge, and chamber interior to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. In one example, a chamber for wafer bevel edge cleaning is provided. The chamber includes a bottom electrode having a bottom electrode surface for supporting the wafer when present. Also included is a top edge electrode surrounding an insulating plate. The insulator plate is opposing the bottom electrode. The top edge electrode is electrically grounded and has a down-facing L shape. Further included in the chamber is a bottom edge electrode that is electrically grounded and spaced apart from the bottom electrode. The bottom edge electrode is disposed to encircle the bottom electrode. The bottom edge electrode is oriented to oppose the down-facing L shape of the top edge electrode.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: August 28, 2012
    Assignee: Lam Research Corporation
    Inventors: Gregory S. Sexton, Andrew D. Bailey, III, Andras Kuthi
  • Publication number: 20120211162
    Abstract: A mask fixture for etching an item includes: a top fixture disposed over the item, including a reservoir centered within the top fixture for containing an etchant; a bottom fixture underneath the item to be etched including a recessed surface area centered within the bottom fixture; and an etch-resistant window for holding the item to be etched, the etch-resistant window disposed entirely within the recessed surface area. In addition, a small via centered within and intersecting both the top and bottom fixtures acts as a path for a high intensity light beam.
    Type: Application
    Filed: January 30, 2012
    Publication date: August 23, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Arthur Wood Ellis
  • Publication number: 20120208368
    Abstract: A method of manufacturing an SiC semiconductor device includes the steps of forming a first oxide film on a first surface of an SiC semiconductor, removing the first oxide film, and forming a second oxide film constituting the SiC semiconductor device on a second surface exposed as a result of removal of the first oxide film in the SiC semiconductor. Between the step of removing the first oxide film and the step of forming a second oxide film, the SiC semiconductor is arranged in an atmosphere cut off from an ambient atmosphere.
    Type: Application
    Filed: February 25, 2011
    Publication date: August 16, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Keiji Wada, Satomi Itoh, Toru Hiyoshi
  • Publication number: 20120184097
    Abstract: A three-dimensional stacked IC device has a stack of contact levels at an interconnect region. According to some examples of the present invention, it only requires a set of N etch masks to create up to and including 2N levels of interconnect contact regions at the stack of contact levels. According to some examples, 2x?1 contact levels are etched for each mask sequence number x, x being a sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N. Methods create the interconnect contact regions aligned with landing areas at the contact levels.
    Type: Application
    Filed: March 16, 2011
    Publication date: July 19, 2012
    Applicant: Macronix International Co., Ltd.
    Inventors: Shih-Hung CHEN, Hang-Ting LUE
  • Publication number: 20120160806
    Abstract: Methods and apparatus to provide efficient and scalable RF inductive plasma processing are disclosed. In some aspects, the coupling between an inductive RF energy applicator and plasma and/or the spatial definition of power transfer from the applicator are greatly enhanced. The disclosed methods and apparatus thereby achieve high electrical efficiency, reduce parasitic capacitive coupling, and/or enhance processing uniformity. Various embodiments comprise a plasma processing apparatus having a processing chamber bounded by walls, a substrate holder disposed in the processing chamber, and an inductive RF energy applicator external to a wall of the chamber. The inductive RF energy applicator comprises one or more radiofrequency inductive coupling elements (ICEs). Each inductive coupling element has a magnetic concentrator in close proximity to a thin dielectric window on the applicator wall.
    Type: Application
    Filed: August 20, 2010
    Publication date: June 28, 2012
    Inventors: Valery A. Godyak, Charles Crapuchettes, Vladimir Nagorny
  • Publication number: 20120151847
    Abstract: The disclosure provides to a PDC element protective system including a mask configured to protect a non-leached portion of a leached polycrystalline diamond compact (PDC) element during a leaching process. The mask may be formed from or coated with polytetrafluoroethylene (PTFE). The disclosure also provides a leaching system containing such a mask and a leaching vessel as well as methods of using the protective and leaching systems. The disclosure further provides a Lewis acid-based leaching agent and methods of its use. Finally, the disclosure provides a method of recycling a PDC or carbide element using a Lewis acid-based leaching agent.
    Type: Application
    Filed: June 24, 2011
    Publication date: June 21, 2012
    Inventors: Ram L. Ladi, Carl Edward Wells, Bhupinder Kumar Kataria, Stephen W. Almond
  • Publication number: 20120152460
    Abstract: A test mask set includes a first test mask having a plurality of gate pattern areas disposed therein, each of the plurality of gate pattern areas having one or more gate patterns; and a second test mask having a plurality of active pattern areas disposed therein, each of the plurality of active pattern areas having one or more active patterns. The gate patterns formed in different areas among the plurality of gate pattern areas differ in at least one of a gate spacing or a gate width.
    Type: Application
    Filed: September 21, 2011
    Publication date: June 21, 2012
    Inventors: Ho-Young KIM, Seung-Jae LEE, Bo-Un YOON
  • Publication number: 20120138227
    Abstract: A method for forming an array area with a surrounding periphery area, wherein a substrate is disposed under an etch layer, which is disposed under a patterned organic mask defining the array area and covers the entire periphery area is provided. The patterned organic mask is trimmed. An inorganic layer is deposited over the patterned organic mask where a thickness of the inorganic layer over the covered periphery area of the organic mask is greater than a thickness of the inorganic layer over the array area of the organic mask. The inorganic layer is etched back to expose the organic mask and form inorganic spacers in the array area, while leaving the organic mask in the periphery area unexposed. The organic mask exposed in the array area is stripped, while leaving the inorganic spacers in place and protecting the organic mask in the periphery area.
    Type: Application
    Filed: February 9, 2012
    Publication date: June 7, 2012
    Applicant: LAM RESEARCH CORPORATION
    Inventors: S. M. Reza Sadjadi, Amit Jain
  • Publication number: 20120103519
    Abstract: Included within the scope of the invention are plasma etch-resistant films for substrates. The films include a yttria material and a at least a portion of the yttria material is in a crystal phase having an orientation defined by a Miller Index notation {111}. Also included are methods of manufacturing plasma etch-resistant films on a substrate. Such methods include applying a yttria material-containing composition onto at least a portion of a surface of a substrate to form a film. The film includes a yttria material and at least a portion of the yttria material is in a crystal phase having an orientation defined by a Miller Index notation {111}.
    Type: Application
    Filed: October 24, 2011
    Publication date: May 3, 2012
    Inventors: Mohammed Aheem, Sang-Ho Lee, Thomas Mercer, Vasil Vorsa
  • Publication number: 20120097329
    Abstract: The present invention is directed to stencils for high-throughput, high-resolution etching of substrates and processes of making and using the same.
    Type: Application
    Filed: May 20, 2011
    Publication date: April 26, 2012
    Applicants: Merck Patent Gesellschaft, Nano Terra Inc.
    Inventors: Eric STERN, Graciela Beatriz BLANCHET, Lindsay HUNTING, Brian T. MAYERS, Joseph M. MCLELLAN, Patrick REUST, Ralf KÜGLER, Jennifer GILLIES
  • Publication number: 20120080406
    Abstract: A system and a method for preparing a lamella. The method may include aligning, by the manipulator, a mask and a sample. Positioning the mask and the sample in front of an ion miller while unchanging the spatial relationship between the mask and the sample. Milling a first exposed portion of the sample until exposing a first sidewall of the lamella. Positioning the mask and the sample in front of the ion miller so that the mask masks a second masked portion of the sample. Milling, by the ion miller, the second exposed portion of the sample until exposing a second sidewall of the lamella. Removing, by the miller, matter from both sides of the lamella; and detaching the lamella from the sample.
    Type: Application
    Filed: June 30, 2011
    Publication date: April 5, 2012
    Applicant: CAMTEK LTD.
    Inventors: Dimitry BOGUSLAVSKY, Colin SMITH
  • Publication number: 20120080148
    Abstract: An inductively coupled plasma ion source for a focused ion beam (FIB) system is disclosed, comprising an insulating plasma chamber with a feed gas delivery system, a compact radio frequency (RF) antenna coil positioned concentric to the plasma chamber and in proximity to, or in contact with, the outer diameter of the plasma chamber. In some embodiments, the plasma chamber is surrounded by a Faraday shield to prevent capacitive coupling between the RF voltage on the antenna and the plasma within the plasma chamber. High dielectric strength insulating tubing is heat shrunk onto the outer diameter of the conductive tubing or wire used to form the antenna to allow close packing of turns within the antenna coil. The insulating tubing is capable of standing off the RF voltage differences between different portions of the antenna, and between the antenna and the Faraday shield.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Applicant: FEI COMPANY
    Inventor: Shouyin Zhang
  • Publication number: 20120007221
    Abstract: A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 12, 2012
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Richard J. Huang, Scott A. Bell, Srikanteswara Dakshina-Murthy, Philip A. Fisher, Richard C. Nguyen, Cyrus E. Tabery, Lu You
  • Patent number: 8083890
    Abstract: The various embodiments provide apparatus and methods of removal of unwanted deposits near the bevel edge of substrates to improve process yield. The embodiments provide apparatus and methods with center and edge gas feeds as additional process knobs for selecting a most suitable bevel edge etching processes to push the edge exclusion zone further outward towards the edge of substrates. Further the embodiments provide apparatus and methods with tuning gas(es) to change the etching profile at the bevel edge and using a combination of center and edge gas feeds to flow process and tuning gases into the chamber. Both the usage of tuning gas and location of gas feed(s) affect the etching characteristics at bevel edge. Total gas flow, gap distance between the gas delivery plate and substrate surface, pressure, and types of process gas(es) are also found to affect bevel edge etching profiles.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: December 27, 2011
    Assignee: Lam Research Corporation
    Inventors: Tong Fang, Yunsang Kim, Andrew D. Bailey, III, Olivier Rigoutat, George Stojakovic
  • Publication number: 20110265950
    Abstract: A semiconductor device manufacturing method includes removing copper deposits, by use of an organic acid gas and an oxidizing gas, from a surface of a second interlayer insulation film having a groove formed therein and reaching a copper-containing electric connector member. The second interlayer insulation film is disposed on a first interlayer insulation film provided with the electric connector member. The method then includes reducing a surface of the electric connector member exposed at a bottom of the groove of the second interlayer insulation film; forming a barrier layer on the second interlayer insulation film; and forming a copper-containing conductive film to fill the groove of the second interlayer insulation film.
    Type: Application
    Filed: July 7, 2011
    Publication date: November 3, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hidenori MIYOSHI, Kazuichi Hayashi
  • Patent number: 8048227
    Abstract: A compensation plate used in a film coating device includes a main body defining a plurality of guiding holes, a plurality of moveable blades connected to the main body, and a plurality of connectors. Each of the plurality of moveable blades defines two through holes corresponding to one of the plurality of guiding holes. The plurality of connectors engage in the through holes and the guiding holes, fix each of the plurality of moveable blades to the main body when each of the plurality of connectors is fastened, and slide in each of the plurality of guiding holes with each of the moveable blades when each of the plurality of connectors releases.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: November 1, 2011
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Chih-Wei Tso, Po-Wen Chan
  • Publication number: 20110253794
    Abstract: A method for manufacturing a component by etching, the component including a substrate and an electrically conductive line configuration supported by the substrate, the electrically conductive line configuration being formed by etching away locally an electrically conductive coating supported by the substrate. An etching mask is used to control locally removal and maintenance of the electrically conductive coating by using an etchant and it includes barrier material on at least one main area corresponding to the electrically conductive line configuration to be maintained during etching The etching mask further includes at least one sub-area comprising barrier material, the sub-area being arranged at a distance from the edge of the main area.
    Type: Application
    Filed: December 15, 2008
    Publication date: October 20, 2011
    Applicant: UPM RFID OY
    Inventor: Tuomas Koskelainen
  • Publication number: 20110226726
    Abstract: A dry etching apparatus for performing dry etching in manufacture of a set of touch screen panels on a mother substrate, including a chamber, an upper electrode in the chamber at an upper portion thereof, the upper electrode configured to apply a high-frequency power source (RF) to the interior of the chamber, a lower electrode in the chamber at a lower portion thereof, the lower electrode configured to apply the high-frequency power source to the interior of the chamber, a gas injection port configured to inject a compound mixture gas into the chamber, an exhaust port configured to exhaust a reactive gas produced in the interior of the chamber, and a shadow mask disposed above a location on the lower electrode for the mother substrate for the touch screen panels, the shadow mask having a plurality of exposure windows respectively corresponding to a plurality of exposure portions to be formed.
    Type: Application
    Filed: February 11, 2011
    Publication date: September 22, 2011
    Inventors: Bong-Sub Song, Soung-Chang Ku
  • Publication number: 20110210096
    Abstract: A method of chemically milling a workpiece includes depositing a masking material on portions of the workpiece according to a predefined masking pattern such that other portions of the workpiece that are desired to be milled are unmasked. Material from the unmasked desired milling areas of the workpiece is chemically removed.
    Type: Application
    Filed: March 1, 2010
    Publication date: September 1, 2011
    Inventor: Edris Raji
  • Patent number: 8007631
    Abstract: A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: August 30, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srikanteswara Dakshina-Murthy, Bhanwar Singh, Ramkumar Subramanian
  • Publication number: 20110206833
    Abstract: An extension electrode with enhanced durability and etching rate for plasma bevel etchers. The extension electrode comprises a plasma exposed truncated conical surface on an annular aluminum body. The aluminum body can roughened prior to anodization and coated with a ceramic material such as yttria.
    Type: Application
    Filed: February 11, 2011
    Publication date: August 25, 2011
    Applicant: Lam Research Corporation
    Inventors: Gregory Sexton, Paul Aponte
  • Publication number: 20110198033
    Abstract: A shutter device having two shutter plates, which shield between an IBS and a substrate, is configured such that the two shutter plates are disposed at symmetrical positions across the IBS and can perform an opening/closing operation in synchronization with a rotation of a rotation-link-member which is rotatably disposed surrounding the IBS. With the configuration, the shutter device can reduce an offset of a shield range in the opening/closing operation.
    Type: Application
    Filed: February 15, 2011
    Publication date: August 18, 2011
    Applicant: CANON ANELVA CORPORATION
    Inventor: Masashi Tsujiyama
  • Publication number: 20110201136
    Abstract: Combinatorial evaluation of dry semiconductor processes is described, including rotating a mask comprising a plurality of apertures, wherein the mask is positioned between a dry semiconductor processing source and the substrate, and performing a dry semiconductor process through the apertures of the mask at a plurality of intervals during the rotating the mask to combinatorially create a plurality of processed regions on the substrate, wherein the apertures of the mask are arranged in such a way that the plurality of processed regions have different geometries relative to the processing source, and analyzing the processed regions to determine effects of time and geometry on the processed regions.
    Type: Application
    Filed: April 27, 2011
    Publication date: August 18, 2011
    Applicant: INTERMOLECULAR, INC.
    Inventor: Tony Chiang
  • Publication number: 20110180212
    Abstract: Chambers for processing a bevel edge of a substrate are provided. One such chamber includes a bottom electrode defined to support a substrate in the chamber. The bottom electrode has a bottom first level for supporting the substrate and a bottom second level near an outer edge of bottom electrode. The bottom second level is defined at a step below the bottom first level. Further included is a top electrode oriented above the bottom electrode. The top electrode having a top first level and a top second level, where the top first level is opposite the bottom first level and the top second level is opposite the bottom second level. The top second level is defined at a step above the top first level. A bottom ring mount oriented at the bottom second level is included. The bottom ring mount includes a first adjuster for moving a bottom permanent magnet toward and away from the top electrode. Further included is a top ring mount oriented at the top second level.
    Type: Application
    Filed: April 7, 2011
    Publication date: July 28, 2011
    Inventors: Andrew D. Bailey, III, Yunsang Kim
  • Patent number: 7978583
    Abstract: Improved techniques for forming a reflective layer of an optical disc are provided. One improvement includes forming the reflective layer over an information layer of the disc by utilizing a metallizer and a masking device having an angled lip configured to align to an outer edge of the information layer. The masking device allows the applied reflective layer to extend to the outer diameter edge of the information layer, and shields plasma generated by the metallizer from reaching internal components of the metallizer. The masking device may include a pusher having a spring mechanism attached to an inner masking portion of the masking device.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: July 12, 2011
    Assignee: Cinram International Inc.
    Inventor: Kenneth James Rinaldi
  • Publication number: 20110159697
    Abstract: There are provided an etching method and an etching apparatus suitable for etching an antireflection coating layer by using a resist film as a mask. The etching method includes forming the antireflection coating layer (Si-ARC layer) on an etching target layer; forming a patterned resist film (ArF resist film) on the antireflection coating layer; and forming a desired pattern on the antireflection coating layer by introducing an etching gas including a CF4 gas, a COS gas and an O2 gas into a processing chamber and etching the antireflection coating layer by the etching gas while using the resist film as a mask.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 30, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Takahito Mukawa
  • Publication number: 20110132540
    Abstract: A plasma processing apparatus is disclosed in which a wafer mounted on a sample stage arranged in a processing chamber in a vacuum vessel is processed using a plasma formed in the processing chamber. A dielectric bell jar makes up the upper part of the vacuum vessel and surrounds processing chamber. A coil-shaped antenna wound on the outer periphery of the bell jar is supplied with the high-frequency power to form the plasma. A Faraday shield of a conductive material is formed of double layers including inner and outer layers arranged in spaced relation to each other between the antenna and the bell jar, each layer having a plurality of slits and set at a predetermined potential. The slits of the inner and outer layers of the Faraday shield are arranged in staggered fashion.
    Type: Application
    Filed: February 25, 2010
    Publication date: June 9, 2011
    Inventors: Yusaku SAKKA, Ken Yoshioka, Ryoji Nishio
  • Patent number: 7951261
    Abstract: The present invention relates to a plasma etching apparatus. In the apparatus, potential difference is applied between a substrate support with a substrate seated thereon and a electrode surrounding an edge region of the substrate, and a distance between the substrate and the electrode is set to 3 mm or less so as to locally generate plasma in an area between the substrate and the electrode, thereby removing particles and a thin film in the edge region of the substrate.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: May 31, 2011
    Assignee: Jusung Engineering Co. Ltd.
    Inventor: Bu-Il Jeon
  • Publication number: 20110117323
    Abstract: The present invention provides a surface processing method for forming recesses and protrusions on a surface of an object to be processed, at least including: a process for attaching a polymer film mask containing a binding resin and organic pigment particles which are contained in the binding resin on the surface of the object to be processed; and a process for etching the surface of the object to be processed to which the polymer film mask has been attached so as to form recesses and protrusions on the surface of the object to be processed. Also, the present invention provides a mask for surface processing used for the surface processing method.
    Type: Application
    Filed: June 18, 2009
    Publication date: May 19, 2011
    Applicant: FUJIFILM CORPORATION
    Inventor: Kimio Ichikawa
  • Patent number: 7943005
    Abstract: A method and apparatus for etching photomasks is provided herein. In one embodiment, the apparatus comprises a process chamber having a support pedestal adapted for receiving a photomask. An ion-neutral shield is disposed above the pedestal and a deflector plate assembly is provided above the ion-neutral shield. The deflector plate assembly defines a gas flow direction for process gases towards the ion-neutral shield, while the ion-neutral shield is used to establish a desired distribution of ion and neutral species in a plasma for etching the photomask.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: May 17, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Ajay Kumar, Madhavi R. Chandrachood, Richard Lewington, Darin Bivens, Amitabh Sabharwal, Sheeba J. Panayil, Alan Hiroshi Ouye
  • Publication number: 20110111593
    Abstract: According to one embodiment, a pattern formation method is disclosed. The method can form a patterning film on a substrate. The method can transfer a form pattern provided on a template onto an imprint material by bringing the template into contact with the imprint material. The imprint material is coated on the patterning film. In addition, the method can perform patterning including etching the patterning film using the imprint material including the transferred form pattern as a mask. The transferring is implemented using a condition determined based on data relating to at least one selected from a dimension and a shape of a pattern of the patterning film after the patterning.
    Type: Application
    Filed: September 17, 2010
    Publication date: May 12, 2011
    Inventor: Masahiro KANNO
  • Publication number: 20110108895
    Abstract: A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer.
    Type: Application
    Filed: January 3, 2011
    Publication date: May 12, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xi Li, Richard Stephen Wise
  • Publication number: 20110111173
    Abstract: This invention provides a surface processing mask having a film mask and a method for manufacturing the same. In the film mask, particles are present as a single layer without overlapping with each other or particles containing first particles and second particles having etching resistance lower than that of the first particles are contained. Moreover, the invention provides a surface processing method including disposing the film mask on the front surface of a process target, and etching the front surface to form irregularities and an optical device having a substrate processed by the surface processing method. Moreover, the invention provides a particle-containing film in which particles are arranged to form a single layer without overlapping with each other and a method for manufacturing the same.
    Type: Application
    Filed: July 15, 2009
    Publication date: May 12, 2011
    Applicant: FUJIFILM CORPORATION
    Inventors: Shotaro Ogawa, Kimio Ichikawa
  • Patent number: 7938907
    Abstract: A device for fabricating a mask by plasma etching a semiconductor substrate comprises a semiconductor substrate part of the area whereof is partially covered by a mask for protecting at least one area that must not be etched and for exposing at least one area including a pattern to be etched, a support for the substrate and means for generating a plasma in the form of a flow of ions toward the substrate. According to the invention the device further comprises means for confining the ions, including a conductive material screen disposed over the substrate and along the limit between the pattern area to be etched and the area not to be etched.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: May 10, 2011
    Assignee: Alcatel
    Inventors: Michel Puech, Martial Chabloz
  • Patent number: 7938931
    Abstract: The embodiments provide structures and mechanisms for removal of etch byproducts, dielectric films and metal films on and near the substrate bevel edge, and chamber interior to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. In an exemplary embodiment, a plasma processing chamber configured to clean a bevel edge of a substrate is provided. The plasma processing chamber includes a bottom electrode configured to receive the substrate, wherein the bottom electrode is coupled to a radio frequency (RF) power supply. The plasma processing chamber also includes a top edge electrode surrounding an insulating plate opposing the bottom electrode. The top edge electrode is electrically grounded. The plasma processing chamber further includes a bottom edge electrode surrounding the bottom electrode. The bottom edge electrode opposes the top edge electrode.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: May 10, 2011
    Assignee: Lam Research Corporation
    Inventors: Gregory S. Sexton, Andrew D. Bailey, III, Andras Kuthi
  • Patent number: 7909960
    Abstract: Improved mechanisms of removal of etch byproducts, dielectric films and metal films near the substrate bevel edge, and etch byproducts on substrate backside and chamber interior is provided to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. An exemplary plasma etch processing chamber configured to clean a bevel edge of a substrate is provided. The chamber includes a bottom edge electrode surrounding a substrate support in the plasma processing chamber, wherein the substrate support is configured to receive the substrate and the bottom edge electrode and the substrate support are electrically isolated from each other by a bottom dielectric ring.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: March 22, 2011
    Assignee: Lam Research Corporation
    Inventors: Yunsang Kim, Andrew D. Bailey, III
  • Patent number: 7909961
    Abstract: A method and apparatus for etching photomasks are provided herein. The apparatus includes a process chamber with a shield above a substrate support. The shield comprises a plate with apertures, and the plate has two zones with at least one characteristic, such as material or potential bias, that is different from each other. The method provides for etching a photomask substrate with a distribution of ions and neutral species that pass through the shield.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: March 22, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Ajay Kumar, Madhavi R. Chandrachood, Richard Lewington, Darin Bivens, Amitabh Sabharwal, Sheeba J. Panayil, Alan Hiroshi Ouye
  • Publication number: 20110049100
    Abstract: Provided are a substrate holder, a substrate supporting apparatus, a substrate processing apparatus, and a substrate processing method. Particularly, there are provided a substrate holder, a substrate supporting apparatus, a substrate processing apparatus, and a substrate processing method that are adapted to improve process efficiency and etch uniformity at the back surface of a substrate.
    Type: Application
    Filed: January 15, 2009
    Publication date: March 3, 2011
    Applicant: CHARM ENGINEERING CO., LTD.
    Inventors: Young Ki Han, Young Soo Seo, Hyoung Won Kim, Chi Kug Yoon, Sang Hoon Lee
  • Patent number: 7897008
    Abstract: An apparatus for controlling a plasma etching process includes plasma control structure that can vary a size of a plasma flow passage, vary a speed of plasma flowing through the plasma flow passage, vary plasma concentration flowing through the plasma flow passage, or a combination thereof.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: March 1, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Ming Chang, Chi-Lun Lu
  • Publication number: 20110042347
    Abstract: Method and plasma treatment apparatus for treatment of a substrate surface (1) using an atmospheric pressure plasma. An atmospheric pressure plasma is provided in a treatment space (5) between a first electrode (2) and a second electrode (3). Furthermore, a substrate (1) and a mask web (7) in contact with the substrate (1) are provided. A plasma generating power is applied to the first and second electrode (2, 3) for treatment of surface areas of the substrate (1) exposed by the mask web (7), in which the substrate (1) and mask web (7) are moved synchronously through the treatment space (5).
    Type: Application
    Filed: January 29, 2009
    Publication date: February 24, 2011
    Applicant: Fujifilm Manufacturing Europe B.V.
    Inventors: Bruno Alexander Korngold, Hindrik Willem De Vries, Eugen Aldea
  • Publication number: 20110030895
    Abstract: A method for etching a dielectric layer is provided. A patterned mask with mask features is formed over a dielectric layer. The mask has isolated areas and dense areas of the mask features. The mask is trimmed by a plurality of cycles, where each cycle includes depositing a deposition layer, and selectively etching the deposition layer and the patterned mask. The selective etching selectively trims the isolated areas of the mask with respect to the dense areas of the mask. The dielectric layer is etched using the thus trimmed mask. The mask is removed.
    Type: Application
    Filed: October 19, 2010
    Publication date: February 10, 2011
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Supriya GOYAL, Dongho HEO, Jisoo KIM, S.M. Reza SADJADI
  • Publication number: 20110024041
    Abstract: An etching apparatus includes a process chamber into which an etching gas is introduced, an electrode for generating plasma disposed in the process chamber, a stage disposed in the process chamber, on which a substrate is placed, and a shadow ring disposed in the process chamber and placed above the stage, so as to cover the circumferential portion and an inner region adjacent thereto of the substrate in a non-contact manner. The shadow ring has an irregular pattern on the inner circumferential edge thereof.
    Type: Application
    Filed: October 5, 2010
    Publication date: February 3, 2011
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Masahiro Komuro
  • Patent number: 7875555
    Abstract: A method for treating a substrate with plasma over a wide pressure range is described. The method comprises exposing the substrate to a low pressure plasma in a process chamber. Further, the method comprises exposing the substrate to a high pressure plasma in the process chamber.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: January 25, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Lee Chen, Merritt Funk
  • Publication number: 20110014792
    Abstract: A fin mask for forming saddle type fins in each of active regions formed in an island shape having a certain size with a major axis and a minor axis includes a first fin mask of a line type, and a second fin mask of an island type, wherein the first fin mask and the second fin mask in combination expose saddle type fin regions and cover ends of the neighboring active regions along the major axis.
    Type: Application
    Filed: September 27, 2010
    Publication date: January 20, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventor: Kwang-Ok KIM