Preformed Panel Circuit Arrangement (e.g., Printed Circuit) Patents (Class 174/250)
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Patent number: 11628728Abstract: A battery module includes a lower housing and a plurality of battery cells. The plurality of battery cells are electrically coupled together to produce a voltage. The module also includes an assembly disposed over the battery cells and coupled to the lower housing. The assembly may include a lid and a plurality of bus bar interconnects mounted on the lid. The module also includes a printed circuit board (PCB) assembly disposed on and coupled to the assembly. The PCB assembly may include a PCB. The module also includes a cover disposed over and coupled to the lower housing to hermetically seal the battery module. Also disclosed is a method of manufacturing the battery module.Type: GrantFiled: September 24, 2019Date of Patent: April 18, 2023Assignee: CPS Technology Holdings LLCInventors: Ronald J. Dulle, Mark D. Gunderson, Bryan L. Thieme, Richard M. DeKeuster, Edward J. Soleski, Robert J. Mack, Gary P. Houchin-Miller, Stephen D. Cash, Lisa L. Winders, Jack L. Johnson
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Patent number: 11626259Abstract: A membrane circuit structure having a plurality of switch regions includes first, second and third membranes and a spacer layer. The second membrane is beneath the first membrane, and a lower surface of the second membrane is provided with a conductive pattern in at least one of the switch regions. The spacer layer is disposed between the first and second membranes. The third membrane is beneath the second membrane, and an upper surface of the third membrane is provided with first and second trigger portions separated from each other in the at least one of the switch regions, and the conductive pattern is able to be in contact with the first and second trigger portions, so that the first and second trigger portions are able to be electrically connected to each other through the conductive pattern.Type: GrantFiled: March 24, 2022Date of Patent: April 11, 2023Assignee: PRIMAX ELECTRONICS LTD.Inventors: Lei-Lung Tsai, Sheng-Fan Chang, Chin-Sung Pan
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Patent number: 11625134Abstract: A touch sensing unit includes a base substrate, touch sensing lines disposed on the base substrate, a first touch insulating layer disposed on the touch sensing lines, and touch electrodes disposed on the first touch insulating layer. The touch electrodes overlap the touch sensing lines in a thickness direction. Each of the touch electrodes has a mesh shape including a body and mesh holes. The bodies do not overlap the touch sensing lines in the thickness direction in a remaining area, except for partial areas.Type: GrantFiled: August 9, 2021Date of Patent: April 11, 2023Assignee: Samsung Display Co., Ltd.Inventors: Ji Hoon Kim, Sang Hun Park
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Patent number: 11617264Abstract: An interconnect substrate includes a first insulating layer, an interconnect layer formed on a first surface of the first insulating layer, and a second insulating layer formed on the first surface of the first insulating layer to cover the interconnect layer, wherein the second insulating layer includes a first resin layer and a second resin layer, the first resin layer covering at least part of a surface of the interconnect layer exposed outside the first insulating layer, the second resin layer covering the first resin layer, wherein both the first resin layer and the second resin layer contain a resin and a filler, and wherein a proportion of the resin in the first resin layer per unit area is higher than a proportion of the resin in the second resin layer per unit area.Type: GrantFiled: September 17, 2021Date of Patent: March 28, 2023Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Yuji Yukiiri
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Patent number: 11603427Abstract: The present application relates to a composition, a battery module and a battery pack. According to one example of the present application, the related manufacturing process can be improved and a battery module having excellent insulation can be provided.Type: GrantFiled: March 19, 2019Date of Patent: March 14, 2023Inventors: Yoon Gyung Cho, Se Woo Yang, Yang Gu Kang, Eun Suk Park, Hyun Suk Kim, Hyoung Sook Park, Sang Min Park, Young Jo Yang
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Patent number: 11602046Abstract: A wiring board according to the present disclosure includes a core board including an upper surface, a lower surface, a through-hole penetrating from the upper surface to the lower surface, and a plurality of glass fibers located inside, and a through-hole conductor located in the through-hole. The through-hole conductor includes a first portion located on an inner wall of the through-hole, and second portions connected to the first portion and located inside the glass fibers. The second portions include portions in a first direction and a second direction intersecting the first direction in a planar direction of the core board, the portions having a shorter length in the planar direction from the inner wall of the through-hole than portions, of the second portions, in directions other than the first direction and the second direction.Type: GrantFiled: May 6, 2021Date of Patent: March 7, 2023Assignee: KYOCERA CorporationInventor: Hiroshi Takeuchi
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Patent number: 11599047Abstract: An image forming apparatus includes an image forming device, a fixing device, a high voltage power supply board, a main body housing and a door. The door is provided in the main body housing so as to face the fixing device. The fixing device includes a fixing member, a pressure roller, a charge applying device, a fixing housing and a contact member. The fixing member is rotatable. The charge applying device is applied with a voltage from the high voltage power supply board and applies a charge to the fixing member. The fixing housing stores the fixing member, the pressure roller and the charge applying device. The contact member is provided in the fixing housing at a position accessible by opening the door and to which a feed line on the high voltage power supply board side and a feed line on the charge applying device side are connected.Type: GrantFiled: September 29, 2021Date of Patent: March 7, 2023Assignee: KYOCERA Document Solutions Inc.Inventor: Shota Onishi
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Patent number: 11594480Abstract: A circuit assembly may include a substrate and a pattern of contact points formed from deformable conductive material supported by the substrate. The assembly may further include an electric component supported by the substrate and having terminals arranged in a pattern corresponding to the pattern of contacts points. The one or more of the terminals of the electric component may contact one or more of the corresponding contact points to form one or more electrical connections between the electric component and the contact points.Type: GrantFiled: August 5, 2021Date of Patent: February 28, 2023Assignee: Liquid Wire Inc.Inventors: Mark William Ronay, Trevor Antonio Rivera, Michael Adventure Hopkins, Edward Martin Godshalk, Charles J. Kinzel
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Patent number: 11594479Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, conductive joints, conductive terminals, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first side and a second side opposite to the first side, wherein trenches are located on the second side of the redistribution structure and extend to an edge of the second side of the redistribution structure. The conductive joints are disposed over the first side of the redistribution structure. The conductive terminals are disposed over the second side of the redistribution structure. The circuit substrate electrically coupled to the redistribution structure through the conductive joints. The insulating encapsulation is disposed on the first side of the redistribution structure to cover the circuit substrate.Type: GrantFiled: June 18, 2021Date of Patent: February 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Lin Ho, Chin-Liang Chen, Pei-Rong Ni, Chia-Min Lin, Yu-Min Liang, Jiun-Yi Wu
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Patent number: 11588003Abstract: A flexible display apparatus includes a flexible substrate having an active area and an inactive area, the inactive area including a first area adjacent to the active area, a second area in which a pad is disposed, and a bending area disposed between the first area and the second area, wherein a plurality of wirings extending from the second area to the first area are disposed in the bending area, and at least one dummy pattern is in between the plurality of wirings.Type: GrantFiled: December 4, 2020Date of Patent: February 21, 2023Assignee: LG DISPLAY CO., LTD.Inventors: SeokYoung Lee, JuWon Sun, JeongHwan Park
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Patent number: 11581233Abstract: A semiconductor device has an electronic component assembly with a substrate and a plurality of electrical components disposed over the substrate. A conductive post is formed over the substrate. A molding compound sheet is disposed over the electrical component assembly. A carrier including a first electrical circuit pattern is disposed over the molding compound sheet. The carrier is pressed against the molding compound sheet to dispose a first encapsulant over and around the electrical component assembly and embed the first electrical circuit pattern in the first encapsulant. A shielding layer can be formed over the electrical components assembly. The carrier is removed to expose the first electrical circuit pattern. A second encapsulant is deposited over the first encapsulant and the first electrical circuit pattern. A second electrical circuit pattern is formed over the second encapsulant. A semiconductor package is disposed over the first electrical circuit pattern.Type: GrantFiled: May 4, 2021Date of Patent: February 14, 2023Assignee: STATS ChipPAC Pte. Ltd.Inventors: JinHee Jung, ChangOh Kim
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Patent number: 11574982Abstract: A slit has ends each close to one of a display area and a terminal. The ends are each formed of a stepwise side face, including etch stop films.Type: GrantFiled: January 31, 2018Date of Patent: February 7, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Ryosuke Gunji, Hiroki Taniyama, Shinji Ichikawa, Takeshi Yaneda, Hiroharu Jinmura, Yoshihiro Nakada, Akira Inoue
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Patent number: 11570894Abstract: A system of circuit card components each include through-holes for soldering having recessed copper layers for thermal insulation. Thermal insulation prevents heat conduction away from flowing solder, allowing the solder to flow freely through the through-hole. Even high-temperature, lead-free solders may maintain the necessary temperature to flow. Different circuit layers include specialized features based on distance from a top or bottom surface. Vias surrounding the through-hole maintain the necessary cross-sectional area for electrical connectivity.Type: GrantFiled: May 13, 2021Date of Patent: January 31, 2023Assignee: Rockwell Collins, Inc.Inventors: James B. Mayfield, Robert P. Campbell, Jeffrey J. Deloy, John A. Bauer
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Patent number: 11564313Abstract: A wiring body includes: a core insulating base material having a first main surface and a second main surface; a signal line and a first power supply line provided on the first main surface; a second power supply line provided on the second main surface and electrically connected to the first power supply line; a first dielectric layer laminated on the first main surface so as to embed the signal line and the first power supply line; a first ground layer provided on the first dielectric layer; a second dielectric layer laminated on the second main surface so as to embed the second power supply line; and a second ground layer provided on the second dielectric layer and sandwiching at least the signal line together with the first ground layer.Type: GrantFiled: May 17, 2021Date of Patent: January 24, 2023Assignee: NIPPON MEKTRON, LTD.Inventor: Fumihiko Matsuda
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Patent number: 11558961Abstract: A printed circuit board includes a first insulating layer having a through hole, and a via disposed to fill the through hole and to be extended to at least one surface of the first insulating layer, wherein the via includes a plating layer having an inner wall part disposed on an inner wall of the through hole and a land part extended from the inner wall part and disposed on the at least one surface of the first insulating layer, and a metal paste layer including metal particles, and filled in the rest of the through hole and disposed on the plating layer.Type: GrantFiled: October 24, 2019Date of Patent: January 17, 2023Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jungwoo Choi, Tae-hong Min
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Patent number: 11538764Abstract: A flexible device includes: (1) a flexible substrate; and (2) an interconnect disposed over the flexible substrate, wherein the interconnect has a varying vertical displacement along its length, relative to a top surface of the flexible substrate.Type: GrantFiled: January 30, 2019Date of Patent: December 27, 2022Assignee: The Regents of the University of CaliforniaInventors: Subramanian S. Iyer, Arsalan Alam, Amir Hanna, Takafumi Fukushima
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Patent number: 11540386Abstract: Provided is a method for manufacturing a flexible film. The method for the manufacturing the flexible film includes providing a parent film on which a plurality of film areas are defined, each of which having a detection pattern formed thereon, applying a voltage to each of the film areas to detect whether a defect exists, removing the detection pattern from respective ones of the film areas on which the defect is detected, and cutting out others of the film areas on which the defect is not detected.Type: GrantFiled: June 24, 2019Date of Patent: December 27, 2022Assignee: Samsung Display Co., Ltd.Inventors: Boyeon Kim, Myeongsu Kim, Sanghyun Lee
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Patent number: 11521946Abstract: In an embodiment a method for producing a semiconductor component comprising at least one semiconductor chip mounted on a surface, wherein the semiconductor chip is fixed on the surface by applying a solder compound to an assembling surface of the semiconductor chip, applying a metallic adhesive layer to a side of the solder compound facing away from the assembling surface, preheating the surface to a first temperature T1, bringing the metallic adhesive layer into mechanical contact in a solid state with the preheated surface, the metallic adhesive layer at least partially melting while it is brought into mechanical contact with the preheated surface, and subsequently cooling the surface to room temperature, the semiconductor chip being at least partially metallurgically bonded to the surface, and wherein the semiconductor chip is subsequently soldered to the surface to form a resulting solder connection.Type: GrantFiled: June 3, 2019Date of Patent: December 6, 2022Assignee: OSRAM OLED GMBHInventors: Klaus Müller, Holger Klassen, Matthias Hofmann
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Patent number: 11516916Abstract: A storage drive, including: a main module, including: a main printed circuit board (PCB) having a first side positioned opposite to a second side; flash memory components positioned on the main PCB at a first end of the storage drive, a controller module positioned on the main PCB at a second end of the storage drive opposite to the first end; and a capacitor module, including: a module printed circuit board (PCB) having a first side positioned opposite to a second side; a plurality of capacitors positioned on the module PCB on the first side of the module PCB, wherein the capacitor module is coupled to the main module such that the capacitor module is positioned at the first end of the storage drive and the first side of the capacitor module faces the first side of the main module.Type: GrantFiled: October 11, 2021Date of Patent: November 29, 2022Assignee: Dell Products L.P.Inventors: Kunzheng Zhang, Sandburg Hao Hu, Qianwen Bian
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Patent number: 11490506Abstract: One embodiment provides a printed circuit board (PCB). The PCB can include one or more metal layers and at least a pair of differential transmission lines. The pair of differential transmission lines can include a first transmission line and a second transmission line. The first transmission line can include a plurality of timing-skew-compensation structures, and a respective timing-skew-compensation structure of the first transmission line or a corresponding segment of the second transmission line adjacent to the timing-skew-compensation structure has a non-uniform width.Type: GrantFiled: May 21, 2020Date of Patent: November 1, 2022Assignee: Hewlett Packard Enterprise Development LPInventors: Hyunjun Kim, Andrew J. Becker, Paul Taylor Wildes, Gregory E. Scott
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Patent number: 11490511Abstract: A circuit board according to the present disclosure includes a substrate that is composed of a ceramic(s), and an electrically conductive layer that is positioned in contact with the substrate. The substrate includes a groove around the electrically conductive layer. Furthermore, an electronic device according to the present disclosure includes a circuit board with a configuration as described above, and an electronic component that is positioned on the electrically conductive layer.Type: GrantFiled: June 27, 2019Date of Patent: November 1, 2022Assignee: KYOCERA CorporationInventor: Yuichi Abe
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Patent number: 11483924Abstract: A substrate support structure includes: a substrate support including: a support body; and a protrusion including a base portion and a leading-end portion, the protrusion protruding from the support body; and a substrate having: a substrate body; a through hole provided at the substrate body; and a protruded portion surrounding the through hole, the protruded portion protruding from a first face of the substrate body, in which the base portion of the protrusion passes through the through hole, and the leading-end portion protrudes from the first face of the substrate body inside the protruded portion and engages with the substrate body such that the through hole is covered.Type: GrantFiled: May 12, 2021Date of Patent: October 25, 2022Assignee: YAZAKI CORPORATIONInventors: Keitaroh Nozawa, Hidehiko Shimizu, Shinji Kawai
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Patent number: 11469529Abstract: An electrical connector pin having a link segment for linking to the connector and an end segment that is free, the end segment having a cross-section that is flat and being provided with a slot passing through the end segment in its thickness direction and extending over a length of the free end segment to form two mutually parallel blades, each having a first edge that is straight beside the slot and a second edge extending remotely from the slot and that is provided with a contact portion projecting laterally relative to an outside surface of the link segment, the blades being elastically deformable transversely so as to vary the width of the slot. A connector and an electronic device including such a pin.Type: GrantFiled: September 13, 2019Date of Patent: October 11, 2022Assignee: SAFRAN ELECTRONICS & DEFENSEInventors: François Guillot, Pascal Spoor, Olivier Roche
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Patent number: 11450639Abstract: A semiconductor device comprises a semiconductor die, comprising a stacking structure, a first bonding pad with a first bonding surface positioned away from the stack structure, and a second bonding pad; a carrier comprising a connecting surface; a third bonding pad which comprises a second bonding surface and is arranged on the connecting surface, and a fourth bonding pad arranged on the connecting surface of the carrier; and a conductive connecting layer comprising a first conductive part, comprising a first outer contour, and formed between and directly contacting the first bonding pad and the third bonding pad; a second conductive part formed between the second bonding pad and the fourth bonding pad; and a blocking part covering the first conductive part to form a covering area, wherein the first bonding surface comprises a first position which is the closest to the carrier within the covering area and a second position which is the farthest from the carrier within the covering area in a cross section vieType: GrantFiled: February 1, 2021Date of Patent: September 20, 2022Assignee: EPISTAR CORPORATIONInventors: Shih-An Liao, Shau-Yi Chen, Ming-Chi Hsu, Chun-Hung Liu, Min-Hsun Hsieh
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Patent number: 11434462Abstract: Incubators are disclosed which include an enclosure with an internal chamber configured to support a cell culture plate and provide an environment suitable for maintaining and/or culturing biological cells. The enclosure can include one or more openings configured to allow access to the cell culture plate. The incubators can further include a structure having a plurality of openings configured to be aligned with a corresponding plurality of wells in the cell culture plate, and a sealing element configured to moveably seal the plurality of openings in the structure. The sealing element can comprise a plurality of openings corresponding to at least a subset of the plurality of openings of the structure. Access to the internal chamber can be provided by aligning the plurality of openings in the sealing element with the plurality of openings in the structure. Methods for using the incubators are also provided.Type: GrantFiled: May 31, 2019Date of Patent: September 6, 2022Assignee: Berkeley Lights, Inc.Inventors: Darcy K. Kelly-Greene, Russell A. Newstrom, Andrew W. McFarland, J. Tanner Nevill, Gang F. Wang
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Patent number: 11432403Abstract: A printed circuit board includes: a first insulating substrate having a mounting hole that penetrates through the first insulating substrate from a first surface to a second surface; a second insulating substrate including a connection portion; a first electrode provided on the second surface and disposed at an edge of the mounting hole; a second electrode provided on the connection portion and joined to the first electrode; and an electronic component provided on the second surface. A center of mass of the second insulating substrate is disposed on the first surface of the first insulating substrate. A center of mass of the electronic component is disposed on the second surface of the first insulating substrate. The electronic component has a weight equivalent to a weight of the second insulating substrate.Type: GrantFiled: February 13, 2019Date of Patent: August 30, 2022Assignee: Mitsubishi Electric CorporationInventors: Yoshiko Fujima, Toshiki Asai, Yusuke Morimoto, Kohei Sato, Shunsuke Sasaki
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Patent number: 11430737Abstract: Provided is a printed circuit board including a laminate that is formed by vertically stacking a plurality of insulating layers including a rigid insulating layer, a flexible insulating layer having a first region in vertical contact with at least one of the plurality of insulating layers and a second region located on an outer side of the laminate, and a first electronic element embedded in the flexible insulating layer.Type: GrantFiled: August 12, 2019Date of Patent: August 30, 2022Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Ho-Hyung Ham, Sa-Yong Lee, Ju-Ho Kim
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Patent number: 11419215Abstract: A module includes a wiring board having a first main surface, a first component mounted on the first main surface and having a first height H1, a second component mounted on the first main surface and having a second height H2 lower than the first height H1, and a sealing resin arranged so as to cover the first component and the second component while covering the first main surface. Compared to a first connection terminal used for connection between the first component and the first main surface, a second connection terminal used for connection between the second component and the first main surface has a higher height. A surface of the first component on a side far from the first main surface and a surface of the second component on a side far from the first main surface are exposed from the sealing resin.Type: GrantFiled: January 12, 2021Date of Patent: August 16, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yoshihito Otsubo, Kyo Shin
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Patent number: 11402961Abstract: A conductive member has a wiring portion, and the wiring portion has a wiring pattern in which straight line wirings each being composed of a plurality of thin metal wires arranged in parallel in one direction are overlapped in two or more directions. The wiring pattern is a separate-direction non-equal pitch wiring pattern in which the average pitch of the straight line wiring in at least one direction is different from the average pitch of the straight line wiring in at least one different direction. The conductive member has a wiring pattern having less moiré than an equal pitch wiring pattern, particularly a wiring pattern capable of reducing both regular moiré and irregular moiré (noise). A conductive film, a display device, and a touch panel each include the conductive member.Type: GrantFiled: September 25, 2020Date of Patent: August 2, 2022Assignee: FUJIFILM CorporationInventors: Kimito Katsuyama, Masaya Nakayama
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Patent number: 11404805Abstract: A device is provided that allows for repeated electrical connection of an integrated circuit. The device includes a top, an alignment plate, a connector and a bottom. The top, alignment plate, connector and bottom each have first and second sides facing opposite directions, with the top, alignment plate, connector and bottom being stacked in a vertical orientation. The top is vertically moveable relative to the alignment plate to secure the integrated circuit adjacent to an edge of the connector, with the edge extending from a space between the first and second sides thereof.Type: GrantFiled: October 19, 2020Date of Patent: August 2, 2022Assignee: The Research Foundation for The State University of New YorkInventors: Anatoliy Borodin, Yuri Polyakov
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Patent number: 11394154Abstract: A connection device for interconnecting electrical components that uses a plurality of contact layers. Each of the contact layers includes a substrate of dielectric material with a top edge, a bottom edge and side surfaces. A plurality of conductive elements extends in parallel through the dielectric material. The various contact layers are stacked. The side surfaces of the contact layers interconnect through a matrix of connective pillars. The connective pillars provide a network of open spaces between each of the contact layers. When the overall connection device is compressed, the dielectric material compresses and widens. The open areas receive the deformation and prevent the deformations from propagating lateral forces that can act to displace the conducive elements.Type: GrantFiled: March 9, 2022Date of Patent: July 19, 2022Inventor: Jeffrey G. Buchoff
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Patent number: 11388822Abstract: Methods for forming circuit boards and circuit boards using an adhesion layer are described. A substrate with two surfaces is exposed to a bifunctional organic compound to form an adhesion layer on the first substrate surface. A resin layer is then deposited on the adhesion layer and the exposed substrate surfaces. Portions of the resin layer may be removed to expose metal pads for contacts.Type: GrantFiled: August 28, 2020Date of Patent: July 12, 2022Assignee: Applied Materials, Inc.Inventors: Tapash Chakraborty, Steven Verhaverbeke, Han-Wen Chen, Chintan Buch, Prerna Goradia, Giback Park, Kyuil Cho
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Patent number: 11374036Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a substrate; an array layer, wherein the array layer includes a conductive pad and a conductive electrode disposed on the substrate; and a scratch prevention layer disposed on a side of the array layer away from the substrate, wherein the scratch prevention layer includes a first hollowed region and a second hollowed region, the first hollowed region corresponds to the conductive pad, and the second hollowed region corresponds to the conductive electrode.Type: GrantFiled: July 3, 2020Date of Patent: June 28, 2022Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventors: Jia Li, Junling Liu
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Patent number: 11373925Abstract: A silver-indium transient liquid phase method of bonding a semiconductor device and a heat-spreading mount, and a semiconductor structure having a silver-indium transient liquid phase bonding joint are provided. With the ultra-thin silver-indium transient liquid phase bonding joint formed between the semiconductor device and the heat-spreading mount, its thermal resistance can be minimized to achieve a high thermal conductivity. Therefore, the heat spreading capability of the heat-spreading mount can be fully realized, leading to an optimal performance of the high power electronics and photonics devices.Type: GrantFiled: May 7, 2019Date of Patent: June 28, 2022Assignee: LIGHT-MED (USA), INC.Inventors: Yongjun Huo, Chin Chung Lee
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Patent number: 11369024Abstract: In a method for producing a wiring circuit board, a conductive pattern is formed using a plating resist formed by photolithography for sequentially moving one photomask in a first direction with respect to a dry film resist to be exposed a plurality of times. The conductive pattern has a conductive intermediate portion which is inclined. The one photomask has a third photo pattern. The third photo pattern includes a first photoline pattern and a second photo line pattern. A first portion of the first photoline pattern coincides with a second portion of the second photoline pattern when projected in the first direction.Type: GrantFiled: November 5, 2020Date of Patent: June 21, 2022Assignee: NITTO DENKO CORPORATIONInventors: Takahiro Takano, Kazushi Ichikawa
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Patent number: 11363714Abstract: A printed wiring board includes a base insulating layer, a conductor layer formed on the base insulating layer and including conductor pads, an underlayer formed on one of the conductor pads of the conductor layer and including a metal different from a metal of the conductor layer, a solder resist layer formed on the base insulating layer such that the solder resist layer is covering the conductor layer and has openings exposing the conductor pads, respectively, and a bump formed directly on a first conductor pad of the conductor pads and including a base plating layer formed in a first opening of the openings and a top plating layer formed on the base plating layer such that a metal of the base plating layer is same as the metal of the conductor layer.Type: GrantFiled: September 24, 2020Date of Patent: June 14, 2022Assignee: IBIDEN CO., LTD.Inventors: Akinori Yoshida, Katsuhiko Tanno
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Patent number: 11355469Abstract: One aspect of the invention is a method of manufacturing a connection structure, including disposing an adhesive layer between a first electronic member including a first substrate and a first electrode formed on the first substrate and a second electronic member including a second substrate and a second electrode formed on the second substrate, and pressure-bonding the first electronic member and the second electronic member via the adhesive layer such that the first electrode and the second electrode are electrically connected to each other, wherein the first electronic member further including an insulating layer formed on a side of the first electrode opposite to the first substrate, and the adhesive layer including: a first conductive particle being a dendritic conductive particle; and a second conductive particle being a conductive particle other than the first conductive particle and having a non-conductive core and a conductive layer provided on the core.Type: GrantFiled: December 27, 2018Date of Patent: June 7, 2022Assignee: Showa Denko Materials Co., Ltd.Inventors: Tetsuyuki Shirakawa, Takahiro Fukui, Shinnosuke Iwamoto
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Patent number: 11342248Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. Where a solder resist coating is provided, a dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, is provided between the solder resist coating and underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal.Type: GrantFiled: July 14, 2020Date of Patent: May 24, 2022Assignee: GaN Systems Inc.Inventors: Cameron Mcknight-Macneil, Greg P. Klowak
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Patent number: 11336155Abstract: To improve the EMC performance of an electronic device on which a motor is mounted.Type: GrantFiled: June 29, 2018Date of Patent: May 17, 2022Assignee: MINEBEA MITSUMI Inc.Inventors: Toshiaki Seima, Koichi Tamai, Haruomi Morohashi, Kazuaki Saito
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Patent number: 11335223Abstract: A display panel and a display device are provided. The display panel includes a driving chip and an electrostatic protection module including a plurality of adjustment units. The adjustment units correspond to at least a part of connection lines, and the electrostatic protection module is configured to adjust a current value on the connection lines when an absolute value of an actual voltage on the connection lines is greater than a preset voltage to prevent damage to the connection lines.Type: GrantFiled: May 22, 2019Date of Patent: May 17, 2022Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventor: Gonghua Zou
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Patent number: 11322428Abstract: A semiconductor device package includes a substrate, a first semiconductor die, a conductive via, a first contact pad and a second contact pad. The substrate includes a first surface, and a second surface opposite to the first surface, the substrate defines a cavity through the substrate. The first semiconductor die is disposed in the cavity, wherein the first semiconductor die includes an active surface adjacent to the first surface, and an inactive surface. The conductive via penetrates through the substrate. The first contact pad is exposed from the active surface of the first semiconductor die and adjacent to the first surface of the substrate. The second contact pad is disposed on the first surface of the substrate, wherein the second contact pad is connected to a first end of the conductive via.Type: GrantFiled: December 2, 2019Date of Patent: May 3, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: You-Lung Yen, Bernd Karl Appelt
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Patent number: 11324118Abstract: A circuit board includes a plurality of signal contact pads each electrically contacting a contact point of one of a plurality of signal terminals and a non-conductive through hole extending through the circuit board in an interval area between a pair of adjacent signal contact pads of the plurality of signal contact pads.Type: GrantFiled: June 17, 2020Date of Patent: May 3, 2022Assignee: Tyco Electronics (Shanghai) Co. Ltd.Inventor: Peng Wei
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Patent number: 11291124Abstract: A method for manufacturing a multilayer wiring board is disclosed. The Method comprises a step (I) of preparing printed wiring boards having both electrical connection pads for establishing an electrical connection between the boards and non-connection pads for not establishing an electrical connection between the boards on the same plane; and a lamination step (II) of overlaying the boards so that the electrical connection pads face each other, and laminating the boards so that the boards are bonded to each other through a conductive material provided between the facing electrical connection pads. In the step (I), to at least one of surfaces faced when the boards are overlaid in the step (II), an insulating film having through holes formed in positions corresponding to the electrical connection pads on the surface is attached (Ia), and the conductive material is provided in the through holes (Ib).Type: GrantFiled: June 5, 2017Date of Patent: March 29, 2022Assignee: Lincstech Co., Ltd.Inventors: Yuto Tanabe, Eiichi Shinada, Masahiro Kato
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Patent number: 11277910Abstract: A wiring substrate includes a multilayer core substrate including a core layer, core conductor layers, and core insulating layers, a first laminate formed on first surface of the substrate and including insulating layers and conductor layers such that each insulating layer includes resin without reinforcing material, and a second laminate formed on second surface of the substrate and including insulating layers and conductor layers such that each insulating layer includes resin without reinforcing material.Type: GrantFiled: July 29, 2020Date of Patent: March 15, 2022Assignee: IBIDEN CO., LTD.Inventors: Shigemitsu Kunikane, Tomoyuki Ikeda
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Patent number: 11277907Abstract: A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, and a partially exposed layer in a central region of the stack being exposed with regard to an upper side and a lower side by a respective blind hole formed in the stack, wherein each of opposing main surfaces of the exposed layer is partially covered by a respective adhesive layer.Type: GrantFiled: October 20, 2020Date of Patent: March 15, 2022Assignee: AT&S Austria Technologie & Systemtechnik AktiengesellschaftInventors: Markus Leitgeb, Bernhard Reitmaier
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Patent number: 11270989Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.Type: GrantFiled: September 12, 2019Date of Patent: March 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen
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Patent number: 11261529Abstract: A method for fabricating a metallic wire mesh touch sensor with reduced visibility. A metallic wire mesh is formed on a transparent substrate such that the surface of the metallic wires is roughened or textured, so as to cause high scattering of incident light, thereby minimizing specularly reflected light towards the user. The metal lines are formed over patterned catalytic photoresist. The rough or textured surface of the metallic wires is achieved by roughening or texturing the catalytic photoresist, by selecting parameters of electronless plating of copper, or both. An RMS surface roughness of about 50 nm would scatter approximately 70% of incident cyan light incident at 30°.Type: GrantFiled: March 31, 2020Date of Patent: March 1, 2022Assignee: FUTURETECH CAPITAL, INC.Inventors: Robert Routh, Michael Morrione, Jeffrey Hawthorne
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Patent number: 11266018Abstract: A printed wiring board includes a main substrate, a standing substrate, a first electrode portion, and a second electrode portion. The second electrode portion is connected to the first electrode portion with solder while a support portion is inserted in a slit. The first electrode portion is provided to reach the slit. The second electrode portion is disposed to span from a bottom surface to a height position higher than or equal to a midpoint between a top surface and the bottom surface.Type: GrantFiled: December 4, 2018Date of Patent: March 1, 2022Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Shunsuke Sasaki, Yusuke Morimoto
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Patent number: 11244883Abstract: A semiconductor device includes a wiring substrate including a first surface, a second surface opposite to the first surface, a first heat dissipation conductive pattern formed on the first surface, a second heat dissipation conductive pattern formed on the first surface, a first wiring formed on the first surface, and a second wiring formed on the first surface. The semiconductor device also includes a semiconductor chip disposed on the wiring substrate and including a third surface and a fourth surface opposite to the third surface. In plan view, the second wiring is adjacent to the first and second heat dissipation conductive patterns without intervening any wiring and any conductive pattern between the second wiring and the first and second heat dissipation conductive patterns.Type: GrantFiled: October 31, 2019Date of Patent: February 8, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hidenori Egawa
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Patent number: 11240915Abstract: A method for manufacturing a multilayer wiring board is disclosed. The method includes steps of preparing printed wiring boards having both electrical connection pads for establishing an electrical connection between the boards and non-connection pads for not establishing an electrical connection between the boards on the same plane, overlaying the boards so that the electrical connection pads face each other, and laminating the boards so that the boards are bonded to each other through a conductive paste provided between the facing electrical connection pads. To prepare the printed wiring boards, attach an insulating film to at least one of surfaces faced when the boards are overlaid in the overlaying, bore holes in the insulating film so that the electrical connection pads are exposed, and provide a conductive paste in the holes.Type: GrantFiled: June 5, 2017Date of Patent: February 1, 2022Assignee: Lincstech Co., Ltd.Inventors: Masahiro Kato, Eiichi Shinada, Yuto Tanabe