With Encapsulated Wire Patents (Class 174/251)
  • Patent number: 9374894
    Abstract: A micro-wire rib structure includes a substrate and a cured layer formed on or over the substrate, the cured layer having a cured-layer surface. A micro-channel is imprinted in the cured layer, the micro-channel having a micro-channel depth, a micro-channel bottom, first and second micro-channel sides, and one or more ribs having opposing rib sides and a rib top defining a rib height less than the micro-channel depth. Each rib is located between the first and second micro-channel sides and extends from the micro-channel bottom toward the cured-layer surface. A cured electrical conductor forming a micro-wire is formed in the micro-channel. The micro-wire extends continuously from the first micro-channel side, over the micro-channel bottom, the rib side(s) and rib top(s) to the second micro-channel side forming a continuous electrical conductor from the first micro-channel side to the second micro-channel side.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: June 21, 2016
    Assignee: EASTMAN KODAK COMPANY
    Inventors: Ronald Steven Cok, Mitchell Stewart Burberry
  • Patent number: 9343195
    Abstract: Certain pyridine-ketone compounds have been found to provide anticorrosion properties when incorporated into silver nanowire containing films. Such compounds may be incorporated into one or more silver nanowire containing layers or in one or more layers disposed adjacent to the silver nanowire containing layers.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: May 17, 2016
    Assignee: Carestream Health, Inc.
    Inventors: James B. Philip, Jr., Chaofeng Zou
  • Patent number: 9318435
    Abstract: A semiconductor apparatus has one or more semiconductor chips. The semiconductor apparatus may include a power supply pad; power lines disposed on one side of the power supply pad, and including a first power line and a second power line; and connection lines connecting the power supply pad and the power lines. The connection lines may include a plurality of first connection lines connecting the power supply pad and the first power line, and a plurality of second connection lines connecting the power supply pad and the second power line, and disposed between the first connection lines. One or more pair of adjacent first connection lines may have a connection part by which the pair of adjacent first connection lines are connected with each other.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: April 19, 2016
    Assignee: SK HYNIX INC.
    Inventors: Jae Hwan Kim, Won John Choi
  • Patent number: 9237683
    Abstract: A lightweight radio/Audio player for vehicular application includes a case and frontal interface formed of polymer based material molded to provide details to accept audio devices and radio receivers, as well as the circuit boards required for electrical control and display. The case and frontal interface are of composite structure, including an insert molded electrically conductive wire mesh screen that has been pre-formed to contour with the molding operation. The wire mesh provides shielding and grounding of the circuit boards via exposed wire mesh pads and adjacent ground clips.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: January 12, 2016
    Assignee: Delphi Technologies, Inc.
    Inventors: Vineet Gupta, Joseph K. Huntzinger, Michael G. Coady, Curtis Allen Stapert, Kevin Earl Meyer, Timothy D. Garner, Jeffrey T. Bell, Robert L. Vadas, Allen E. Oberlin
  • Patent number: 9055700
    Abstract: In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multi-layer coating.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: June 9, 2015
    Assignee: Semblant Limited
    Inventors: Mark Robson Humphries, Frank Ferdinandi, Rodney Edward Smith
  • Publication number: 20150144379
    Abstract: A method produces a multilayer element with a substrate and at least one conductor structure connected in an areal manner to the substrate, which has first regions of electrically conductive material, which is present in accordance with a prescribed pattern, while electrically non-conductive second regions lie between the first regions.
    Type: Application
    Filed: May 27, 2013
    Publication date: May 28, 2015
    Applicant: 3D- Micromac AG
    Inventors: Tino Petsch, Maurice Clair, Alexander Böhm, Martin Sachse
  • Patent number: 9040832
    Abstract: A method of manufacturing a wiring substrate, includes obtaining a laminated body in which a first copper tin alloy layer and a copper layer are arranged in sequence on a first coupling agent layer, on a first insulating resin layer, forming a seed layer on the copper layer, forming a plating resist in which an opening portion is provided on the seed layer, forming a metal plating layer in the opening portion of the plating resist by applying an electroplating that utilizes the seed layer as a plating power feeding path, removing the plating resist, and forming a first wiring layer on the first coupling agent layer by etching the seed layer, the copper layer, and the first copper tin alloy layer while using the metal plating layer as a mask.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: May 26, 2015
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yuichiro Shimizu, Ryo Fukasawa
  • Publication number: 20150136447
    Abstract: A multilayer wiring board has a strip structure comprising a core material in which a ground pattern is disposed on one side of an insulating layer and a strip line is disposed on the other side, a prepreg disposed on the strip line of the core material, and a ground pattern disposed on the prepreg. In this multilayer wiring board, the core material is formed with a high frequency-adaptive base material, and the prepreg is formed with a general-purpose material.
    Type: Application
    Filed: May 9, 2013
    Publication date: May 21, 2015
    Inventors: Masahiro Katou, Yasuyuki Koshikawa, Hiroshi Wada
  • Publication number: 20150136446
    Abstract: Embodiments of the invention provide a printed circuit board having a structure in which a plurality of insulating layers having a metal wiring formed on one surface thereof are stacked, wherein a metal layer is interposed in the insulating layers, in order to improve warpage property of the board.
    Type: Application
    Filed: March 14, 2014
    Publication date: May 21, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Joung Gul RYU, Sung Taek LIM, Mi Sun HWANG
  • Publication number: 20150138743
    Abstract: A substrate package includes a woven fabric having electrically non-conductive strands woven between electrically conductive strands including wire strands, co-axial strands, and/or an inductor pattern of strands. The package may be formed by an inexpensive and high throughput process that first weaves the non-conductive strands (e.g., glass) between the conductive strands to form a circuit board pattern of conductive strands in a woven fabric. Next, the woven fabric is impregnated with a resin material to form an impregnated fabric, which is then cured to form a cured fabric. The upper and lower surfaces of the cured fabric are subsequently planarized. Planarizing segments and exposes ends of the wire, co-axial, and inductor pattern strands. Since the conductive strands were formed integrally within the planarized woven fabric, the substrate has a high mechanical stability and provides conductor strand based electrical components built in situ in the substrate package.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 21, 2015
    Inventors: Mihir K. ROY, Mathew J. Manusharow
  • Publication number: 20150136448
    Abstract: According to one embodiment, a flexible printed wiring board includes a first conductor layer formed on the first surface of an insulation base, a second conductor layer formed on the second surface of the insulation base, a first insulation layer covering the first conductor layer, and a second insulation layer covering the second conductor layer. The first insulation layer has an opening formed in a position corresponding to a connecting terminal portion to expose the first conductor layer. A metal layer is provided in a region ranging from the connecting terminal portion to a bending presumed portion. The metal layer is positioned behind the opening between the second surface and the second insulation layer to avoid the first conductor layer.
    Type: Application
    Filed: August 13, 2014
    Publication date: May 21, 2015
    Inventor: Kazuyoshi Sasaki
  • Publication number: 20150136449
    Abstract: [Objective] To provide a multilayer wiring substrate in which, even when a core substrate is thinned, the core substrate can reliably accommodate a capacitor. [Means for Solution] A multilayer wiring substrate 10 includes a sheetlike capacitor element 101, a resin filler 92, and via conductors 43 and 47. A sheetlike capacitor element 101 has an element main-surface 102 and an element back-surface 103, is configured such that a dielectric layer 107 is sandwiched directly between a main-surface-side electrode layer 105 exposed at the element main-surface 102 side and a back-surface-side electrode layer 106 exposed at the element back-surface 103 side, and is accommodated at least partially in an accommodation hole 90 such that a core main-surface 12 and the element main-surface 102 face the same direction. A resin filler 92 is charged into a gap between the sheetlike capacitor element 101 and an inner wall surface 91 of the accommodation hole 90.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 21, 2015
    Inventors: Daisuke YAMASHITA, Teruyuki KOBAYASHI, Takuya TORII, Masahiro INOUE
  • Patent number: 9035193
    Abstract: A connecting member such as a terminal base is used in connection with a printed circuit board unit in which circuit elements such as a power module are mounted on a printed circuit board. The connecting member connects the circuit element of an electrical circuit including the printed circuit board, to an electrical wire. The connecting member includes a terminal connecting section to be directly connected to terminal pins of the circuit element; a wire connecting section to be connected to the electrical wire; and attachment sections for attaching the connecting member to the printed circuit board.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: May 19, 2015
    Assignee: DAIKIN INDUSTRIES, LTD.
    Inventors: Sumio Kagimura, Hiroshi Doumae, Hirotaka Doi, Shuuji Genda
  • Publication number: 20150129285
    Abstract: A packaging substrate having an embedded through-via interposer is provided, including an encapsulant layer, a through-via interposer embedded in the encapsulant layer and having a plurality of conductive through-vias therein, a redistribution layer embedded in the encapsulant layer and formed on the through-via interposer so as to electrically connect with first end surfaces of the conductive through-vias, and a built-up structure formed on the encapsulant layer and the through-via interposer for electrically connecting second end surfaces of the conductive through-vias.
    Type: Application
    Filed: January 22, 2015
    Publication date: May 14, 2015
    Inventors: Dyi-Chung Hu, Tzyy-Jang Tseng
  • Publication number: 20150131255
    Abstract: A semiconductor package may include: a substrate including a core layer having a first surface and a second surface which is opposite to the first surface, a wiring layer formed over the first and second surfaces and in an inside of the core layer, and having a first electrode disposed in the inside of the core layer and exposed from the core layer and a second electrode disposed over the first surface, and a passivation layer formed over the first and second surface of the core layer such that the first and the second electrodes are exposed; a first semiconductor chip disposed over the first surface of the core layer; a second semiconductor chip stacked over the first semiconductor chip; a first connection member for connecting the first semiconductor chip with the first electrode; and a second connection member for connecting the second semiconductor chip with the second electrode.
    Type: Application
    Filed: April 15, 2014
    Publication date: May 14, 2015
    Applicant: SK hynix Inc.
    Inventor: Eun Hye DO
  • Publication number: 20150131250
    Abstract: A method includes fabricating a printed circuit board. The fabricating includes forming at least one conductive layer on top a first dielectric layer. The fabricating includes forming a second dielectric layer on top of the at least one conductive layer. The fabricating includes forming a thermal pad on top of the second dielectric layer. The fabricating includes forming a first through hole through the thermal pad, the second dielectric layer, the at least one conductive layer, and the first dielectric layer. The fabricating includes filling the first through hole with a conductive material to form a plated through hole. The fabricating includes topdrilling the plated through hole to remove a top portion of the conductive material from a top of the plated through hole, wherein a bottom portion of the conductive material remains in the plated through hole after removal of the top portion.
    Type: Application
    Filed: November 13, 2013
    Publication date: May 14, 2015
    Applicant: International Business Machines Corporation
    Inventor: Phillip D. Isaacs
  • Publication number: 20150131246
    Abstract: A printed circuit board includes a first layer stack and a second layer stack coupled to the first layer stack. The first layer stack includes a first electrically-insulating layer, a first electrically-conductive layer, and a cut-out area defining a void that extends therethrough. The first electrically-insulating layer includes a first surface and an opposite second surface. The first electrically-conductive layer is disposed on the first surface of the first electrically-insulating layer. The second layer stack includes a second electrically-insulating layer. The second electrically-insulating layer includes a first surface and an opposite second surface. One or more electrically-conductive traces are disposed on the first surface of the second electrically-insulating layer. The printed circuit board further includes a device at least partially disposed within the cut-out area.
    Type: Application
    Filed: January 23, 2015
    Publication date: May 14, 2015
    Inventors: WAYNE L. MOUL, ROBERT J. BEHNKE, II, SCOTT E.M. FRUSHOUR, JEFFREY L. JENSEN
  • Publication number: 20150130060
    Abstract: A semiconductor package substrate includes an insulating substrate, a circuit pattern on the insulating substrate, a protective layer formed on the insulating substrate to cover the circuit pattern on the insulating substrate, a pad formed on the protective layer while protruding from a surface of the protective layer, and an adhesive member on the pad.
    Type: Application
    Filed: May 24, 2013
    Publication date: May 14, 2015
    Inventors: Sung Wuk Ryu, Dong Sun Kim, Seung Yul Shin
  • Publication number: 20150131249
    Abstract: A board for mechanically supporting and electrically connecting electronic components includes a non-conductive substrate, a plurality of electrically conductive traces and pads disposed on the non-conductive substrate, and a solder mask applied to the non-conductive substrate and covering the traces. Metal lines are disposed on the non-conductive substrate under the solder mask and along at least two sides of the pads disposed in corners of the non-conductive substrate, so that a metal line is interposed between the pads in the corners of the non-conductive substrate and each adjacent pad. The metal lines form a raised region in the solder mask along the metal lines which prevents solder bridging in the corners of the non-conductive substrate during solder reflow. A corresponding semiconductor package and semiconductor assembly with such solder bridging prevention structures are also provided.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 14, 2015
    Inventors: Carlo Baterna Marbella, Fabian Schnoy
  • Publication number: 20150129284
    Abstract: A printed circuit substrate may be configured with at least one internal lead designed and shaped to reduce solder bridging. The printed circuit substrate can have a plurality of internal leads that each has a continuously curvilinear boundary that defines an isolation channel. The isolation channel may be configured with a uniform distance that separates a first internal lead from an adjacent second internal lead.
    Type: Application
    Filed: November 11, 2013
    Publication date: May 14, 2015
    Applicant: Seagate Technology LLC
    Inventors: Prapan Aparimarn, Chaovalit Chiyatan, Piriyakorn Jirawattanakasem, Joompondej Bamrungwongtaree
  • Publication number: 20150122530
    Abstract: A printed wiring board includes a core substrate including a resin insulating layer and multiple conductor layers, a first wiring structure formed on a first surface of the core substrate and including a conductor layer and a resin insulating layer, and a second wiring structure formed on a second surface of the core substrate and including a conductor layer and a resin insulating layer. The core substrate is interposed between the first wiring structure and the second wiring structure such that the resin insulating layers and conductor layers in the core substrate, first wiring structure and second wiring structure are alternately laminated, the resin insulating layer in the first wiring structure has a vol % of resin which is larger than a vol % of resin in the resin insulating layer in the second wiring structure such that a difference in the vol % of resin in the first and second wiring structures is in the range of from 0.5% to 5.0%.
    Type: Application
    Filed: November 5, 2014
    Publication date: May 7, 2015
    Applicant: IBIDEN CO., LTD.
    Inventor: Naoki KATSUDA
  • Publication number: 20150123281
    Abstract: A semiconductor package substrate includes an insulating substrate; a circuit pattern on the insulating substrate; a protective layer on the insulating substrate, the protective layer covering the circuit pattern on the insulating substrate; a pad on the protective layer; and an adhesive member on the protective layer, wherein the pad includes a first pad buried in the protective layer, and a second pad on the first pad, the second pad protruding over the protective layer.
    Type: Application
    Filed: May 24, 2013
    Publication date: May 7, 2015
    Inventors: Sung Wuk Ryu, Dong Sun Kim, Seung Yul Shin
  • Publication number: 20150114690
    Abstract: A flex-rigid wiring board includes a flexible substrate, a non-flexible substrate positioned such that the non-flexible substrate is extending in horizontal direction of the flexible substrate, a first wiring layer on first surface sides of the flexible and non-flexible substrates, a second wiring layer on second surface sides of the flexible and non-flexible substrates, a first insulating layer covering the first sides of the flexible and non-flexible substrates and having an opening exposing a portion of the first side of the flexible substrate, and a second insulating layer covering the second sides of the flexible and non-flexible substrates and having an opening exposing a portion of the second side of the flexible substrate. The first wiring layer includes first conductor pattern on the first side of the flexible substrate, and the second wiring layer includes second conductor pattern extending across the second sides of the flexible and non-flexible substrates.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 30, 2015
    Applicant: IBIDEN Co., Ltd.
    Inventors: Teruyuki ISHIHARA, Michimasa Takahashi, Takashi Kariya
  • Publication number: 20150114687
    Abstract: Embodiments are directed to a method for manufacturing a smoke detector, comprising: manufacturing a substrate that comprises a guard ring configured to surround an ion chamber collector plate pin connection point, a surface mount component connection point, and a trace coupling the ion chamber collector plate pin connection point and the surface mount component connection point, and coupling a surface mount component to the substrate at the surface mount component connection point.
    Type: Application
    Filed: October 23, 2014
    Publication date: April 30, 2015
    Inventor: Matthew J. Buchholz
  • Publication number: 20150114689
    Abstract: A flex-rigid wiring board includes a flexible substrate, a non-flexible substrate positioned such that the non-flexible substrate is extending in horizontal direction of the flexible substrate, a first wiring layer formed on first surfaces of the flexible and non-flexible substrates, a second wiring layer embedded in second surfaces of the flexible and non-flexible substrates, a first insulating layer covering the first surfaces of the flexible and non-flexible substrates and having an opening exposing a portion of the first surface of the flexible substrate, and a second insulating layer covering the second surfaces of the flexible and non-flexible substrates and having an opening exposing a portion of the second surface of the flexible substrate. The first wiring layer includes non-embedded wirings on the first surfaces of the flexible and non-flexible substrates, and the second wiring layer includes embedded wirings in the second surfaces of the flexible and non-flexible substrates.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 30, 2015
    Applicant: IBIDEN Co., Ltd.
    Inventors: Teruyuki ISHIHARA, Michimasa TAKAHASHI, Takashi KARIYA
  • Publication number: 20150114688
    Abstract: Disclosed herein is a printed circuit board having an improved structure of a dummy part to improve warpage strength of the printed circuit board, the printed circuit board including: a plurality of insulating layers built-up therein, the plurality of insulating layers including copper clad layers; and a product zone and a dummy zone formed at a central part and along an edge part of the insulating layers, respectively, wherein the copper clad layers included in each insulating layer are arranged in the dummy zone at predetermined intervals in a longitudinal direction.
    Type: Application
    Filed: October 23, 2014
    Publication date: April 30, 2015
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Byung Ho KIM
  • Publication number: 20150115467
    Abstract: The inventive concepts provide package-on-package (PoP) devices. In the PoP devices, an interposer substrate and a thermal boundary material layer may be disposed between a lower semiconductor package and an upper semiconductor package to rapidly exhaust heat generated from a lower semiconductor chip included in the lower semiconductor package. The interposer substrate may be formed of one or more insulating layers, conductive vias, heat dissipating members, protection layers, and various conductive patterns.
    Type: Application
    Filed: August 11, 2014
    Publication date: April 30, 2015
    Inventors: Kyol PARK, JICHUL KIM, YUNHYEOK IM, Eon Soo JANG
  • Publication number: 20150114686
    Abstract: A printed circuit board includes a first dielectric layer, a first ground layer, a second dielectric layer, a first power layer, a first via hole, and a first ground hole. A first signal line is laid on the first dielectric layer. A third signal line is laid on the second dielectric layer. The first and third signal lines are electrically connected to the first via hole. An extending direction of the first signal line on the first dielectric layer is opposite to an extending direction of the third signal line is laid on the second dielectric layer. A first void area is defined in the first ground layer around the first via hole. A second void area is defined in the first power layer around the first via hole. The first ground hole is outside the first void area and the second void area.
    Type: Application
    Filed: October 16, 2014
    Publication date: April 30, 2015
    Inventors: FENG-HUA DENG, FENG ZHANG
  • Publication number: 20150114691
    Abstract: Disclosed herein are a core substrate and a method for manufacturing the same. According to a preferred embodiment of the present invention, a core substrate includes: a porous scaffold formed with a void; an insulating material formed to fill a void of the porous scaffold; and an electronic device embedded into the porous scaffold and the insulating material and having internal electrodes exposed on both surfaces thereof.
    Type: Application
    Filed: October 27, 2014
    Publication date: April 30, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Ho HONG, Sang Hyun Shin, Sa Yong Lee, Sung Han Kim, Keun Yong Lee
  • Publication number: 20150103269
    Abstract: Provided are a transparent conductive substrate production method for an electrostatic capacitance touch panel having a high pattern recognition property, by simple steps without using a vacuum process and a wet etching method, as well as a transparent conductive substrate and an electrostatic capacitance touch panel. An electrode drawing lead wiring pattern is formed on at least one main face of a transparent film using a conductive paste. An electrode pattern forming unit prints an electrode pattern with a transparent conductive pattern forming ink containing metal nanowires or metal nanoparticles so that the electrode pattern is connected to the electrode drawing lead wiring pattern, and dries the printed electrode pattern. The dried electrode pattern is subjected to pulsed light irradiation by a photoirradiation unit 18, to sinter the metal nanowires or the metal nanoparticles contained in the transparent conductive pattern forming ink.
    Type: Application
    Filed: April 26, 2013
    Publication date: April 16, 2015
    Applicants: SHOWA DENKO K.K., OSAKA UNIVERSITY
    Inventors: Katsuaki Suganuma, Hiroshi Uchida, Kenji Shinozaki
  • Publication number: 20150096788
    Abstract: A method for fabrication of a circuit board using the disclosed embodiments relies on a CAD model of a multilayer circuit board with conductive elements defined by layer. A first granular conductive material layer is introduced into a mold. A fusion process element traverses across the mold to fuse selected portions of the first granular conductive material layer forming first layer conductive elements. An additional granular conductive material layer is introduced into the mold over the fused selected portions of the first layer and unfused portions of the first layer. The fusion process element is then traversed across the mold to fuse selected portions of the additional granular conductive material layer forming an additional layer of conductive elements. Unfused granular conductive material is then purged from the fused first conductive elements and additional conductive layer elements.
    Type: Application
    Filed: October 7, 2013
    Publication date: April 9, 2015
    Applicant: The Boeing Company
    Inventor: Donald F. Wilkins
  • Publication number: 20150096789
    Abstract: The present invention relates to an electronic component embedded printed circuit board and a method for manufacturing the same. An electronic component embedded printed circuit board of the present invention includes a core having a cavity therein and internal circuit layers on upper and lower surfaces thereof; an electronic component inserted in the cavity and having an elastic body on an outer peripheral surface thereof; insulating layers laminated on the top and bottom of the core; external circuit layers patterned on the insulating layers; and vias formed in the insulating layers to electrically connect the internal circuit layers and the external circuit layers, wherein among the vias, the via in contact with the electronic component is connected through the elastic body.
    Type: Application
    Filed: May 8, 2014
    Publication date: April 9, 2015
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Moon Il KIM
  • Patent number: 9000302
    Abstract: A wiring board includes first insulating layers and second insulating layers formed on a core layer in this order; a third insulating layer and a solder resist layer formed on another surface of the core layer in this order, first wiring layers and second wiring layers formed in the first insulating layers and the second insulating layers, respectively, wherein a first end surface of the first via wiring exposes from the first surface of the outermost first insulating layer to be directly connected with an outermost second wiring layer, the first via wiring and the outermost second wiring layer being separately formed, the first surface of the outermost first insulating layer and the first end surface of the first via wiring are polished surfaces, smooth surfaces and are flush with each other, and the wiring density of the second wiring layers is higher than that of the first wiring layers.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: April 7, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Hitoshi Sakaguchi, Wataru Kaneda, Masato Tanaka, Akio Rokugawa
  • Publication number: 20150090478
    Abstract: A ceramic substrate comprises a plurality of ceramic sheets, a plurality of inner conductive layers, a plurality of vias, and an upper conductive layer. The ceramic sheets are stacked one on top of another and include a top ceramic sheet. The inner conductive layers include electrically conductive material that forms electrically conductive features on an upper surface of each ceramic sheet excluding the top ceramic sheet. The vias are formed in each of the ceramic sheets with each via being filled with electrically conductive material. The upper conductive layer includes electrically conductive material that forms electrically conductive features on an upper surface of the top ceramic sheet. The upper conductive layer is constructed from a stack of four sublayers. A first sublayer is formed from titanium. A second sublayer is formed from copper. A third sublayer is formed from platinum. A fourth sublayer is formed from gold.
    Type: Application
    Filed: September 30, 2014
    Publication date: April 2, 2015
    Inventors: Joseph Ambrose Wolf, Kenneth A. Peterson
  • Publication number: 20150091152
    Abstract: Disclosed herein are an external connection terminal, a semiconductor package having the external connection terminal, and a method of manufacturing the same. The external connection terminal includes an internal insulating material, an external insulating material formed to enclose the internal insulating material, and metal lines formed between the internal insulating material and the external insulating material.
    Type: Application
    Filed: September 19, 2014
    Publication date: April 2, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Eun Jung JO, Chang Seob HONG, Kyu Hwan OH, Kang Hyun LEE
  • Patent number: 8993894
    Abstract: A printed wiring board includes a core substrate having first and second surfaces, a first conductor formed on the first surface of the substrate, a second conductor formed on the second surface of the substrate, a first through-hole conductor formed through the substrate and connecting the first and second conductors, and a second through-hole conductor formed through the substrate and connecting the first and second conductors. The second through-hole conductor has a diameter which is greater than a diameter of the first through-hole conductor, the first through-hole conductor has a roughened inner wall forming an interior space, the second through-hole conductor has a roughened inner wall forming an interior space, and the roughened inner wall of the first through-hole conductor has an arithmetic average roughness which is set lower than an arithmetic average roughness of the roughened inner wall of the second through-hole conductor.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: March 31, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Hideyuki Kawai, Yoshinori Takenaka
  • Publication number: 20150083464
    Abstract: A process for manufacturing a transparent body for use in a touch screen panel is provided. The process includes: depositing a first transparent layer stack over a transparent substrate, wherein said first transparent layer stack includes at least a first dielectric film with a first refractive index, and a second dielectric film with a second refractive index different from the second the first refractive index; providing a structured transparent conductive film in a manner such that the first transparent layer stack and the transparent conductive film are disposed over the substrate in this order, and wherein the structured transparent conductive film has a sheet resistance of 100 Ohm/square or below; and providing a transparent adhesive onto the structured transparent conductive film configured for attaching the layer stack to the touch screen panel.
    Type: Application
    Filed: March 30, 2012
    Publication date: March 26, 2015
    Applicant: Applied Materials, Inc.
    Inventors: Thomas Werner Zilbauer, Jürgen Grillmayer
  • Publication number: 20150083465
    Abstract: A transparent or conductive substrate and its manufacturing method are provided. The transparent or conductive substrate comprises a base substrate capable of light transmission; a transparent electroconductive layer formed by depositing a transparent electroconductive material; and an anti-reflection layer, wherein the anti-reflection layer is formed by using a dry etching method and comprises a plurality of spine-type structures and an anti-reflection structure formed by depositing inorganic particles.
    Type: Application
    Filed: May 7, 2012
    Publication date: March 26, 2015
    Applicant: KOREA INSTITUTE OF MACHINERY & MATERIALS
    Inventors: Jung Heum Yun, Gun Hwan Lee, Yeon Hyun Park, Sung Hun Lee
  • Publication number: 20150085504
    Abstract: In one aspect, a circuit board includes a base board and a layer of an elastic material comprising a first surface and a second surface. The layer of elastic material is adhered to the base board via the first surface. The circuit board further includes an electrical trace disposed on the second surface of the layer of elastic material. At least a portion of the layer of elastic material stretches or shrinks when the base board expands or contracts. A method of manufacturing a circuit includes obtaining an aluminum board, obtaining a layer of an elastic material, and applying a layer of adhering material to a surface of the aluminum board. The method further includes disposing the layer of the elastic material onto the layer of adhering material, and adhering the layer of the elastic material onto the aluminum board via the layer of adhering material.
    Type: Application
    Filed: September 23, 2014
    Publication date: March 26, 2015
    Inventor: Ellis W. Patrick
  • Patent number: 8987602
    Abstract: A laminated multilayer electronic support structure comprising a dielectric with integral vias and feature layers and further comprising a planar metal core characterized by a thickness of less than 100 microns.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: March 24, 2015
    Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.
    Inventors: Dror Hurwitz, Alex Huang
  • Publication number: 20150075843
    Abstract: A multilayer wiring board includes a first metal foil wiring layer that has at least two or more layers of metal foil wiring lines and is arranged on a mounting surface side for mounting a surface mount type component, a wire wiring layer that is arranged on an opposite side of the mounting surface, and in which an insulation coating wire is wired, and a first interlayer conduction hole that has a conduction part which electrically connects the metal foil wiring line positioned on a surface of the first metal foil wiring layer to at least one of the metal foil wiring line in an inner layer of the first metal foil wiring layer and the insulation coating wire of the wire wiring layer. A hole diameter of the first interlayer conduction hole varies in a board thickness direction of the multilayer wiring board.
    Type: Application
    Filed: March 27, 2013
    Publication date: March 19, 2015
    Inventors: Hiroyuki Yamaguchi, Seiichi Kurihara, Hiroshi Sakurai, Shunsuke Nukina
  • Publication number: 20150075845
    Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. According to a preferred embodiment of the present invention, the printed circuit board includes: a base substrate; an inner layer build-up layer formed on the base substrate and including a first inner layer circuit layer, a second inner layer circuit layer, an inner layer insulating layer, and an inner layer via having a tapered section; and an outer layer build-up layer formed on the inner layer build-up layer and including an outer layer circuit layer, an outer layer insulating layer, and an outer layer via having a rectangular section.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 19, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Ki Young Yoo
  • Publication number: 20150075844
    Abstract: An array printed circuit board (PCB) is provided in which a defective single PCB may be easily replaced. A method of replacing a defective single PCB and a method of manufacturing an electronic apparatus are also provided. The array PCB may include a plurality of single PCBs. A rail portion may surround the single PCBs. A plurality of tab route portions connect the single PCBs to the rail portion, each of the tab route portions including at least one pair of via electrodes. A test terminal portion may be formed at one side of the rail portion and may include a plurality of test terminals. The at least one pair of via electrodes may include a first via electrode, arranged adjacent to the rail portion and electrically connected to a corresponding test terminal, and a second via electrode arranged adjacent to and electrically connected to a corresponding single PCB.
    Type: Application
    Filed: August 12, 2014
    Publication date: March 19, 2015
    Inventors: Young-hoon KIM, Hyun-seok CHOI, Joo-han LEE, Da-hye CHOE
  • Publication number: 20150077361
    Abstract: Provided are an electrode plate using an ITO, and an electrochromic plate, an electrochromic mirror and a display device using the electrode plate, the electrode plate including a transparent electrode layer, a metal mesh pattern on the transparent electrode layer, an insulating layer provided in a space defined by an upper surface of the transparent electrode layer and the metal mesh pattern and between metal components of the metal mesh pattern, and a base substrate on the metal mesh pattern and the insulating layer.
    Type: Application
    Filed: July 31, 2014
    Publication date: March 19, 2015
    Inventors: Young Dae SEO, Hyo Won SON, Joo Hyun HWANG
  • Patent number: 8981231
    Abstract: Provided is a molded product including a primary molded layer, a transfer layer that includes at least a decorating layer and a print layer for foil flow prevention including one of polyester, polyurethane, polyimide and cellulose, or a mixture obtained by combining two or more of polyester, polyurethane, polyimide and cellulose as a main component, and is transferred to a surface of the primary molded layer, the decorating layer and the print layer for foil flow prevention being arranged in increasing order of distance from a side of the primary molded layer, and a secondary molded layer formed on the side of the print layer for foil flow prevention of the transfer layer.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventor: Atsushi Seki
  • Patent number: 8981236
    Abstract: A printed circuit board includes a line intensive distribution area, a line sparse distribution area, a solder mask layer, and a signal layer. A first signal line is laid on the signal layer. The first signal line crosses the line intensive distribution area and the line sparse distribution area. The first signal line is narrower in the line intensive distribution area than in the line sparse distribution area. The solder mask layer is thicker in the line intensive distribution area than in the line sparse distribution area.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: March 17, 2015
    Assignees: Hong Fu Jin Precision Industry (WuHan) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventor: Feng Zhang
  • Publication number: 20150070434
    Abstract: A method of manufacturing a print element substrate, comprising preparing a substrate, including a first region and a second region, in which a printing portion is formed on the first region, and a wiring pattern connected to the printing portion is formed on the first region and the second region, forming an insulating film covering the printing portion and the wiring pattern, and forming a conductive cavitation-resistant film on the insulating film, wherein in the forming the insulating film, the insulating film is formed such that a side surface of a portion of the insulating film, which is formed on the second region, includes an inclined face.
    Type: Application
    Filed: August 21, 2014
    Publication date: March 12, 2015
    Inventors: Noriyuki Kurita, Keiichi Sasaki
  • Publication number: 20150068788
    Abstract: A printed wiring board includes a core insulation layer including a resin and having a via conductor through the core insulation layer, a first conductive layer formed on the core layer and including a copper foil and a plated film, an interlayer insulation layer formed on the first layer and including a resin, the interlayer layer having a via conductor through the interlayer layer, and a second conductive layer formed on the interlayer layer and including a copper foil and a plated film. The first layer includes a conductive circuit, the core and interlayer layers have dielectric constants of 4.0 or lower for signal transmission at frequency of 1 GHz and thermal expansion coefficient of 85 ppm/° C. or lower at or below Tg, and the foil of the first layer has thickness greater than thickness of the foil of the second layer.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 12, 2015
    Applicant: IBIDEN Co., Ltd.
    Inventors: Tetsuo AMANO, Toshio Nishiwaki
  • Publication number: 20150070599
    Abstract: For a substrate sheet having a transparent electrode made of an electroconductive polymer and metal wiring connecting this transparent electrode and a connector junction on a translucent base and provided with a protective layer covering the transparent electrode and the metal wiring, a substrate sheet is provided that has its transparent electrode protected and its metal wiring protected from corrosion. The protective layer was made up of a laminate having a sulfuration-resistant resist layer that prevents the metal wiring from being sulfurated and a lightfast resist layer that absorbs ultraviolet light stacked on the base, and the sulfuration-resistant resist layer was a polyurethane-polyurea-based plastic layer.
    Type: Application
    Filed: June 7, 2013
    Publication date: March 12, 2015
    Applicant: POLYMATECH JAPAN CO., LTD.
    Inventors: Shinichi Tomooka, Soyoko Nikki, Yutaka Nakanishi
  • Publication number: 20150060110
    Abstract: Methods for applying a hydrophobic coating to various components within a computing device are disclosed. More specifically, a hydrophobic coating can be applied by a plasma assisted chemical vapor deposition (PACVD) process to a fully assembled circuit board. Frequently, a fully assembled circuit board can have various components such as electromagnetic interference (EMI) shields which cover water sensitive electronics. A method is disclosed for perforating portions of the EMI shields that overlay the water sensitive electronics. Methods of sealing board to board connectors are also disclosed. In one embodiment solder leads of the board to board connectors can be covered by a silicone seal.
    Type: Application
    Filed: March 31, 2014
    Publication date: March 5, 2015
    Applicant: Apple Inc.
    Inventors: Nicholas G. MERZ, Scott A. MYERS, Gregory N. STEPHENS, Joseph C. POOLE