Abstract: A microstructure comprises a laminate structure having a first conductor, a second conductor, and an intervening insulator located between the first and the second conductors. The first conductor includes opposite faces in relation to the second conductor, side faces, and edge parts which form the boundaries of the aforementioned opposite faces and side faces. The second conductor includes an extended face extending beyond the edge parts exceeding the first conductor. The insulation film includes an area covering at least part of an edge part and/or at least part of a side face.

Abstract: A capacitor built-in substrate of the present invention includes; a base resin layer; a plurality of capacitors arranged side by side in a lateral direction in a state that the capacitors are passed through the base resin layer, each of the capacitors constructed by a first electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively such that the projection portion on one surface side of the base resin layer serves as a connection portion, a dielectric layer for covering the projection portion of the first electrode on other surface side of the base resin layer, and a second electrode for covering the dielectric layer; a through electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively; and a built-up wiring formed on the other surface side of the base resin layer and connected to the second electrodes of the capac

Abstract: A printed circuit board assembly includes: a substrate; a main signal line formed on the substrate to transmit a signal; an SMD mounted on the substrate; a pad interposed between the SMD and the substrate; and a sub signal line provided on the substrate to electrically connect the main signal line with the pad, and having a width different from that of the main signal line. Thus, the printed circuit board assembly transmits a signal at a high speed and enhancing reliability and an economical efficiency of a product using the printed circuit board assembly.

Abstract: A capacitor built-in interposer of the present invention, includes a base resin layer, a capacitor first electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively whereby the projection portion on one surface side of the base resin layer serves as a connection portion, a capacitor dielectric layer for covering the projection portion of the first electrode on other surface side of the base resin layer, and a capacitor second electrode for covering the dielectric layer, wherein a plurality of capacitors each constructed by the first electrode, the dielectric layer, and the second electrode are arranged and aligned in a lateral direction in a state that the capacitors are passed through the base resin layer.

Abstract: A primary memory board is disclosed. The primary memory board comprises a printed circuit board (PCB) having a front side and a back side, a plurality of DIMM surface mount connectors, and at least one component. The plurality of DIMM surface mount connectors are mounted on the front side of the PCB. The at least one component is mounted on the back side of the PCB and is positioned opposite the location of at least one of the plurality of DIMM surface mount connectors mounted on the front side of the PCB.

Abstract: A substrate, preferably constructed of a ductile material and a tool having the desired shape of the resulting device for contacting contact pads on a test device is brought into contact with the substrate. The tool is preferably constructed of a material that is harder than the substrate so that a depression can be readily made therein. A dielectric (insulative) layer, that is preferably patterned, is supported by the substrate. A conductive material is located within the depressions and then preferably lapped to remove excess from the top surface of the dielectric layer and to provide a flat overall surface. A trace is patterned on the dielectric layer and the conductive material. A polyimide layer is then preferably patterned over the entire surface. The substrate is then removed by any suitable process.

Abstract: A method for manufacturing a substrate board with high efficiency of heat conduction and electrical isolation is disclosed. The method comprises the steps of: providing a substrate layer with an arrangement surface and a heat-dissipating surface; executing an anodic treatment on the arrangement surface and the heat-dissipating surface to respectively form a first anodic treatment layer and a second anodic treatment layer; forming a heat conduction and electrical isolation layer on the second anodic treatment layer; and forming a diamond like carbon (DLC) layer on the heat conduction and electrical isolation layer. The heat expansion coefficient of the substrate layer is greater than that of the second anodic treatment layer, the heat conduction and electrical isolation layer, and the DLC layer in turn.

Abstract: This invention provides a better means to achieve affordable solar energy, as well as other technologies. It does so by improving control grids (for addressing and alignment) in solar concentrators and optical equipment in general. Thus troublesome and expensive grid material like Indium Tin Oxide (ITO) can be replaced by more manageable, hardier, and in the long run relatively less expensive nanotubes; or a carbon grid simply laid down by ordinary photocopy (Xerographic) reduction techniques. The instant invention relates to improvements in the control (addressing and alignment) grid for Solar Energy Concentrators; and similar equipment such as Optical Switches [e.g. cf. M. Rabinowitz U.S. Pat. No. 6,976,445]; and Display devices such as Dynamic Reflection, Illumination, and Projection equipment [e.g. cf. M. Rabinowitz U.S. Pat. No. 7,130,102]; as well as display equipment in general.

Abstract: A component built-in module of the present invention includes: a first wiring pattern; an electronic component mounted on the first wiring pattern; a second wiring pattern; an electrical insulating sheet with the electrical component built therein, the electrical insulating sheet being disposed between the first wiring pattern and the second wiring pattern; and a via conductor formed in a via hole penetrating through the electrical insulating sheet, the via conductor connecting electrically the first wiring pattern and the second wiring pattern. A side face of the via conductor defines a continuous line in an axis direction of the via conductor. Thus, a component built-in module having excellent reliability concerning electrical connection can be provided.

Abstract: A system may include a first microvia pad, a second microvia pad having a projection extending in a direction toward the first microvia pad, and a microvia electrically coupled to the first microvia pad and to the second microvia pad.

Abstract: An apparatus and method to provide a micro-electromechanical systems (MEMS) radio frequency (RF) switch module with a vertical via. The MEMS RF switch module includes a MEMS die coupled to a cap section. The vertical via passes through the cap section to electrically couple an RF switch array of the MEMS die to a printed circuit board (PCB). In one embodiment, the MEMS die includes a trace ring surrounding at least a portion of the RF switch array so that a signal may enter or exit the MEMS RF switch module using the vertical via without crossing the trace ring.

Abstract: A stacked microelectronic assembly includes a plurality of microelectronic subassemblies. Each subassembly includes a substrate having at least one site, a plurality of first contacts and a plurality of second contacts. Each subassembly also has at least one microelectronic element assembled to the at least one attachment site and electrically connected to at least some of the first and second contacts. The substrate is folded so that the first contacts are accessible at a bottom of a subassembly and the second contacts are accessible at a top of a subassembly. The plurality of subassemblies are stacked one on top of another in a generally vertical configuration. The substrate of at least one of the subassemblies has a plurality of attachment sites and a plurality of microelectronic elements assembled to the attachment sites. The substrate is folded so that at least some of the plurality of microelectronic elements are disposed alongside one another.

Abstract: An apparatus including a substrate having dimensions suitable as a support circuit for at least one integrated circuit, the substrate comprising a laterally extending plication region defining first and second longitudinal portions; a plurality of conductive traces distributed in a first distribution plane of the substrate and extending transversely through the plication region; a first and second layers of conductive material in a second distribution plane of the first portion and second portion, respectively, of the substrate; at least one conductive bridge extending transversely through less than the entire plication region in the second distribution plane and coupled to the first continuous layer and to the second continuous layer; and at least one externally accessible contact point coupled to at least one of the first and second layers. A method of forming a support circuit and a system including a package.

Abstract: A system may include a first microvia pad, a second microvia pad having a projection extending in a direction toward the first microvia pad, and a microvia electrically coupled to the first microvia pad and to the second microvia pad.

Abstract: A conducting thin-film nanoprobe card fabrication method includes the steps of: (a) arranging nanotubes on a substrate in vertical; (b) covering the nanotubes with a liquid polymeric resin and then hardening the polymeric resin to form a conducting nanomembrane; (c) removing a part of the polymeric resin from the conducting nanomembrane to expose one end of each nanotube to outside; (d) removing the substrate and preparing a ceramic substrate having contacts at one side and metal bumps at the other side and plated through holes electrically respectively connected with the contacts and the metal bumps; (e) mounting the nanomembrane on the ceramic substrate to hold the nanotubes in contact with the contacts of the ceramic substrate, and (f) forming recessed holes in the nanomembrane by etching and inserting a metal rod in each recessed hole to form a respective probe.

Abstract: A wiring transfer sheet including a carrier base and a wiring layer formed thereon is produced so that an exposed area of a surface of the carrier base on which the wiring layer is formed has a plurality of concavities. By transferring the wiring layer to an electrically insulating substrate with this wiring transfer sheet, convexities which are complementary to the concavities are formed on the electrically insulating substrate. The convexities improve adhesion between a wiring board and a resin stacked thereon. Therefore, the wiring board thus obtained has surface coplanarity suitable for mounting a semiconductor bare chip and an electronic component as a whole, and a microscopical surface structure which adheres to a material stacked thereon.

Abstract: A method for making a multi-layer circuit board 116 having apertures 96, 98 which may be selectively and electrically isolated from electrically grounded member 46 and further having selectively formed air bridges and/or crossover members 104 which are structurally supported by material 112. Each of the apertures 96, 98 selectively receives electrically conductive material 114.

Abstract: Computer-based design and verification tools provide integrated circuit layouts for use in chromeless phase lithography. A phase-mask design tool assigns feature size descriptors to circuit layout features, and mask features are configured using the feature size descriptors. Feature size descriptors can be assigned based on feature size ranges established based on a mask error function, feature dimensions with respect to a lithographic system resolution limit, or selected properties of aerial image intensity as a function of feature size. Circuit layout features are assigned mask features that include twin phase steps. In addition, circuit layout features associated with selected feature descriptors are assigned sub-resolution assist mask pattern portions or other mask pattern portions based on optical and process corrections.

Abstract: One embodiment of the present invention provides a system that uses an exposure through a second mask to assist an exposure through a phase shifting mask in printing a tight space adjacent to a large feature. During operation, the system exposes a photoresist layer on the surface of a semiconductor wafer through the phase-shifting mask. This phase-shifting mask includes phase shifters that define a space between a first feature and a second feature, wherein the first feature is so large that the effectiveness of phase shifting is degraded in defining the space. Moreover, the degradation in phase shifting and the tightness of the space cause the space not to print reliably when exposed through the phase shifting mask alone. To alleviate this problem the system exposes the photoresist layer through the second mask, wherein the exposure through the second mask assists in exposing the space between the first feature and the second feature so that the space prints reliably.

Abstract: Conductive or solder bumps are stacked between a mounted component such as a BGA device and a printed wiring substrate in a multileveled printed circuit board unit. An interposer or relay substrate is interposed between the adjacent stacked conductive bumps. The interposer substrate is made of a porous material. When any difference in the expansion is caused between the printed wiring substrate and the mounted component, one side of the interposer substrate receives a relatively smaller displacement force while the other side of the interposer substrate receives a relatively larger displacement force. A shearing stress is induced in the interposer substrate. Deformation of the porous material serves to absorb the shearing stress in the interposer substrate. The conductive bumps bonded on one side of the interposer substrate as well as the conductive bumps bonded on the other side of the interposer substrate may be relieved from a shearing stress.

Abstract: A lithographic process employing a resist for masking a substrate includes additional steps for limiting creep of the resist. The process is suitable for chemical amplification resists incorporating substrate protection agents sensitive to the same inactivation treatment as dissolution inhibitors of the resist. The additional steps are carried out after the development of the resist by dissolution. The steps include an additional step of sensitizing the residual resist on the substrate after the development, followed by a step of bringing the residual resist into contact with neutralization compounds.

Abstract: A Z-axis electrical contact may be formed using a resinous deposit containing conductive particles which may align along surface regions to form an electrical conduction path over the resinous material. If the resinous material is thermoplastic, the material may be heated to mechanically bond to contact surfaces. Advantageously, the resinous material may be formed by forcing a resinous matrix containing conductive particles through an annular opening in a stencil. The resulting member allows surfaces to be contacted which may be irregular or may be covered by native oxide layers.

Abstract: A gas discharge type display apparatus includes a front substrate having a plurality of first electrodes and a back substrate having a plurality of second electrodes and at least ones of the first and second electrodes are made of the photosensitive material containing silver exposed by using the laser thereby, making a mask unnecessary.

Abstract: A wiring transfer sheet including a carrier base and a wiring layer formed thereon is produced so that an exposed area of a surface of the carrier base on which the wiring layer is formed has a plurality of concavities. By transferring the wiring layer to an electrically insulating substrate with this wiring transfer sheet, convexities which are complementary to the concavities are formed on the electrically insulating substrate. The convexities improve adhesion between a wiring board and a resin stacked thereon. Therefore, the wiring board thus obtained has surface coplanarity suitable for mounting a semiconductor bare chip and an electronic component as a whole, and a microscopical surface structure which adheres to a material stacked thereon.

Abstract: A microelectronic die is aligned with a package substrate and attached to it using solder balls. A specially shaped heat spreader, preferably with a coefficient of thermal expansion (CTE) similar to that of silicon, is attached to the back side of the die using a heat-conducting adhesive. An epoxy-based material is flowed into the gap between the die, the substrate, and the heat spreader via a through-hole in either the substrate or the heat spreader using a dispense process or a transfer molding process. By positioning the heat spreader to abut the die corners and/or edges, the stresses on the die are substantially reduced or eliminated.

Abstract: Plastic cards with included electronic elements are made by laminating a carrier sheet bearing multiple electronic elements between top and bottom plastic sheets. The laminated composite is die cut into separate cards. Prior to lamination the carrier sheet is perforated in a web pattern such that the carrier sheet material is largely recessed from the side edges of the finished cards for better lamination and appearance of the finished card edges. The electronic elements may be obtained on continuous rolls of carrier material which is cut into sheets for lamination.

Abstract: A metal-polymer composite comprises a metal and substrate layer disposed on the metal, wherein the substrate layer is formed from a curable thermosetting resin system comprising a curing agent and about 0.1 to 100 weight percent (wt %), preferably about 0.2 to about 80 wt %, more preferably about 0.4 to about 60 wt %, and most preferably about 2 to about 40 wt % of an episulfide, and further wherein the resin system is cured in the presence of the metal. In another embodiment, the thermosetting system comprises about 0.1 to about 50 wt %, preferably about 1 to about 40 wt % and more preferably about 2 to about 30 wt % of at least one episulfide resin, at least one epoxy resin reactive therewith, and a curing agent, wherein the resin system is cured in the presence of a metal, such as a layer of copper or gold. A preferred epoxy resin is the diglycidyl ether of bisphenol A, which is the condensation product of bisphenol A and epichlorohydrin (hereinafter abbreviated “DGEBA”).

Abstract: A printed circuit board and a pad apparatus having a solder deposit formed on the pad apparatus by using a mask having a slit are provided. The slit has the same shape as the solder deposit. The solder deposit includes first and second end portions individually shaped and sized to completely cover at an end portion of the pad a predetermined area of an end portion of the pad, the area defined by both the entire width of the pad and a predetermined length from the end of the pad. A connection web extends between the two end portions to integrate the two end portions into a single structure and is a longitudinal part having a width smaller than any one of both the width of the pad and the width of each of the two end portions. First and second trapezoidal portions are respectively formed at junctions between opposite ends of said connection web and one of the two end portions. The mask has a slit formed at a position corresponding to the position of the solder deposit.

Abstract: A contact pad for a circuit board includes a central portion; and a plurality of spokes extending from the central portion. A circuit board includes a nonconductive substrate; a plurality of electrically conductive contact pads, each of the contact pads having a central portion; and a plurality of spokes extending from the central portion; and an electrically conductive trace interconnecting the contact pads.

Abstract: Conductive layers have at least a portion of a conductive member arranged in a nonlinear or polygonal configuration and having a greater layout area and an insulating layer is alternately stacked relative to the conductive layer, wherein a variation in amount of the conductive member at the conductive layer with a middle of a board thickness direction as a reference is set in a range in which a warp is less likely to be produced and in a range near to zero.

Abstract: A controlled-shaped solder reservoir provides additional solder to a bump in the flow step for increasing the volume of solder forming the solder bump. The controlled shaped reservoirs can be shaped and sized to provide predetermined amounts of solder to the solder bump. Thus, the height of the resulting solder bump can be predetermined. The solder reservoirs can be shaped to take a minimum amount of space, such as by at least partially wrapping around the solder bump. Consequently, the solder bumps may have increased height without adding to the space requirements of the solder bump, or without increasing the fabrication cost. In addition, due to the finite time required for solder flow, a means of sequencing events during soldering is provided.

Abstract: A device with a multi-layered micro-component electrical connector. The multi-layer micro-component electrical connector includes a dielectric layer, a micro-mesh of a first electrical conductor secured to the dielectric layer, and a second electrical conductor secured to and contacting the micro-mesh to provide electrical communication. The dielectric layer has a dielectric layer thermal expansion coefficient and the first electrical conductor has a thermal expansion coefficient different from the dielectric layer thermal expansion coefficient. Due to the presence of the micro-mesh the device is operable at temperatures above 250° C. without delamination or blistering of the first electrical conductor from the dielectric layer.

Abstract: Structures and methods that provide for via transitions between opposite sides of a high resistivity silicon micro-machined membrane substrate. The via transitions provide ground-signal-ground interconnection between coplanar waveguides disposed on opposite sides of substrate. Adjacent via transitions are anisotropically etched from opposite surfaces of the substrate to form the via transitions. The ground-signal-ground configuration provides RF impedance matching at the via transition.

Abstract: A microconnector provides a practically sufficient strength, and has an arrangement in which structures of electrode members and guiding members can be designed at least somewhat independently of each other for allowing a simple connecting operation. In a male connector, wiring layers are formed on a substrate, and male pin connector electrodes project from the wiring layers, whereby the electrodes are two-dimensionally arranged and enclosed with spacers. In a female connector, on the other hand, wiring layers are formed on a substrate, and female connector electrodes are formed on single ends of the wiring layers respectively. The female connector electrodes comprise holes for receiving the pin electrodes, and are arranged in correspondence to the pin electrodes. The female connector electrodes each having a spring characteristic and are enclosed with spacers.

Abstract: A printed circuit board (PCB) assembly includes a PCB having and a ferrite attenuator. The PCB includes input/output signal paths for carrying signals to and from the PCB, power paths for conducting power to the PCB, and ground paths for connecting the PCB to a ground level. The ferrite attenuator surrounds the input/output signal paths, the power paths, and the ground paths. The PCB assembly is preferably used in a system, such as a computer system, where the ferrite attenuator suppresses electromagnetic interference (EMI) generated in the system.

Abstract: A microfabricated device having a high vertical aspect ratio and electrical isolation between a structure region and a circuit region. The device may be fabricated on a single substrate and may include electrical interconnections between the structure region and the circuit region. The device includes a substrate and an isolation trench surrounding a structure region in the substrate. The isolation trench includes a lining of a dielectric insulative material. A plurality of electromechanical elements are located in the structure region and are laterally anchored to the isolation trench.

Abstract: A Z-axis electrical contact may be formed using a resinous deposit containing conductive particles which may align along surface regions to form an electrical conduction path over the resinous material. If the resinous material is thermoplastic, the material may be heated to mechanically bond to contact surfaces. Advantageously, the resinous material may be formed by forcing a resinous matrix containing conductive particles through an annular opening in a stencil. The resulting member allows surfaces to be contacted which may be irregular or may be covered by native oxide layers.

Abstract: An electronic packaging assembly is disclosed. An electronic component is disposed on a socketing substrate utilizing a ball grid array or land grid array. The socketing substrate contains a series of pins that are embedded within the thickness of the socketing substrate. The pins correspond with the ball grid array or land grid array contacts of the electronic component. The socketing substrate is mounted onto a motherboard using an array of solder balls that correspond to and are disposed on, the end of the pins facing the motherboard. If desired, the electronic component may be protected by a metal lid. If desired, socketing substrates can be disposed on both sides of a motherboard.

Abstract: A printed wiring board employing a grooved path conductive lead configuration. The printed wiring board is formed on a substrate having a surface area. Grooved paths having side walls are formed in the substrate and the sidewalls are coated with a conductive material to form a conductive lead for carrying an electronic signal. The grooved path leads permit closer spacing between adjacent lead pairs without increasing crosstalk between the lead pairs. The grooved path leads also accommodate the inclusion of obstructions such as mounting areas on the substrate because the spacing between adjacent grooved path leads can be condensed without increasing crosstalk levels.

Abstract: A reduced crosstalk microstrip transmission-line has a plurality of microstrips sandwiched between a lower base dielectric layer of flexible circuit material and an upper coverlay with higher permittivity and of different flexible circuit material than the base dielectric layer. With the higher permittivity of the coverlay, the thickness of the coverlay is selected such that the microstrip transmission-line retains practical flexibility and far-end crosstalk to a first neighboring microstrip from a driving channel is zero.

Abstract: A process and apparatus for producing supported conductive networks which can be flexible or rigid, having densely packed circuits. The process and apparatus for making the conductive network involves forming a conductive material supported on a "dynamic pressure cushion" into a non-planar pattern defining the desired conductive circuits in relation to a fixed reference plane. The "dynamic pressure cushion" is a material having suitable viscosity and flow characteristics to flow out from under the conductive material as it is being formed and fill up any voids. To ensure that the "dynamic pressure cushion" properly flows without deforming the desired circuits, the die used to form the conductive material is provided with a material flow control grid and material expansion troughs. After forming the unwanted material is then mechanically removed in dimensional relation to the reference plane leaving the desired conductive circuits.

Abstract: In a substrate member (e.g., circuit board), a plurality of openings (15) are formed in an insulating film (14) which covers electric lines (12) formed on a substrate 11, with pad constructing (contacting) portions (13) of selected ones of the electric lines being exposed. In one example, the pad constructing portion (that portion of the pad to which final connection is to occur, e.g., by solder to a semiconductor device), is set to a first dimension (e.g., length) having a dimension less than a corresponding dimension of the original length. The film openings are also set to another dimension having an allowance size larger than a corresponding dimension of the pad constructing portion. The opening is thus of sufficiently large size in comparison to the respective pad being exposed so as to assure effective tolerance compensation for film positioning deviations in at least two (e.g., X and Y) directions as might occur during production of the substrate member.

Abstract: An integrated circuit device includes a first insulation layer formed on a substrate; a second insulation layer formed above the first insulation layer; a thin-film resistor formed on the second insulation layer; a third insulation layer in covering relation to the thin-film resistor and the second insulating layer; first contact holes penetrating the third insulation layer in association with the thin-film resistor; second contact holes penetrating through the second and third insulation layers; and conductive layers for electromagnetically shielding the thin-film resistor, the conductive layers including a first conductive layer formed between the first and second insulation layers below the thin-film resistor and a wiring layers formed above the thin-film resistor within the first and second contact holes.

Abstract: A unitized multilayer circuit structure that includes a plurality of planar dielectric insulating layers stacked in laminar fashion to form a substrate having sides formed by edges of the dielectric insulating layers and recessed regions formed in one or more one sides of the substrate for use in attaching the unitized multilayer circuit structure to a higher level assembly or for attaching electrical contact circuitry to the unitized multilayer circuit structure.

Abstract: A supported conductive network (SCN), which can be flexible or rigid, can have self-aligning conductors which connect with corresponding conductors of other networks. The conductive network can be fabricated into densely packed contact clusters for use as electrical interconnectors or circuits. The methods and apparatus for making the conductive network involve forming a sheet of conductive material into ridges and troughs one of which defines the conductive network and the other of which is waste material and then mechanically removing the waste material. The conductive network thus formed is supported by a dielectric layer.

Abstract: An electrical connector includes a housing and a row of connector contacts coupled to the housing. The row of connector contacts has a predetermined center-to-center spacing between adjacent contacts, with the predetermined center-to-center spacing being relatively large relatively far from an imaginary reference point in the row of connector contacts, and being relatively small relatively near the imaginary reference point in the row of connector contacts. The imaginary reference point is preferably at the center of the row of contacts, and the center-to-center contact spacing preferably progressively increases from the center of the row to the ends of the row. The size of the connector contacts may also progressively increase as well. The electrical connector is preferably adapted for use with a multilayer ceramic substrate which includes a row of capture pads of the same predetermined center-to-center spacing at the edge thereof.

Abstract: A hermetic package particularly adapted for high density interconnect (HDI) electronic systems employs a ceramic substrate which serves as a base for the hermetic package. The substrate comprises a cofired body including buried conductors which provide electrical continuity between a set of inner contact points and a set of outer contact points bridging a seal ring that comprises either a solder seal or a weldable seal for the hermetic package lid. The outer contact points may be directly connected to a leadframe. The leadframe leads, after severing, can be directly attached to a printed circuit board.

Abstract: A multi-layer printed circuit board with self-contained printed resistors includes an undercoat layer made of an insulating material and formed on an outermost conductor circuit at least except for a ground portion of the outermost conductor circuit; an electro-magnetic wave shield layer made of a cured copper paste and formed on the undercoat layer and the ground portion of the outermost conductor circuit so as to cover a generally entire surface of the outermost conductor circuit; and protective overcoat covering an outer surface of the shield layer.

Abstract: A multilayer wiring substrate having high reliability can be produced in good productivity by subjecting metal wiring layers to stabilization treatment on the surface with a metal such as Cr, Mo or the like or an aqueous solution of water glass so as to prevent generation of hillocks or whiskers and to improve chemical resistance.

Abstract: An arrangement for interconnecting high density signals of integrated circuits includes an electronic circuit on a multilayered substrate which includes at least three layers. These layers comprise a signal layer for carrying signals in the electronic circuit, a dielectric layer of organic material disposed adjacent the signal layer, and a metallic reference layer. The layers are disposed such that the dielectric layer is between the signal layer and the metallic reference layer. For providing controlled line impedance and for reducing cross-talk between the signals carried in the electronic circuit, the metallic reference layer includes uniformly spaced apertures which are situated in a slanted grid arrangement.