Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.

Abstract: An electronic component-embedded substrate includes a wiring structure including a plurality of insulating layers and a plurality of wiring layers and having a cavity penetrating through at least one of the plurality of insulating layers, a first electronic component disposed in the cavity, a dam structure disposed on the wiring structure and having a through-portion, a first insulating material disposed in at least a portion of each of the cavity and the through-portion, and covering at least a portion of each of the wiring structure and the first electronic component, and a first circuit layer disposed on the first insulating material.

Abstract: The semiconductor device includes an insulating circuit substrate mounted with a semiconductor element; an external terminal; a base including a support portion; an adhesive sheet; and a sealing portion covering the semiconductor element. The support portion has a first surface, a second surface on the side opposite to the first surface, and a first opening opened at the first surface and the second surface. The insulating circuit substrate is disposed in the first opening. The adhesive sheet is disposed on the second surface of the support portion and has a second opening in which the semiconductor element is disposed in plan view. The adhesive sheet is projected into the first opening in plan view and adhered to a circuit block. The external terminal is adhered on the adhesive sheet and has a connecting surface to which a bonding wire is connected.

Abstract: A disclosed apparatus may be a circuit board that includes (1) a first unique sublaminate that includes a plurality of ground layers and a plurality of signal layers, (2) a second unique sublaminate that includes a plurality of power layers and another plurality of signal layers, and (3) a symmetry axis that bisects the circuit board between the first unique sublaminate and the second unique sublaminate, wherein the first unique sublaminate and the second unique sublaminate are distinct from one another. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A stretchable wiring board that includes a stretchable substrate having a first main surface with a first region, a second region adjacent the first region, and a third region adjacent the second region; a first stretchable wiring line on the first main surface and extending over the first region; an insulating layer extending over the first region and the second region; and a second stretchable wiring line extending over the first region, the second region, and the third region. At a position in the first region where the total thickness of the first stretchable wiring line, the insulating layer, and the second stretchable wiring line is the largest, the thicknesses of the first stretchable wiring line, the insulating layer, and the second stretchable wiring line satisfy a predetermined relationship with the thickness of the second stretchable wiring line at a boundary between the second region and the third region.

Abstract: A wiring substrate includes a core layer, first conductor layers including a first inner conductor layer, a first outer conductor layer and a first intermediate conductor layer, second conductor layers including a second inner conductor layer, a second outer conductor layer and a second intermediate conductor layer, and interlayer insulating layers interposed between the first conductor layers and between the second conductor layers. The first and/or second inner conductor layers has a first laminated structure including a metal foil layer and a plating film layer, the first and/or second outer conductor layers has the first laminated structure, and the first and/or second intermediate conductor layers has a second laminated structure including a metal foil layer and a plating film layer and includes a conductor pattern formed such that an upper surface of the conductor pattern has an edge portion forming an inclined portion inclined toward the core layer.

Abstract: A printed circuit board of a camera module according to various embodiments of the disclosure includes: a ground portion constructed on the printed circuit board; a conductive member which is disposed to cover the ground portion and includes a first opening at a location corresponding to the ground portion; and an adhesive layer which is interposed between the printed circuit board and the conductive member and includes a second opening at a location corresponding to the ground portion, wherein the conductive member may be electrically coupled to the ground portion through a solder constructed on the first opening and the second opening. Other embodiments are also possible.

Abstract: A semiconductor package may include a semiconductor package first side, an embedded bridge interconnect, a first via, and a second via. The bridge interconnect may include a bridge interconnect first side with a conductive pad and a bridge interconnect second side. The distance between the bridge interconnect first side and the semiconductor package first side may be less than a distance between the bridge interconnect second side and the semiconductor package first side. The first and second vias may each include a first end that is narrower than a second end. The semiconductor package first side may be closer to the first end of the first via than the second end of the first via, and closer to the second end of the second via than the first end of the second via. The first side of the semiconductor package may be configured to electrically couple to a die.

Abstract: A device substrate includes a core material. A capacitor sheet can be affixed adjacent to a surface of the core material, where the capacitor sheet covers the surface of the core material. A first opening can extend through both capacitor sheet and the core material, where the first opening are larger than a substrate pass through-hole. An electrically inert material can fill the first opening. A second opening can extend parallel to the first opening through the electrically inert material, where the second opening is at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.

Abstract: A method of manufacturing a base plate includes the following steps: providing a first substrate, the first substrate including a first base layer, a first copper coating and a second copper coating covered on two sides of the first base layer; opening at least one first hole on the first substrate, the first hole penetrating the first base layer and the first copper; forming a first electroplated coating on the first copper coating, the first copper coating filling the first hole to form a first connecting portion; opening at least one second hole on the first connecting portion and the first electroplated coating to form a plurality of second connecting pins.

Abstract: A printed circuit board includes: a first insulating layer; a first wiring layer at least partially buried in the first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer; a second wiring layer at least partially buried in the second insulating layer; and a cavity penetrating through the second insulating layer and a portion of the first insulating layer and exposing a portion of the upper surface of the first insulating layer as a bottom surface of the cavity. The first wiring layer includes a wiring pattern at least partially exposed from the first insulating layer by the cavity, an upper surface of the wiring pattern has a step structure with the upper surface of the first insulating layer exposed by the cavity, and a lower surface of the wiring pattern is coplanar with a lower surface of the first insulating layer.

Abstract: An electronic element mounting substrate includes a first substrate that has a first main surface, has a rectangular shape, and has a mounting portion for an electronic element on the first main surface, and a second substrate that is located on a second main surface opposite to the first main surface, is made of a carbon material, has a rectangular shape, has a third main surface facing the second main surface and a fourth main surface opposite to the third main surface, in which the third main surface or the fourth main surface has heat conduction in a longitudinal direction greater than heat conduction in a direction perpendicular to the longitudinal direction, and that has a recessed portion on the fourth main surface.

Abstract: A multi-layer ceramic capacitor includes: a ceramic body including ceramic layers laminated along one axial direction, first and second internal electrodes alternately disposed between the ceramic layers, first and second end surfaces to which the first and second internal electrodes are respectively drawn, a first end margin that forms an interval between the first end surface and the second internal electrodes, and a second end margin that forms an interval between the second end surface and the first internal electrodes; and first and second external electrodes that respectively cover the first and second end surfaces and are respectively connected to the first and second internal electrodes, the multi-layer ceramic capacitor satisfying the following relationship: SE?S/400+300, where S (?m) represents an area of the ceramic body and SE (?m) represents a total area of the first and second internal electrodes in cross sections of the first and second end margins.

Abstract: An electronic component module includes an electronic component, a structure body, a through wiring, and an insulator. The structure body covers at least a portion of the electronic component and has conductivity. The through wiring extends through the structure body. The insulator is disposed at least between the through wiring and the structure body.

Abstract: An electronic device and oscillator structure are provided. The electronic device includes a printed circuit board, an oscillator configured to oscillate at a frequency corresponding to an operation clock of the electronic device, and a connection member disposed between the oscillator and the printed circuit board such that the oscillator is spaced apart from a surface of the printed circuit board to electrically connect the oscillator to the printed circuit board. The connection member includes a first pad part electrically connected to a terminal of the oscillator, a second pad part electrically connected to a pad of the printed circuit board, and at least one conductive pattern electrically connecting the first pad part and the second pad part.

Abstract: A device and method of utilizing conductive thread interconnect cores. Substrates using conductive thread interconnect cores are shown. Methods of creating a conductive thread interconnect core are shown.

Abstract: Provided is a liquid crystal phase shifting device including: a first substrate and a second substrate that are opposite to each other, wherein first protrusions is provided on a surface of the first substrate facing towards the second substrate, second protrusions is provided on a surface of the second substrate facing towards the first substrate, and the first protrusions and the second protrusions are alternately arranged; a microstrip line provided on the surface of the first substrate facing towards the second substrate, the microstrip line covering at least part of the first protrusions; first support pads provided between the first substrate and the second substrate; a ground electrode provided on the surface of the second substrate facing towards the first substrate, the ground electrode overlapping at least part of the second protrusions; and liquid crystal molecules provided between the microstrip line and the ground electrode.

Abstract: A electronic device includes an embedded ball land substrate and a semiconductor die. The embedded ball land substrate includes a top surface, a bottom surface opposite the top surface, and one or more side surfaces adjacent the top surface and the bottom surface. The embedded ball land substrate further includes a mold layer on the bottom surface, contact pads on the top surface, and ball lands embedded in the mold layer and electrically connected to the contact pads. The semiconductor die includes a first surface, a second surface opposite the first surface, one or more side surfaces adjacent the first surface and the second surface, and attachment structures along the second surface. The semiconductor die is operatively coupled to the contact pads via the attachment structures.

Abstract: A method for manufacturing a millimeter scale electromechanical device includes coupling a stainless steel ply to a polymer carrier ply, coating the stainless steel ply in a photo resist material, masking the photoresist material, exposing the photoresist material to cure a portion of the photoresist material, developing the photoresist material to remove uncured photoresist material from the stainless steel ply, chemically etching the stainless steel ply to remove a patterned portion of the stainless steel ply, dissolving the polymer carrier ply to release unwanted chips of the stainless steel ply, and adhering the patterned stainless steel ply to a flexible material ply to form a sub-laminate.

Abstract: Multiple designs for a multi-layer circuit may be simulated to determine impedance profiles of each design, allowing a circuit designer to select a design based on the impedance profiles. One feature that can be modified is the structure surrounding the barrels of a differential VIA on layers that are not connected to the differential VIA. Specifically, one antipad can be used that surrounds both barrels or two antipads can be used, with one antipad for each barrel. Additionally, the size of the antipad or antipads can be modified. These modifications affect the impedance of the differential VIA. Additionally, a conductive region may be placed that connects to the VIA barrel even though the circuit on the layer does not connect to the VIA. This unused pad, surrounded by a non-conductive region, also affects the impedance of the differential VIA.

Abstract: A transition structure for millimeter wave is provided. The transition structure includes a first layer signal element coupled to an end of a first transmission line and a plurality of first layer ground elements surrounding the end of the first transmission line equidistantly from the end of the first transmission line and disposed along two opposite sides of a strip body of the first transmission line equidistantly from the strip body of the first transmission line. The transition structure further includes an intermediate layer signal element coupled to the first layer signal element and a plurality of intermediate layer ground elements surrounding the intermediate layer signal element quasi-coaxially. A multilayer transition structure including a multilayer structure and the transition structure is also provided. Therefore, the problem of operating frequency caused by the thickness of the multilayer structure can be overcome, thereby increasing the resonance frequency of the multilayer structure.

Abstract: A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.

Abstract: A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

Abstract: A film of the present invention contains a polypeptide derived from spider silk proteins. The decomposition temperature of the film is 240 to 260° C. The film absorbs ultraviolet light having a wavelength of 200 to 300 nm and has a light transmittance of 85% or more at a wavelength of 400 to 780 nm. The film is transparent and colorless in a visible light region. A method for producing a film of the present invention includes: dissolving a polypeptide derived from spider silk proteins in a dimethyl sulfoxide solvent to prepare a dope; and cast-molding the dope on a surface of a base. Thus, the present invention provides a spider silk protein film that can be formed easily and has favorable stretchability, and a method for producing the same.

Abstract: A chip package includes a high voltage withstanding substrate and a device chip. The high voltage withstanding substrate has a main body, a functional layer, and a grounding layer. The main body has a top surface, a bottom surface opposite the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The functional layer is located on the top surface. The grounding layer covers the bottom surface and the sidewall. The device chip is located on the functional layer, and has a grounding pad that faces the main body. The grounding pad is electrically connected to the grounding layer in the through hole.

Abstract: A semiconductor device manufacturing method includes processes of: applying a protective film precursor solution over an end of each of a plurality of semiconductor element structures and a side surface and a bottom surface of a groove; roughly drying a solvent in the protective film precursor solution to form a protective film; and performing full-curing to evaporate a solvent in the protective film after a process of cutting between the plurality of semiconductor element structures or a process of peeling a plurality of semiconductor elements from a dicing tape.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

Abstract: Optoelectronic modules exhibiting relatively small thickness and methods for their manufacture are disclosed. The optoelectronic modules include substrates and transparent covers. Each optoelectronic module includes a transparent substrate on which an optoelectronic component is mounted. The optoelectronic component can be sensitive to and/or operable to generate a particular wavelength of electromagnetic radiation. The transparent substrate is transmissive to the particular wavelength of electromagnetic radiation. In some instances, the transparent substrate is composed, at least partially of glass.

Abstract: A multilayer substrate includes a laminate, first and second signal lines, first and second ground conductors, and interlayer connection conductors. The first and second signal lines extend along a transmission direction and include parallel extending portions that extend in parallel or substantially in parallel with each other. The first and second ground conductors sandwich the first and second signal lines in a laminating direction. The first and second ground conductors respectively include a first opening and a third opening between the signal lines when viewed from the laminating direction, and respectively include second openings and fourth openings disposed outside in a width direction orthogonal or substantially orthogonal to the transmission direction in the parallel extending portions when viewed from the laminating direction. The interlayer connection conductors are disposed in the transmission direction and at least between the signal lines.

Abstract: A semiconductor package includes a core layer, a conductive interconnect and a semiconductor chip. The core layer has a top surface and a bottom surface opposite to the top surface. The conductive interconnect penetrates through the core layer. The conductive interconnect has a top surface and a bottom surface respectively exposed from the top surface and the bottom surface of the core layer. The semiconductor chip is disposed on the top surface of the core layer. The semiconductor chip includes a conductive pad, and the top surface of the conductive interconnect directly contacts the conductive pad.

Abstract: A semiconductor device includes a redistribution layer, a bump bonded to a first surface of the redistribution layer, and a chip bonded to a second surface of the redistribution layer. The redistribution layer includes an insulating layer, a conductive member connecting the bump to the chip and being provided inside the insulating layer, a bonding electrode connected between the conductive member and the bump, and a conductive layer provided between the insulating layer and the conductive member and between the bonding electrode and the conductive member. A resistivity of the conductive member is lower than a resistivity of the conductive layer.

Abstract: A method for fabricating a flexible electronic device, including the steps of: providing channels on a rigid substrate; adhering a flexible substrate to the rigid substrate with an adhesive; fabricating an electronic device on the flexible substrate; injecting a chemical substance into the channels; and reacting the chemical substance with the adhesive and peeling the flexible substrate from the rigid substrate. The rigid substrate comprises a first surface, a second surface opposite the first surface, and a side wall extending between the first surface and the second surface. The channels are provided on the first surface of the rigid substrate. The channels are in communication with an injection port, the injection port is located on the side wall of the rigid substrate, and a portion of the side wall is located between the injection port and the first surface.

Abstract: Circuit assemblies can be electrically interconnected by providing a circuit assembly having a top surface, a bottom surface, and a perimeter edge connecting the top and bottom surfaces, the perimeter edge being formed of insulative material and having a plurality of conductive features embedded in and exposed on the surface of the edge. The conductive features are arranged in contact sets, and each contact set is separated from adjacent contact sets by a portion of the perimeter edge that is free of conductive features. Each contact set includes conductive features that together form a distributed electrical connection to a single node. The insulative material is selectively removed to form recesses adjacent the conductive features exposing additional surface contact areas along lateral portions of the conductive features in the recesses.

Abstract: A high performance touch sensor according to the present invention comprises: a substrate; a first detection electrode formed on the substrate; an insulation layer formed on the first detection electrode; a second detection electrode formed on the insulation layer; and a protection layer formed on the second detection electrode, wherein one of the first detection electrode and the second detection electrode has a triple-film structure including a metal oxide and a thin film metal laminated on each other, and the other one includes a metal pattern. Therefore, the present invention can implement touch sensor having a high resolution and a large area while simultaneously satisfying a low resistance characteristic and an optical characteristic, facilitate progress of a high-temperature process, and diversify the substrate.

Abstract: A silicon interconnect fabric includes: (1) a substrate having a front side and a back side; (2) a front side patterned metal layer on the front side of the substrate; (3) a back side patterned metal layer on the back side of the substrate; (4) multiple conductive vias extending through the substrate and connecting the front side patterned metal layer and the back side patterned metal layer; and (5) multiple conductive posts connected to the back side patterned metal layer.

Abstract: A printed wiring board includes first, second, and third wiring layers, first and second insulating members, and first and second vias. The first wiring layer includes a recognition mark and a first wiring on a first surface. The second wiring layer includes a first pad and a second wiring. The third wiring layer includes a third wiring. The first via penetrates the first insulating member and electrically connects the recognition mark to the first pad. The second via penetrates the second insulating member and electrically connects the first pad to the third wiring. The first pad and the first and second vias are in a region within an outer perimeter of the recognition mark when viewed from a direction orthogonal to the first surface.

Abstract: An iron powder and method of making an iron powder. The method includes a step of neutralizing an acidic aqueous solution containing a trivalent iron ion and a phosphorus-containing ion, with an alkali aqueous solution, so as to provide a slurry of a precipitate of a hydrated oxide, or a step of adding a phosphorus-containing ion to a slurry containing a precipitate of a hydrated oxide obtained by neutralizing an acidic aqueous solution containing a trivalent iron ion with an alkali aqueous solution. A silane compound is added to the slurry so as to coat a hydrolysate of the silane compound on the precipitate of the hydrated oxide. The precipitate of the hydrated oxide after coating is recovered through solid-liquid separation, the recovered precipitate is heated to provide iron particles coated with a silicon oxide, and a part or the whole of the silicon oxide coating is dissolved and removed.

Abstract: A method for manufacturing a printed wiring board includes forming a conductor layer including first and second pads on an insulating layer, forming a dry film resist layer on the insulating and conductor layers, forming first and second openings exposing the first and second pads, applying first metal plating to form first and second base plating layers on the first and second pads, applying second metal plating to form a first top plating layer of a first post and portion of a second top plating layer of a second bump post, applying the second metal plating further to form second portion of the second top layer of the second post, removing the dry film resist layer, forming a solder resist layer to cover the first and second posts, and thinning the solder resist layer over entire surface to position the first and second top layers outside the solder resist layer.

Abstract: The disclosure provides a composite for forming an insulating substrate. The composite includes 100 parts by weight of a liquid crystal polymer and 0.5-85 parts by weight of a dielectric additive. The liquid crystal polymer has a repeating unit represented by in which Ar is 1,4-phenylene, 1,3-phenylene, 2,6-naphthalene, or 4,4?-biphenylene, Y is —O— or —NH—, and X is carboxamido, imido/imino, amidino, aminocarbonylamino, aminothiocarbonyl, aminocarbonyloxy, aminosulfonyl, aminosulfonyloxy, aminosulfonylamino, carboxyl ester, (carboxyl ester)amino, (alkoxycarbonyl)oxy, alkoxycarbonyl, hydroxyamino, alkoxyamino, cyanato, isocyanato, or a combination thereof.

Abstract: A board assembly sheet includes a plurality of mounting boards each for mounting an electronic component. The mounting boards are defined in the board assembly sheet. The mounting board has a total thickness of 60 ?m or less. The board assembly sheet has a through hole passing through the board assembly sheet in a thickness direction. The through hole is formed to be along an end edge of the mounting board or along a phantom line extending along the end edge.

Abstract: An electronic package configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package includes a package substrate of a rectangular shape. A chip package having a first high-speed interface circuit die is mounted on a top surface of the package substrate. The chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. The first high-speed interface circuit die includes a first Serializer/Deserializer (SerDes) circuit block.

Abstract: A planar-type wireless power-receiving circuit module includes a planar ground conductor, a substrate, a power-receiving coil, and a magnetic sheet. The planar ground conductor has a cavity in the middle section thereof. The substrate is disposed on a first main surface of the planar ground conductor. The substrate includes dielectric layers stacked on top of each other in a manner so as to form electronic circuitry. The power-receiving coil is electrically connected to the electronic circuitry and is disposed in the cavity. The magnetic sheet overlaps the power-receiving coil when the planar ground conductor is viewed in plan. The magnetic sheet is part of a path of magnetic flux passing through the power-receiving coil and is disposed on a first main surface of the power-receiving coil.

Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

Abstract: Voids are introduced in a copper shape to reduce warpage experienced by a printed circuit board during a reflow process. Copper shapes on an outer layer of a printed circuit board may be used to connect large packages that include ball grid arrays to the printed circuit board. The copper shapes may induce warpage in the printed circuit board during the reflow process. Routing a mesh pattern of voids in the copper shapes may reduce solder ball joint cracking and pad cratering during reflow and make solder joints more reliable. The voids may make the copper shapes less ridged and change the copper heat dissipation profile to remove sharp warpage forces that cause solder joints to experience pad cratering. The voids may be 8 mil×8 mil cuts or indentations in the copper shape.

Abstract: A semiconductor substrate includes a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer. The dielectric insulation layer includes a first material having a thermal conductivity of between 25 and 180 W/mK, and an insulation strength of between 15 and 50 kV/mm, and an electrically conducting or semiconducting second material evenly distributed within the first material.

Abstract: A semiconductor device has a plurality of interconnected modular units to form a 3D semiconductor package. Each modular unit is implemented as a vertical component or a horizontal component. The modular units are interconnected through a vertical conduction path and lateral conduction path within the vertical component or horizontal component. The vertical component and horizontal component each have an interconnect interposer or semiconductor die. A first conductive via is formed vertically through the interconnect interposer. A second conductive via is formed laterally through the interconnect interposer. The interconnect interposer can be programmable. A plurality of protrusions and recesses are formed on the vertical component or horizontal component, and a plurality of recesses on the vertical component or horizontal component. The protrusions are inserted into the recesses to interlock the vertical component and horizontal component.

Abstract: A power plane structure for a printed circuit board includes a copper layer, and a carbon layer applied directly to a surface of the copper layer. The carbon layer can include graphite or graphene. In additional embodiments, a duplicate power plane structure for a printed circuit board includes two power planes separated by an insulating core, each power plane including a copper layer and a carbon layer applied directly to a surface of the copper layer.

Abstract: A wiring board including a build-up circuit layer, a patterned conductive layer, first and second adhesion promoting material layers and first and second solder mask layers is provided. The build-up circuit layer has a first surface and a second surface opposite thereto. The patterned conductive layer is disposed on the second surface. The first adhesion promoting material layer is disposed on the first surface and includes at least one first opening. The second adhesion promoting material layer is disposed on the second surface and the patterned conductive layer, and includes at least one second opening. The first solder mask layer is disposed on the first adhesion promoting material layer and includes at least one third opening provided corresponding to the first opening. The second solder mask layer is disposed on the second adhesion promoting material layer and includes at least one fourth opening provided corresponding to the second opening.

Abstract: The filter unit has a center frequency and comprises a first dielectric substrate, a first conducting plane, and at least one transmission arrangement. The at least one transmission arrangement comprises a shunt node which has a shunt connection to the conducting plane. The electrical length of the shunt connection defines the center frequency of the filter unit. The transmission arrangement further comprises a plurality of transmission lines connected in series between an input port and an output port, wherein each port is connectable to auxiliary systems with a system impedance. Moreover, each transmission line has a characteristic impedance and wherein the characteristic impedance of each transmission line is less than the system impedance.

Abstract: A thermoelectric module assembly for thermally conditioning a component is includes first and second heat spreaders spaced apart from one another and at least one thermoelectric sub-assembly between and in thermal communication with the first and second heat spreaders. The at least one thermoelectric sub-assembly includes a plurality of thermoelectric devices and a printed circuit board having a plurality of electrical conduits. Each of the thermoelectric devices has a first end portion and a second end portion, the second end portion opposite from the first end portion, the first end portion mechanically coupled to the printed circuit board and in electrical communication with the plurality of electrical conduits, and the second end portion spaced from the printed circuit board.