Abstract: A flexible circuit board capable of transmitting high frequency signals with reduced attenuation includes two outer wiring boards enclosing an inner wiring board. The inner wiring board includes a first conductive wiring layer and a first substrate layer. The first conductive wiring layer includes a signal line and two ground lines on both sides of the signal line. The first substrate layer covers a side of the first conductive wiring layer and defines first through holes which expose the signal line. Each of the two outer wiring boards includes a second substrate layer and a second conductive wiring layer. The second substrate layer abuts the inner wiring board and defines second through holes aligning with the first through holes, to partially surround the signal line with air of very low dielectric constant. A method for manufacturing the flexible circuit board is also disclosed.

Abstract: A package carrier includes a substrate, at least one interposer disposed in at least one opening of the substrate, a conductive structure layer, a first build-up structure, and a second build-up structure. The interposer includes a glass substrate, at least one conductive via, at least one first pad, and at least one second pad. The conductive via passes through the glass substrate, and the first and the second pads are disposed respectively on an upper surface and a lower surface of the glass substrate opposite to each other and are connected to opposite ends of the conductive via. The conductive structure layer is disposed on the substrate and is structurally and electrically connected to the first and the second pads. The first and the second build-up structures are disposed respectively on the first and the second surfaces of the substrate and are electrically connected to the conductive structure layer.

Abstract: Disclosed herein is an OLED lighting apparatus which can compensate for high sheet resistance of a first electrode formed of a transparent conductive material while improving light extraction efficiency through enhancement in aperture ratio. For this purpose, the OLED lighting apparatus omits auxiliary wires and, instead of the auxiliary wires, includes a first auxiliary wire and a second auxiliary wire to secure low resistance. As a result, the OLED lighting apparatus can compensate for high sheet resistance of the first electrode, thereby achieving normal light emission without reduction in luminance due to current drop when implemented as a large-area high-resolution lighting apparatus.

Abstract: A flexible display panel and a flexible display device are provided. The flexible display panel includes: a first insulating layer; a plurality of leads disposed above the first insulating layer, the plurality of leads passing through a predetermined bending region of the flexible display panel; a second insulating layer above respective one of the leads; where at least one of the leads is provided with at least one first hollow portion in the predetermined bending region, and the first insulating layer and the second insulating layer are connected via the at least one first hollow portion. In this way, product performance can be improved.

Abstract: A high power density power supply includes at least one power module and a cooling fan in a casing. A first filter circuit board facing upward is provided below the cooling fan. A second filter circuit board facing downward is provided above the cooling fan. The back of the second filter circuit board is provided with a plurality of buffer pads. An insulating plate is disposed on the buffer pads to completely cover the top of the second filter circuit board. Thereby, the insulating plate provided an insulating effect between an upper cover of the casing and the second filter circuit board to prevent the second filter circuit board from directly contacting the upper cover to form a short circuit, so as to improve the safety of the power supply.

Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.

Abstract: Provided is a structure that has highly reliable electroconductive pattern regions, that offers an extremely simple manufacturing process, and that has excellent electrical insulation between the electroconductive pattern regions. This structure (10) having electroconductive pattern regions is provided with a support (11), and, on a surface configured by the support, a layer (14) in which insulation regions (12) containing a copper oxide- and phosphorus-containing organic substance and electroconductive pattern regions (13) containing copper are disposed next to one another. This stack is provided with: a support, a coating layer containing copper oxide and phosphorus and disposed on a surface configured by the support; and a resin layer disposed so as to cover the coating layer.

Abstract: A high-frequency board includes an insulating substrate, a first line conductor, a second line conductor, a capacitor, a first bond, and a second bond. The insulating substrate has a recess on its upper surface. The first line conductor extends from an edge of the recess on the upper surface of the insulating substrate. The second line conductor faces the first line conductor across the recess on the upper surface of the insulating substrate. The capacitor overlaps the recess. The first bond joins the capacitor to the first line conductor. The second bond joins the capacitor to the second line conductor, and is spaced from the first bond.

Abstract: A resin composition according to the present invention contains a cyanate compound (A). Further, the resin composition according to the present invention contains a maleimide compound (B) and/or an epoxy resin (C); and primary hexagonal boron nitride particles (D) having an average aspect ratio of 4 to 10.

Abstract: A conductive network fabrication process is provided and includes filling a hole formed in a substrate with dielectric material, laminating films of the dielectric material on either side of the substrate, opening a through-hole through the dielectric material at the hole, depositing a conformal coating of dielectric material onto an interior surface of the through-hole and executing seed layer metallization onto the conformal coating in the through-hole to form a seed layer extending continuously along an entire length of the through-hole.

Abstract: A surface mount electronic device providing an electrical connection between an integrated circuit (IC) and a printed circuit board (PCB) is provided and includes a die and a dielectric material formed to cover portions of the die. Pillar contacts are electrically coupled to electronic components in the die and the pillar contacts extend from the die beyond an outer surface of the die. A conductive ink is printed on portions of a contact surface of the electronic device package and forms electrical terminations on portions of the dielectric material and electrical connector elements that connect an exposed end surface of the pillar contacts to the electrical terminations.

Abstract: An electronic component package includes a substrate having an upper surface. Traces on the upper surface of the substrate extend in a longitudinal direction. The traces have a first latitudinal width in a latitudinal direction, the latitudinal direction being perpendicular to the longitudinal direction. Rectangular copper pillars are attached to bond pads of an electronic component, the copper pillars having a longitudinal length and a latitudinal second width. The latitudinal second width of the copper pillars is equal to and aligned with the first latitudinal width of the traces. Further, the longitudinal length of the copper pillars is parallel with the longitudinal direction of the trace and equal to the length of the bond pads. The copper pillars are mounted to the traces with solder joints.

Abstract: A semiconductor package includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, and an inductance sensing part having a coil form and electrically connected to the semiconductor chip.

Abstract: A light-emitting device includes a light-emitting element having an element front surface and an element back surface spaced apart from each other in a first direction, a supporting member on which the light-emitting element is mounted, and a light-transmitting resin formed on the supporting member to cover the light-emitting element. The supporting member includes a base having a base front surface and a base back surface opposite to the base front surface, and first and second wirings each disposed on the base and electrically connected to the light-emitting element. The light-emitting element is mounted on the support member with the element back surface facing the base front surface.

Abstract: Provided is an electronic apparatus capable of improving time margin. The electronic apparatus includes: a base substrate including a substrate base including a plurality of layers and a plurality of wiring layers between the layers; a controller chip and at least one memory semiconductor chip mounted on the base substrate; a signal line disposed in one of the wiring layers and connecting the controller chip to the at least one memory semiconductor chip; and a pair of open stubs disposed in another wiring layer, connected to both ends of the signal line, and extending to face each other with a gap.

Abstract: Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide an improved data transfer rate of 1 gigabits per second over at least a 6 mm span, for example. The embedded interposers are not limited to use with memory modules.

Abstract: An electronic component manufacturing method includes a blotting process of bringing a conductive paste applied to an end portion of each electronic component body held by a jig into contact with a surface of a surface plate. The blotting process includes simultaneous performance of a distance changing process of changing the distance between an end face of each electronic component body and the surface of the surface plate and a position changing process of changing a two-dimensional position where the end face of the electronic component body is projected on the surface of the surface plate in such a manner that the direction of the movement of two-dimensional position in parallel to the surface of the surface plate successively varies (e.g., along a circular path).

Abstract: A method for manufacturing a circuit board with embedded conductive circuits includes providing a first circuit substrate having a first support board and a first peelable film, providing a second circuit substrate having a second support board and a second peelable film, providing an insulating layer to obtain an intermediate body, pressing the intermediate body, and removing the first support board, the first peelable film, the second support board, and the second peelable film. The first circuit substrate includes a first circuit layer. The second circuit substrate includes a second circuit layer. The first circuit layer is electrically coupled to the second circuit layer through the insulating layer.

Abstract: A circuit includes a printed circuit board including a first portion defining a window formed as a first void on a first side of the printed circuit board and a second portion defining a cavity formed as a second void opposite the first void on a second side of the printed circuit board. The circuit further includes a heat sink inserted in the second void, the heat sink having a first side forming a bottom of the first void and the bottom of the first void within the printed circuit board. The circuit yet further includes at least one electronic circuit die mounted to the first side of the heat sink and electrically coupled to the first side of the printed circuit board.

Abstract: A chip includes a substrate; macros placed on the substrate, which has a placement region being divided into sub-regions according to locations of the macros; and one or more vertical power stripes (VPSs) disposed in each sub-region. At least one VPS is not aligned with the VPSs of an adjacent higher or lower sub-region.

Abstract: Described are component carriers including a stepped cavity into which a stepped component assembly is embedded. The component carriers have (a) fully cured electrically insulating material originating from at least one electrically insulating layer structure of the component carrier and circumferentially surrounding the stepped component assembly and/or (b) an undercut in a transition region between a narrow recess and a wide recess of the stepped cavity. Further described are methods for manufacturing such component carriers.

Abstract: Example implementations relate a chassis for a circuit assembly. The chassis includes a chassis body defining an access opening and a volume to house the circuit assembly including a circuit module and an input-output (IO) unit. The chassis body houses the circuit assembly such that the circuit module is enclosed within the volume defined by the chassis body and the IO unit remains accessible for cabling at the access opening. The chassis further includes an IO enclosure attached to the chassis body to seal the access opening from surrounding environment, where the IO enclosure includes a cabling port to allow the cabling to the IO unit.

Abstract: An integrated circuit is attached to a chip carrier in a flip chip configuration. An electrically conductive conformal layer is disposed on a back surface of the substrate of the integrated circuit. The electrically conductive conformal layer contacts the semiconductor material in the substrate and extending onto, and contacting, a substrate lead of the chip carrier. The substrate lead of the chip carrier is electrically coupled to a substrate bond pad of the integrated circuit. The substrate bond pad is electrically coupled through an interconnect region of the integrated circuit to the substrate of the integrated circuit. A component is attached to the chip carrier and covered with an electrically insulating material. The electrically conductive conformal layer also extends at least partially over the electrically insulating material on the component. The electrically conductive conformal layer is electrically isolated from the component by the electrically insulating material on the component.

Abstract: There is provided a rubber composition for additive manufacturing that allows rubber shaped articles to be favorably produced using an additive manufacturing apparatus. The rubber composition for additive manufacturing of the present invention comprises a liquid rubber.

Abstract: According to one embodiment, the present invention relates to a printed circuit board, comprising: a first insulating layer; an inner layer circuit pattern disposed on an upper surface of the first insulating layer; a second insulating layer, disposed on the first insulating layer, for covering the inner layer circuit pattern; a first outer layer circuit pattern integrated into a lower surface of the first insulating layer; and a second outer layer circuit pattern embedded in an upper surface of the second insulating layer, the first insulating layer comprising a thermosetting resin, and the second insulating layer comprising a photocurable resin.

Abstract: A single-board computer system radiation hardened for space flight includes a printed circuit board (PCB) having a top side and bottom side; a reconfigurable field programmable gate array (FPGA) processor device a connector disposed on the top side; a plurality of peripheral components mounted on the bottom side, wherein AC coupling capacitors are configured to select routing between the first FPGA and the second FPGA. An expansion card plug attaches to a connector on the bottom of the PCB and a frame is mounted to the PCB.

Abstract: A printed circuit board is provided. The printed circuit board includes an insulating material, and a circuit comprising a first region that partially penetrates the insulating material, and a second region formed on the first region and that protrudes from an upper portion of the insulating material, the first region includes a first electroplating layer and a first electroless plating layer that are formed between the insulating material and the first electroplating layer.

Abstract: A filler-containing film that can be precisely pressed to an electronic component with lower thrust is a film having a filler distributed layer in which fillers are regularly disposed in a resin layer, wherein an area occupancy rate of the fillers in a plan view is 25% or less, a ratio La/D between a layer thickness La of the resin layer and a particle diameter D of the fillers is 0.3 or more and 1.3 or less, and a proportion by number of the fillers present in a non-contact state with each other is 95% or more with respect to the entire fillers. The proportion by number of the fillers present in a non-contact state with each other is preferably 99.5% or more with respect to the entire fillers.

Abstract: A semiconductor device includes an internal circuit and a power mesh configured to transmit an operating voltage to the internal circuit. The power mesh includes first power lines extending in a first direction and arranged in a second direction intersecting with the first direction, when viewed from a top; second power lines sharing lanes with the first power lines and at least partially overlapping with the first power lines in the second direction; first power straps extending in the second direction and coupled to the first power lines; and second power straps extending in the second direction and coupled to the second power lines. Each of the first and second power lines may have a width of the same size as a width of each lane in sections where they do not overlap, and may have a width of a size smaller than the width of each lane in sections where they overlap.

Abstract: A circuit board includes: an insulating layer having at least a part formed of an insulating resin; and an electrode pad embedded in the insulating layer and having a neck formed on an outer side surface, the neck being held in contact with the insulating resin of the insulating layer. The electrode pad includes: a first conductor layer having an end surface exposed from one surface of the insulating layer; and a second conductor layer formed on the first conductor layer and having a grain boundary density different from a grain boundary density of the first conductor layer. The neck is formed in a region of the outer side surface, the region corresponding to a boundary part between the first conductor layer and the second conductor layer.

Abstract: A sheet material includes a resin layer containing a binder and catalyst particles, an electroless plating film on the side of one main surface of the resin layer and including first electroless plating films and a second electroless plating film, and a base material on the side of the other main surface of the resin layer.

Abstract: A printed circuit board assembly (PCBA) controls an electrically-initiated device (EID) in an electric field. The PCBA includes a conductive layer, a dielectric layer, and a trans-conductive layer (TCL). The conductive layer of the PCBA designated protected areas. An electrical current with a predetermined current density is impressed in the conductive layer when the PCBA is in the electric field. The TCL is a nickel-metal composite metamaterial positioned between the conductive and dielectric layers and configured to change in shape or thickness in the electric field such that the impressed current is steered away from the conductive layer and into the dielectric layer to prevent premature activation of the EID. A system includes an outer housing, power supply, an EID such as a sonobuoy or medical device, and the PCBA, all of which are encapsulated in the housing. A method is also disclosed for manufacturing the PCBA.

Abstract: A chip antenna module includes a substrate having layers; a chip antenna mounted on one surface of the substrate to radiate a radio signal, the chip antenna having a body portion formed of a dielectric substance, and a ground portion and a radiating portion disposed on opposite surfaces of the body portion; and an auxiliary patch disposed below the radiating portion on at least one layer of the substrate.

Abstract: A printed wiring board in the present disclosure includes a core layer, a first buildup layer, a second buildup layer, and a through hole. The core layer has a conductor circuit located on a surface of an insulator. The first buildup layer containing a first resin is laminated on a surface of the core layer. The second buildup layer containing a second resin is laminated on a surface of the first buildup layer. The through hole extends through the core layer, the first buildup layer, and the second buildup layer. The first resin and the second resin are different from each other. The second buildup layer includes a plurality of filled vias filled with a conductor which are located around a circumference of an opening of the through hole.

Abstract: In a non-reciprocal circuit element, a permanent magnet is connected to one main surface of a magnetic plate, and a circuit board is connected to the other main surface of the magnetic plate, with a solder bump lying between the circuit board and the other main surface. The permanent magnet can control the transmission of electrical signal from each of a plurality of signal conductors of circuit board to a corresponding one of a plurality of input/output terminals of the magnetic plate. The non-reciprocal circuit element further includes an underfill material arranged between the magnetic plate and the circuit board. The magnetic plate has a through hole formed therein, the through hole extending from one main surface to the other main surface. The through hole has an empty space in which at least a part of a conductive film arranged in the through hole is exposed.

Abstract: The stiffening brace may include a set of borders dimensioned to substantially surround an integrated circuit, wherein each border includes (1) a portion of material that is positioned atop a perimeter of the integrated circuit and (2) an additional portion of material that extends beyond the perimeter of the integrated circuit such that the additional portion of material overhangs a circuit board to which the integrated circuit is soldered. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A method of manufacturing a constituent for a component carrier is disclosed. The method includes providing an electrically conductive structure, forming a highly thermally conductive and electrically insulating or semiconductive structure on the electrically conductive structure, and subsequently, attaching a thermally conductive and electrically insulating structure, having a lower thermal conductivity than the highly thermally conductive and electrically insulating or semiconductive structure, on an exposed surface of the highly thermally conductive and electrically insulating or semiconductive structure.

Abstract: An electronic component embedded substrate includes first insulating layer having a first through portion; a first electronic component disposed in the first through portion; a second insulating layer disposed on the first insulating layer and having a second through portion; a second electronic component disposed in the second through portion; and an insulating material covering at least a portion of each of the first electronic component and the second electronic component. The first through portion and the second through portion intersect, such that a portion of the first through portion and a portion of the second through portion overlap each other, on a plane.

Abstract: A component carrier is provided, which includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; a component on the stack; and stress propagation suppressing particles in at least part of the stack suppressing propagation of stress through the component carrier.

Abstract: A printed circuit board is provided. The printed circuit board includes N power layers and a first via group. The N power layers are arranged in parallel and spaced from each other. The first via group includes M rows of vias which are disposed through the N power layers, where N and M are positive integers greater than 0. Each row of the M rows of vias is electrically connected to the first layer of the N power layers. A Pth row of the M rows of vias is further electrically connected to Q power layers of the N power layers respectively, where Q is a smallest positive integer greater than or equal to P((N?1)/M), and P is a positive integer less than or equal to M.

Abstract: An electronic assembly and a method of forming an electronic assembly. The electronic assembly including a printed circuit board including a perimeter; a compression gasket extending around at least a portion of the perimeter of the printed circuit board; and a housing including a first wall and a housing side wall extending from the first wall, the first wall and housing side wall form a cavity, wherein the printed circuit board and the compression gasket are located within the cavity with the compression gasket positioned between the perimeter and the housing side wall.

Abstract: The present invention provides a surface treated copper foil in which a dropping of the roughening particles from a roughening treatment layer on the surface of the copper foil is suppressed and an occurrence of wrinkles or stripes when bonding with an insulating substrate is suppressed. The surface of the roughening treatment layer satisfies one or more of the following: a roughness Ra is 0.08 to 0.20 ?m, a roughness Rz is 1.00 to 2.00 ?m, a roughness Sq is 0.16 to 0.30 ?m, a roughness Ssk is ?0.6 to ?0.35, a roughness Sa is 0.12 to 0.23 ?m, a roughness Sz is 2.20 to 3.50 ?m, a roughness Sku is 3.75 to 4.50, and a roughness Spk is 0.13 to 0.27 ?m, a glossiness of a TD of the surface of the side of the roughening treatment layer of the surface treated copper foil is 70% or less.

Abstract: An article includes a wafer having a body which defines a first surface and a second surface. The wafer defines a via having a via surface extending between the first and second surfaces through the body. An adhesion layer is positioned on the via surface. At least a portion of the via surface is free of the adhesion layer. A metallic component is positioned within the via and extends from the first surface to the second surface.

Abstract: There is provided a method for manufacturing an electrical wire. The electrical wire includes a rod-like conductor having a shape corresponding to a predetermined wiring route and also having rigidity to enable the rod-like conductor to maintain the shape, and an insulation sheath covering the rod-like conductor. The method includes: preparing a plurality of rod-like preliminary conductors having the rigidity so as to correspond to a plurality of sub routes into which the wiring route is divided; processing at least one of the plurality of preliminary conductors into a shape conforming to the corresponding sub routes; connecting the plurality of preliminary conductors together to form the rod-like conductor; and forming the insulation sheath to cover the rod-like conductor.

Abstract: An electronic component includes a multilayer capacitor, including a capacitor body, and a pair of external electrodes disposed on both ends of the capacitor body, respectively, and an interposer, including an interposer body, and a pair of external terminals disposed on both ends of the interposer body, respectively. The external terminals include bonding portions, mounting portions, and connection portions disposed to connect the bonding portions and the mounting portions to each other. Adhesives are provided between the external electrodes and the bonding portion. A height at which the adhesives fall along the connection portions of the external terminals is defined as t and a height of the interposer is defined as T, t/T satisfies 0.04?t/T?0.80.

Abstract: The application provides a printed circuit board and an optical module so as to alleviate poor contact between the electro-conductive contact sheet group and the clamping piece due to the solder resist. The printed circuit board includes a substrate, and electro-conductive contact sheet group positioned on the surface of the substrate, where a part of the substrate is overlaid with solder resist, and there is a gap between the solder resist and the electro-conductive contact sheet group.

Abstract: A display substrate includes a substrate, a plurality of electrode leads disposed on the substrate, and a plurality of electrodes electrically disconnected with each other disposed on the substrate. Each electrode is in direct contact with one or more of the plurality of electrode leads, and a thickness of each electrode lead is greater than a thickness of a corresponding electrode. At least one of the plurality of electrode leads is respectively provided with at least one gap, and each gap is configured to electrically disconnect one of the plurality of electrodes that is in direct contact with a corresponding electrode lead from another one of the plurality of electrodes that is adjacent to the corresponding electrode lead.

Abstract: A method for manufacturing a housing is described. The methods includes: providing a cover body defining a slot; filling a first material into the slot; and filling a second material into the slot to fill up the slot. A housing and a mobile terminal including the housing are further provided.

Abstract: A multilayer substrate includes a lamination body including a first resin substrate, a second resin substrate, and a bonding layer that are hot-pressed. A first conductor pattern including a surface defined by a plated film is disposed on a first surface of the first resin substrate. A second conductor pattern including a surface defined by a plated film is disposed on a second surface of the first resin substrate. A third conductor pattern including a surface defined by a plated film is disposed on a third surface of the second resin substrate. A fourth conductor pattern including a surface defined by a plated film is disposed on a fourth surface of the second resin substrate. The first conductor pattern is located closer to one outermost layer than the second conductor pattern is. The second conductor pattern is thinner than the first conductor pattern.

Abstract: A fan-out semiconductor package is provided. A semiconductor chip is disposed in a through hole of a first connection member. At least a portion of the semiconductor chip is encapsulated by an encapsulant. A second connection member including a redistribution layer is formed on an active surface of the semiconductor chip. An external connection terminal having excellent reliability is formed on the encapsulant.