Abstract: The present invention relates to a resin paste composition including an organic compound, and a granular aluminum powder having an average particle diameter of from 2 to 10 ?m and a flake-shaped silver powder having an average particle diameter of from 1 to 5 ?m which are uniformly dispersed in the organic compound, and a semiconductor device manufactured by bonding a semiconductor element onto a supporting member through the resin paste composition and then encapsulating the resulting bonded product. According to the present invention, it is possible to provide a resin paste composition used for bonding an element such as semiconductor chips onto a lead frame which is excellent in not only electrical conductivity and bonding property but also working efficiency without using a large amount of rare and expensive silver, and a semiconductor device having a high productivity and a high reliability.

Abstract: A patterned transparent conductor includes a substrate and additives at least partially embedded into at least one surface of the substrate and localized adjacent to the surface according to a pattern to form higher sheet conductance portions. The higher sheet conductance portions are laterally adjacent to lower sheet conductance portions.

Abstract: A method and apparatus for filling a via with transparent material is presented, including the steps of providing a panel having a via, occluding the via with transparent material in a workable state so that a portion of the occluding material is internal to the via and a portion of the material is external to said via. The external and internal portions are separated so the transparent filler material, when set, forms a smooth and featureless surface. This causes the filled via to have a substantially even and uniform appearance over a wide range of viewing angles when lit.

Abstract: A composite component includes a first joining partner, at least one second joining partner and a first joining layer situated between the first joining partner and the second joining partner. In addition to the first joining layer, at least one second joining layer is provided between the first and the second joining partner; and at least one intermediate layer is situated between the first and the second joining layer.

Abstract: A method of manufacturing a narrow frame touch input sheet having very good anticorrosion properties and suitable for a narrow frame capacitance type touch sensor having a double-layer transparent conductive film pattern. The method uses an electrical conductivity sheet obtained by sequentially forming transparent and light blocking conductive films, and first resist layers, on both sides of a transparent base sheet, exposing and developing the resist layers on both sides simultaneously, etching the transparent and light blocking films simultaneously, removing the resist layers, laminating second resist layers with anticorrosion agent on the revealed light blocking films, etching the light blocking films in center windows and terminal portions to reveal the transparent films, and side etching revealed end faces of the light blocking films at center window and terminal portion boundaries to create visor structured second resist layers that are heat softened as an anticorrosion layer on the revealed faces.

Abstract: A wiring substrate includes a substrate body formed of an inorganic material and including a first surface and a second surface, a first trench formed in a first surface side of the substrate body, a second trench formed in a second surface side of the substrate body, a penetration hole penetrating through the substrate body, a first plane layer filling the first trench, a second plane layer filling the second trench, and a penetration wiring filling the penetration hole. The first plane layer is a reference potential layer. The second plane layer is a power supply layer.

Abstract: Disclosed herein is a method for fabricating a printed circuit board, including: stacking a second insulating layer including a reinforcement on an outer surface of a first insulating layer having a post via formed thereon; polishing an upper surface of the second insulating layer to expose an upper side of the post via; stacking a film member on the second insulating layer to cover the post via and compress the second insulating layer; polishing an upper surface of the film member to expose an upper side of the post via; and forming a circuit layer connected to the post via on the upper surface of the film member.

Abstract: A method of manufacturing an electronic component includes forming a resin layer over an underlying layer, pressing a conductor plate including a pattern formed on one major surface thereof against the resin layer, and embedding the pattern in the resin layer, and performing polishing, Chemical Mechanical Polishing, or cutting by the use of a diamond bit on another major surface of the conductor plate until the resin layer appears, and leaving the pattern in the resin layer as a conductor pattern.

Abstract: A method for making an electronic device includes forming an interconnect layer stack on a rigid wafer substrate having a plurality of patterned electrical conductor layers, a dielectric layer between adjacent patterned electrical conductor layers, and at least one solder pad on an uppermost patterned electrical conductor layer. An LCP solder mask having at least one aperture therein alignable with the at least one solder pad is formed. The LCP solder mask and interconnect layer stack are aligned and laminated together. Solder is positioned in the at least one aperture. At least one circuit component is attached to the at least one solder pad using the solder.

Abstract: A transparent thin plate including a transparent substrate in a sheet form, a mesh layer formed on a surface of the transparent substrate and made of an opaque material having a structure wherein an outline of meshes is made of bands that are very thin and have a substantially equal width, and having a light transmittance of 50% or more. The transparent thin plate also includes a colored layer that is arranged in a state in which the colored layer is laminated in a partial area of the mesh layer and on the surface of the mesh layer, and has a color different from that of the opaque material constituting the mesh layer.

Abstract: Disclosed herein are a heat-dissipating substrate and a fabricating method thereof. The heat-dissipating substrate includes a plating layer divided by a first insulator formed in a division area. A metal plate is formed on an upper surface of the plating layer and filled with a second insulator at a position corresponding to the division area, with an anodized layer formed on a surface of the metal plate. A circuit layer is formed on the anodized layer which is formed on an upper surface of the metal plate. The heat-dissipating substrate and fabricating method thereof achieves thermal isolation by a first insulator formed in a division area and a second insulator.

Abstract: A fine pitch interposer structure includes a Multi-core base substrate and a plurality of buildup laminates. A surface of each Multi-core base substrate has a first circuit layer, and a second circuit layer which is electrically connected to the first circuit layer. The buildup laminates are stacked on the surface of the Multi-core base substrate. Each buildup laminate includes a photosensitive dielectric layer, and a plurality of blind vias with a pre-determined interval therebetween which are correspondingly arranged on each of the plurality of vias formed on the photosensitive dielectric layer. The blind vias are electrically connected to the first circuit layer. At least one blind via of one buildup laminate is superimposed on another blind via of another buildup laminate.

Abstract: A device-embedded flexible printed circuit board (FPCB) and a method of manufacturing the device-embedded FPCB are provided. The device-embedded FPCB includes: a first conductive layer; a first insulating layer which is disposed on the first conductive layer and includes at least one bump hole and at least one groove; a first plating layer which is formed in the at least one groove of the first insulating layer; and a device which includes at least one bump which is inserted into the at least one bump hole to be connected to the first conductive layer.

Abstract: A conductive member including: a base material; and a conductive layer disposed on the base material, wherein the conductive layer includes: a metal nanowire including a metal element (a) and having an average minor axis length of 150 nm or less; and a sol-gel cured product obtained by hydrolyzing and polycondensing an alkoxide compound of an element (b) selected from the group consisting of Si, Ti, Zr, and Al; and a ratio of the substance amount of the element (b) contained in the conductive layer to the substance amount of the metal element (a) contained in the conductive layer is in a range of from 0.10/1 to 22/1.

Abstract: The present invention relates to a method for forming solder resist and a substrate for a package. The method for forming solder resist including: forming a first solder resist inner region by primarily coating, exposing, and developing a solder resist on a substrate on which an outer PoP pad and an inner chip pad are formed, and removing the solder resist's outer portion on the substrate's outer region and curing the solder resist's inner portion on the substrate's inner region; forming a plugged SR region which does not expose the substrate; changing a surface roughness by performing a desmear process on a surface of the first solder resist inner region in which the plugged SR region is formed; and forming a second solder resist SMD region which covers an edge of the PoP pad, exposing, and developing the solder resist on the substrate after the desmear process is provided.

Abstract: A substrate on which LEDs are to be mounted to form an element row and which includes a first line and a second line disposed such that the element row is interposed therebetween. The first line includes a first main line portion extending mainly in the row direction of the element row, and a first connecting portion including a portion for connecting to the LEDs. The second line includes a second main line portion extending mainly in the row direction of the element row, and a second connecting portion including a portion for connecting to the LEDs. The gap between the first main line portion and the second main line portion is larger at LED mounting positions than at positions other than the LED mounting positions.

Abstract: An electronic part includes a first electronic member having a wiring side. An anisotropic conductive sheet has a first side and a second side opposite to the first side and is disposed on the first electronic member so that the wiring side contacts the first side. A second electronic member has a third side and a fourth side opposite to the third side and is disposed on the anisotropic conductive sheet so that the second side contacts the third side. The second electronic member is electrically connected to the first electronic member through the anisotropic conductive sheet. An elastic body has a fifth side and a sixth side opposite to the fifth side and is disposed on the second electronic member so that the fourth side contacts the fifth side. A pressing member is disposed on the sixth side of the elastic body.

Abstract: A substrate with a transparent conductive layer includes a transparent supporting substrate, a thermosetting resin layer containing 50% by weight or more of a melamine resin, and a carbon nanotube conductive layer in this order, wherein a value of linearity of resistance of the carbon nanotube conductive layer is 1.5% or less.

Abstract: The semiconductor device 1 includes a substrate 3, a semiconductor chip 4 mounted on the substrate 3, the substrate 3, a bump 5 connecting the substrate 3 and the semiconductor chip 4, and an underfill 6 filling in around the bump 5. In the case of a bump 5 composed of a high-melting-point solder having a melting point of 230° C. or more, the underfill 6 is composed of a resin material having an elastic modulus in the range of 30 MPa to 3000 MPa. In the case of a bump 5 composed of a lead-free solder, the underfill 6 is composed of a resin material having an elastic modulus in the range of 150 MPa to 800 MPa. An insulating layer 311 of buildup layers 31 of the substrate 3 has a linear expansion coefficient of 35 ppm/° C. or less in the in-plane direction of the substrate at temperatures in the range of 25° C. to the glass transition temperature.

Abstract: The present invention relates to a metal foil laminated polyimide resin substrate wherein a metal foil is directly laminated on one side or both sides of a polyimide resin substrate; and the surface of the metal foil to be bonded to the polyimide resin substrate has a surface roughness (Rzjis) of 3.0 ?m or less; a surface area ratio (B) of 1.25 to 2.50, in which the surface area ratio (B) is calculated as a ratio [A/6550] of a surface area of a two-dimensional region with a surface area of 6550 ?m2 which is determined by a laser method (three-dimensional area: A ?m2) to the area of the two-dimensional region; and a chromium content per unit area of the two-dimensional region of 2.0 mg/m2 or more.

Abstract: The present invention relates to a method for providing a reflective coating (114) to a substrate (104) for a light-emitting device (112), comprising the steps of: providing (201) a substrate (104) having a first surface portion (116) with a first surface material and a second surface portion (106, 108) with a second surface material different from the first surface material; applying (202) a reflective compound (401) configured to attach to said first surface material to form a bond with the substrate (104) in the first surface portion (116) that is stronger than a bond between the reflective compound (401) and the substrate (104) in the second surface portion (106, 108); curing (203) said reflective compound (401) to form a reflective coating (114) having said bond between the reflective coating (114) and the substrate (104) in the first surface portion (116); and subjecting said substrate (104) to a mechanical treatment with such an intensity as to remove (205) said reflective coating (114) from said secon

Abstract: A power module substrate includes: a ceramics substrate composed of AlN, having a top face; a metal plate composed of pure aluminum and joined to the top face of the ceramics substrate with a brazing filler metal including silicon interposed therebetween; and a high concentration section formed at a joint interface at which the metal plate is joined to the ceramics substrate, having a silicon concentration that is more than five times the silicon concentration in the metal plate.

Abstract: An electromagnetic bandgap structure including: at least three conductive plates; a first stitching via, configured to electrically connect any one of the conductive plates to another conductive plate; and a second stitching via, configured to electrically connect the one conductive plate to yet another conductive plate, wherein the first stitching via electrically connects the one conductive plate to another conductive plate by allowing a part of the first stitching via to be connected through a planar surface above or below the one conductive plate, and the second stitching via electrically connects the one conductive plate to yet another conductive plate by allowing a part of the second stitching via to be connected through a planar surface that is different from the planar surface through which the part of the first stitching via is connected, the two planar surfaces being placed in a same direction based on the conductive plates.

Abstract: A method for manufacturing a printed wiring board includes forming a metal film on a surface of an insulative board, a plating resist on the metal film, and a plated-metal film on the metal film exposed from the plating resist, covering a portion of the plated-metal film with an etching resist, etching to reduce thickness of the plated-metal film exposed from the etching resist, removing the etching and plating resists, and forming a wiring having a pad for wire-bonding an electrode of an electronic component and a conductive circuit thinner than the pad by removing the metal film exposed after the plating resist is removed, a solder-resist layer on the surface of the board and wiring, an opening in the layer exposing the pad and a portion of the circuit contiguous to the pad, and a metal coating on the pad and portion of the circuit exposed through the opening.

Abstract: A silicon nitride sintered body, wherein in a silicon nitride substrate consisting of crystal grains of ?-type silicon nitride and a grain boundary phase containing at least one type of rare earth element (RE), magnesium (Mg) and silicon (Si), the grain boundary phase consists of an amorphous phase and a MgSiN2 crystal phase. The X-ray diffraction peak intensity of any crystal plane of a crystal phase containing the rare earth element (RE) is less than 0.0005 times the sum of the diffraction peak intensities of (110), (200), (101), (210), (201), (310), (320) and (002) of the crystal grains of the ?-type silicon nitride; and the X-ray diffraction peak intensity of (121) of the MgSiN2 crystal phase is 0.0005 to 0.003 times the sum of the X-ray diffraction peak intensities of (110), (200), (101), (210), (201), (310), (320) and (002) of the crystal grains of the ?-type silicon nitride.

Abstract: There is provided an interconnection structure. An interconnection structure according to an aspect of the invention may include: a plurality of side portions provided on one surface of a substrate part and a plurality of cavities located between the side portions and located further inward than the side portions; and electrode pattern portions provided on surfaces of the side portions and the cavities.

Abstract: A submount with an electrode layer having excellent wettability in soldering and method of manufacturing the same are disclosed. A submount (1) for having a semiconductor device mounted thereon comprises a submount substrate (2), a substrate protective layer (3) formed on a surface of the submount substrate (2), an electrode layer (4) formed on the substrate protective layer (3) and a solder layer (5) formed on the electrode layer (3) wherein the electrode layer (4) is made having an average surface roughness of less than 1 ?m. The reduced average surface roughness of the electrode layer (4) improves wettability of the solder layer (5), allowing the solder layer (5) and a semiconductor device to be firmly bonded together without any flux therebetween. A submount (1) is thus obtained which with the semiconductor device mounted thereon is reduced in heat resistance, reducing its temperature rise and improving its performance and service life.

Abstract: Disclosed herein are an adhesive member for manufacturing a printed circuit board, a printed circuit board, and a method of manufacturing the same. The printed circuit board includes a base substrate, an insulating layer formed on the base substrate, a primer layer formed on the insulating layer, and a circuit layer formed on the primer layer.

Abstract: A high quality component-incorporated substrate achieves a sufficient connection between an in-plane electrode and an interlayer connection conductor at low cost. A method of forming a hole for an interlayer connection conductor of a resin substrate includes a step of forming an in-plane electrode in a core substrate, a step of forming a light reflective conductor for reflecting a laser beam applied on the in-plane electrode in a later step, a step of forming a resin layer so as to cover the core substrate, the in-plane electrode and the light reflective conductor, and a step of forming a hole for the interlayer connection conductor by removing the resin layer on the light reflective conductor through the use of a laser beam.

Abstract: A noise dampening energy efficient circuit board includes a carbon material layer for dampening electromagnetic interference between surface mount components and trace patterns of the circuit board. One or more ground plane layers are arranged relative to the carbon material layer to cooperatively dampen and repel noise of varying frequencies. The positioning of the carbon material layer with respect to the ground plane layer enhances the ground plane operation. Glass fiber material layers and other insulating dielectric layers are disposed at particular locations within the noise dampening energy efficient circuit board. The carbon material layer and the ground plane layer dampen electromagnetic noise, thereby permitting energy saving design considerations, increasing energy efficiencies and reducing power consumption. Mounting posts of the surface mount components include insulating sleeves to selectively insulate different layers of the circuit board from surface mount components.

Abstract: A transparent conductive film which comprises: a substrate composed of a non-crystalline polymer film; a first hard coating layer; a first transparent conductor layer; a first metal layer; a second hard coating layer; a second transparent conductor layer; and a second metal layer. The first hard coating layer includes a binder resin and a plurality of particles. And the second hard coating layer includes a binder resin and a plurality of particles. The first metal layer has a plurality of projections on a surface thereof and the second metal layer has a plurality of projections on a surface thereof.

Abstract: The present invention provides a multilayer rigid flexible printed circuit board including: a flexible region including a flexible film having a circuit pattern formed on one or both surfaces thereof and a laser blocking layer formed on the circuit pattern; and a rigid region formed adjacent to the flexible region and including a plurality of pattern layers on one or both surfaces of extended portions extended to both sides of the flexible film of the flexible region, and a method for manufacturing the same.

Abstract: An electroconductive ink made with metallic nanoparticles is disclosed. The ink contains an organophosphorus acid that increases adhesion between the deposited metallic layer and the substrate to which the metallic layer is applied.

Abstract: A glass-ceramic substrate with improved bonding strength between an insulating and ferrite layer, and method of manufacturing same are disclosed. The glass-ceramic substrate comprises a glass-ceramic layer, a ferrite layer, and interlayer means between the glass-ceramic layer and the ferrite layer. The glass-ceramic layer comprises a glass phase and a glass comprising a first crystal. The ferrite layer comprises a ferrite crystal.

Abstract: This publication discloses an electronics module and a method for manufacturing it. The electronic module includes at least one first embedded component (6), the contact terminals (7) of which face essentially towards the first surface of the insulating-material layer (1) and which is connected electrically by its contact terminals (7) to the conductor structures contained in the electronic module. According to the invention, a second embedded component (6?), the contact terminals (7?) of which face essentially towards the second surface of the insulating-material layer and which is connected electrically by its contact terminals (7?) to the conductor structures contained in the electronic module, is attached by means of glue or two-sided tape to the first component (6), and the contact terminals (7, 7?) are connected to the conductor structures with the aid of a conductive material, which is arranged in the insulating-material layer in holes (17) at the locations of the contact terminals (7, 7?).

Abstract: The circuit-connecting material for connection between circuit members each having a board and a circuit electrode formed on the primary surface of the board, comprising an adhesive composition that cures in response to light or heat and an organic compound containing a urethane group and an ester group.

Abstract: Provided is an ultra-thin copper foil to which a carrier foil is attached, including: a carrier foil, a peeling layer, and an ultra-thin copper foil, wherein the peeling layer includes a first metal A having peelability, a second metal B and a third metal C facilitating coating of the first metal, wherein the amount (a) of the first metal A is in a range of about 30 to about 89% by total weight of the peeling layer, the amount (b) of the second metal B is in a range of about 10 to about 60% by total weight of the peeling layer, and the amount (c) of the third metal C is in a range of about 1 to about 20% by total weight of the peeling layer.

Abstract: A circuit subassembly, comprising: a conductive layer, a dielectric layer formed from a thermosetting composition, wherein the thermosetting composition comprises, based on the total weight of the thermosetting composition a polybutadiene or polyisoprene resin, about 30 to about 70 percent by weight of a magnesium hydroxide having less than about 1000 ppm of ionic contaminants, and about 5 to about 15 percent by weight of a nitrogen-containing compound, wherein the nitrogen-containing compound comprises at least about 15 weight percent of nitrogen; and an adhesive layer disposed between and in intimate contact with the conductive layer and the dielectric layer, wherein the adhesive comprises a poly(arylene ether), wherein the circuit subassembly has a UL-94 rating of at least V-1.

Abstract: A chip stacking structure including a carrier, a first redistribution layer, a second redistribution layer, at least one first chip, at least one second chip, and at least one conductor is provided. The carrier has a first surface and a second surface opposite to each other. The carrier has at least one through hole. The first and second redistribution layers are disposed on the first and second surfaces of the carrier, respectively. The first and second chips are disposed on the first and second surfaces of the carrier and electrically connected with the first and second redistribution layers, respectively. The conductor is disposed on one of the first and second chips. The conductor is disposed in the through hole. The first and second chips are electrically connected by the conductor. A gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.

Abstract: A spontaneous emission display includes a support, a first electrode section provided on the support and having a fine wire structure portion made of a conductive metal and a translucent conductive film, and a display section formed on the first electrode section and having a light-emitting layer. The volume resistance of the fine wire structure portion of the first electrode is 10?4 ?·cm or less and/or the surface resistance thereof is 100 ?/sq or less. The volume resistance of the conductive film is 0.05 ?·cm or more and/or the surface resistance thereof is 100 ?/sq or more. When the surface resistance of the first electrode section before a bending test is denoted by R1 and that after the bending test is denoted by R2, R2/R1<18 is satisfied.

Abstract: The present invention is directed to enhancing the bonding reliability of a bonding portion between an Al electrode of a semiconductor device and a bonding material having metal particles as a main bonding agent. In the semiconductor device, a semiconductor element and an Al electrode are connected to each other with a bonding layer made of Ag or Cu interposed therebetween, and the bonding layer and the Al electrode are bonded to each other with an amorphous layer interposed therebetween. It is possible to obtain excellent bonding strength to the Al electrode by performing a bonding process in atmospheric air by using a bonding material including a metal oxide particle with an average diameter of 1 nm to 50 ?m, an acetic acid- or formic acid-based compound, and a reducing agent made of an organic material.

Abstract: An electrical connector is provided for mating with an electrical component. The connector includes a substrate having a mating side, and a solder column extending from the mating side of the substrate. The solder column includes a base that is engaged with the substrate. The solder column extends a length away from the mating side of the substrate to a tip. The tip includes a contact surface that is configured to engage and electrically connect to an electrical contact of the electrical component. The solder column is linearly tapered along at least a portion of the length from the base to the tip.

Abstract: A printed wiring board is formed by adhering a coverlay film having a resistance layer formed on a surface of the coverlay film body to a printed wiring board body having a conductive layer formed on a surface of a substrate through an adhesive layer. The resistance layer is separated from and opposed to the conductive layer through the adhesive layer.

Abstract: Provided is printed circuit board for minimizing dielectric losses experienced by a low-current portion of an electric circuit. The printed circuit board includes a first substrate supporting an electrically-conductive material patterned to form a conductive pathway between electric circuit components, and a surface-mount guard pad provided on a substantially-planar exposed surface of the first substrate and covering at least an area of the exposed surface including a footprint of the low-current portion on the first substrate. A second substrate is also provided with one or more electrically conductive pads that are surface mounted to the guard pad to couple the second substrate to the guard pad. The second substrate also supports a signal trace included in the low-current region for conducting a low-current signal.

Abstract: In a wiring board according to the present invention, a substrate, a solder resist provided on the substrate, a land, a wiring line, and a connection portion connecting the wiring line and the land, the connection portion is provided with a recess as a non-flat portion, and is formed to comprise a width greater than a width of the wiring line and smaller than a width (diameter) of the land, the width of the connection portion being gradually increased from the wiring line toward the land.

Abstract: A circuitized substrate in which three conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to two dielectric layers. Each of the foil surfaces which physically bond to a respective dielectric layer are smooth (e.g., preferably by chemical processing) and may include a thin, organic layer thereon. One of the conductive layers may function as a ground or voltage (power) plane while the other two may function as signal planes with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided, as is a method of making the substrate.

Abstract: A printed circuit board and a manufacturing method of the same are disclosed. The method includes: preparing a carrier including a primer resin layer formed thereon; forming a circuit pattern on the primer resin layer; stacking the carrier onto an insulating layer such that the circuit pattern is buried in the insulating layer; removing the carrier; forming a via hole in the insulating layer on which the primer resin layer is stacked; and forming a conductive via in the via hole. The conductive via is formed by forming a plating layer in the via hole and on the primer resin layer and removing a portion of the plating layer formed over the primer resin layer.

Abstract: In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.

Abstract: When a formed position of a via formed on a board is the same as a position of a footprint of a chip component located on the back surface of the board corresponding to an area on which a BGA is mounted, a board designing apparatus determines that the chip component and the BGA can be connected using chip on hole. When it is determined that the chip component and the BGA can be connected, the board designing apparatus carries out chip on hole by forming a via in an area of the board on which the BGA is mounted, the via leading to the footprint of the chip component located on the back surface of the board.

Abstract: A wired circuit board assembly sheet has a plurality of wired circuit boards, distinguishing marks for distinguishing defectiveness of the wired circuit boards, and a supporting sheet for supporting the plurality of wired circuit boards and the distinguishing marks. Each of the distinguishing marks has an indication portion for indicating a specified one of the wired circuit boards.