Adhesive/bonding Patents (Class 174/259)
  • Patent number: 9190381
    Abstract: An insulating adhesive film is formed by laminating a first insulating adhesive layer which contains a filler in an insulating adhesive composition and a second insulating adhesive layer which contains no filler in an insulating adhesive composition. H/2<Tf<H?Tf+Tn is satisfied, wherein H is the height of the bump of the IC chip, Tf is the thickness of the first insulating adhesive layer, and the Tn is the thickness of the second insulating adhesive layer. The side of the substrate on which an electrode is formed and the side of an IC chip on which a bump is formed are connected via the insulating adhesion film arranged such that the first insulating adhesive layer and the electrode-forming side of the electronic component are opposed to thereby connect the electrode of the substrate and the bump of the IC chip.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: November 17, 2015
    Assignee: DEXERIALS CORPORATION
    Inventor: Ryoji Kojima
  • Patent number: 9111847
    Abstract: A method for manufacturing a chip package is provided. The method includes forming a layer over a carrier; forming further carrier material over the layer; selectively removing one or more portions of the further carrier material thereby releasing one or more portions of the layer from the further carrier material; and adhering a chip including one or more contact pads to the carrier via the layer.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: August 18, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Georg Meyer-Berg
  • Patent number: 9078365
    Abstract: Disclosed is a resin composition which is advantageous not only in that the resin composition can be produced at low cost, but also in that it is unlikely to thermally expand, and a prepreg, a laminate, and a wiring board formed using the resin composition. The resin composition comprises an insulating resin having an aromatic ring, wherein the insulating resin having an aromatic ring has a molecular weight between crosslinking sites of 300 to 1,000 on the stage after the production of the laminate, as determined from an elastic shear modulus of the insulating resin measured at a temperature of Tg or higher.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: July 7, 2015
    Assignee: HITACHI CHEMICAL CO., LTD.
    Inventors: Koji Morita, Shin Takanezawa, Kazunaga Sakai, Yuusuke Kondou
  • Patent number: 9040839
    Abstract: A wiring body connection structure includes a first wiring body and a second wiring body, the first wiring body having a first base material made of an elastomer and a first wiring containing an elastomer and a conductive material, the second wiring body having a second base material and a second wiring. In the wiring body connection structure, a laminated section is partitioned where a first end of the first wiring body and a second end of the second wiring body overlap in a front-rear direction. The wiring body connection structure further includes a cover member arranged on a front surface of the first wiring body, and a conductive adhesive layer bonding the first end and the second end in the laminated section while ensuring a conductive property. The cover member is interposed between a frontmost end of the second end and the first wiring in the laminated section.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: May 26, 2015
    Assignee: SUMITOMO RIKO COMPANY LIMITED
    Inventors: Lei Zhu, Motoyuki Furuta
  • Publication number: 20150136460
    Abstract: A transparency having a bus bar system includes a non-conductive substrate having a major surface. At least one conductive coating is located over at least a portion of the major surface. An electrically conductive adhesive, such as an isotropically conductive tape or film, is located over at least a portion of the conductive coating. A metallic member, such as a metallic foil or metallic braid, is located over the isotropically conductive adhesive.
    Type: Application
    Filed: January 5, 2015
    Publication date: May 21, 2015
    Inventor: John R. Short
  • Publication number: 20150136461
    Abstract: A solder alloy of a tin-silver-copper solder alloy, containing tin, silver, antimony, bismuth, copper, and nickel, and substantially does not contain germanium, relative to the total amount of the solder alloy, the silver content is more than 1.0 mass % and less than 1.2 mass %, the antimony content is 0.01 mass % or more and 10 mass % or less, and the bismuth content is 0.01 mass % or more and 3.0 mass % or less.
    Type: Application
    Filed: June 25, 2013
    Publication date: May 21, 2015
    Inventors: Yoji Imamura, Kazuki Ikeda, JinYu Piao, Tadashi Takemoto
  • Patent number: 9035192
    Abstract: An anisotropic conductive adhesive composite and film include a binder and conductive particles dispersed in the binder. The conductive particles include a copper core particle and a metal coating layer coated on a surface of the corresponding copper core particle.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: May 19, 2015
    Assignee: CHEIL INDUSTRIES, INC.
    Inventors: Gyu Ho Lee, Young Woo Park, Il Rae Cho, Young Hun Kim, Kyoung Soo Park, Jin Seong Park, Dong Seon Uh, Kyung Jin Lee, Kwang Jin Jung
  • Patent number: 9024203
    Abstract: A method for manufacturing an embedded printed circuit board includes the following steps. First, a circuit substrate is provided. The circuit substrate includes a base, a first wiring layer, and a second wiring layer. The first wiring layer includes a number of electrode connection wires. Second, an opening is defined in the circuit substrate. The opening passes through the base and the second wiring layer. Third, an anisotropic conductive film is adhered onto the electrode connection wires in the opening. Fourth, an electrical element including many electrodes is provided. Fifth, the electrical element is arranged in the opening, with the electrodes respectively spatially correspond to the electrode connection wires, and each electrode is electrically connected to the corresponding electrode connection wire through the anisotropic conductive film, thereby obtaining an embedded printed circuit board.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: May 5, 2015
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventor: Chien-Kuang Lai
  • Patent number: 9021693
    Abstract: A method of manufacturing a printed circuit board, including: applying a dry film on a carrier and then patterning the dry film to form holes for forming metal bumps; forming an upper circuit layer including metal bumps charged in the holes and connection pads on the dry film; forming an insulation layer on the dry film; forming a build-up layer including a lower circuit layer on the insulation layer; removing the carrier; and removing the dry film.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: May 5, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jin Yong An, Jae Joon Lee
  • Patent number: 9012785
    Abstract: A flexible multilayer substrate includes a multilayer body including a plurality of laminated resin layers. The multilayer body includes an innermost surface, which is a surface on an inner side when the substrate is bent, and an outermost surface, which is a surface on an outer side when the substrate is bent. Each of the plurality of resin layers includes a skin layer on one surface. Lamination of the multilayer body includes a skin layer joint plane at one location at a central portion in the thickness direction, and the skin layer and other surface come in contact with each other at another location along the central portion in the thickness direction. A skin layer joint plane is arranged on a side closer to the innermost surface than a central plane in the thickness direction of the multilayer body.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: April 21, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yoshihito Otsubo
  • Patent number: 9012783
    Abstract: A brazing material includes silver and copper as main components; at least one element A selected from indium, zinc, and tin; at least one element B selected from titanium, zirconium, hafnium, and niobium; and at least one element C selected from molybdenum, osmium, rhenium, and tungsten. The content of copper is not less than 35% by mass and not more than 50% by mass, based on the total amount of silver, copper, and the elements A, B and C. A heat dissipation base includes a supporting substrate, circuit members on a first main surface of the substrate, and a heat dissipation member on a second main surface opposite to the first main surface. The circuit members are joined to the supporting substrate by a joining layer composed of the brazing material.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: April 21, 2015
    Assignee: Kyocera Corporation
    Inventors: Yuuichi Abe, Kiyotaka Nakamura, Kiyoshi Yakubo
  • Patent number: 9012787
    Abstract: An electronic board includes conducting traces having an upper surface at least partially sunken with respect to a gluing surface of the board. A surface mount technology electronic device for mounting to the board includes insulating windows that define gluing sites within one or more pins. An electronic system is formed by one or more of such surface mount technology electronic devices mounted to electronic board. The devices are attached using a wave soldering technique that flows through channels formed by the sunken conductive traces.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventors: Cristiano Gianluca Stella, Rosalba Cacciola
  • Publication number: 20150083469
    Abstract: A wiring board includes a substrate body provided with a through hole penetrating the substrate body from one surface to another surface; and a through wiring formed in the through hole and including a first metal layer formed on a part of an inner side surface of the through hole at the one surface side, a first wiring layer that covers the first metal layer to fill a part of the through hole at the one surface side, a second metal layer continuously formed on the rest part of the inner side surface of the through hole at the other surface side and on an end portion of the first wiring layer at the other surface side, and a second wiring layer that covers the second metal layer to fill a part of the through hole at the other surface side.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 26, 2015
    Inventors: Masahiro SUNOHARA, Yuichiro SHIMIZU
  • Patent number: 8986434
    Abstract: Compositions and methods for silver plating onto metal surfaces such as PWBs in electronics manufacture to produce a silver plating which is greater than 80 atomic % silver, tarnish resistant, and has good solderability.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: March 24, 2015
    Assignee: Enthone Inc.
    Inventors: Yung-Herng Yau, Thomas B. Richardson, Joseph A. Abys, Karl F. Wengenroth, Anthony Fiore, Chen Xu, Chonglun Fan, John Fudala
  • Patent number: 8987606
    Abstract: Provided herein are technologies generally relating to creating connections and/or associations. In some examples, the embodiments can relate to a circuit that includes a surface, a first electrical contact that is attached to the surface, a glass substrate, a second electrical contact that is attached to the glass substrate, and at least one elastomer layer. In some embodiments, the elastomer layer can provide or assist in creating a contact between the first electrical contact and the second electrical contact.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: March 24, 2015
    Assignee: Empire Technology Development LLC
    Inventor: Eehern Jay Wong
  • Patent number: 8987607
    Abstract: To provide a conductive particle, which contains a core particle, and a conductive layer formed on a surface of the core particle, where the core particle is formed of a resin, or a metal, or both thereof, and the conductive layer contains a phosphorus-containing hydrophobic group at a surface thereof.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: March 24, 2015
    Assignee: Dexerials Corporation
    Inventors: Hiroki Ozeki, Tomoyuki Ishimatsu, Reiji Tsukao
  • Patent number: 8980417
    Abstract: A production process for producing a glass fiber fabric that has good smoothness and is excellent in resin impregnation property is provided wherein glass fiber yarns are woven to obtain a glass fiber fabric.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: March 17, 2015
    Assignee: Nitto Boseki Co., Ltd.
    Inventor: Kazutaka Adachi
  • Patent number: 8975525
    Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kevin Bills, Mahesh Bohra, Jinwoo Choi, Tae Hong Kim, Rohan Mandrekar
  • Patent number: 8974626
    Abstract: A method of manufacturing a micro structure, includes the steps of: preparing separate first and second substrates, the first substrate having a first surface on which a first structural body having a first height and a second structural body having a second height greater than the first height of the first structural body are arranged, the second substrate having a second surface; then placing the first and second substrates to cause the first and second surfaces to face each other across the first and second structural bodies; and then bonding the first and second substrates to each other while compressing the second structural body in a height direction thereof between the first and second surfaces to cause the second structural body to have a height defined by the first structural body.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: March 10, 2015
    Assignee: FUJIFILM Corporation
    Inventors: Takamichi Fujii, Akihiro Mukaiyama
  • Patent number: 8966748
    Abstract: The invention relates to a method for manufacturing an arrangement with a component on a carrier substrate, wherein the method encompasses the following steps: Manufacturing spacer elements on the rear side of a cover substrate, arranging a component on a cover surface of a carrier substrate, and arranging the spacer elements formed on the carrier substrate so as to situate the component in the at least one hollow space and close the latter. In addition, the invention relates to an arrangement, a method for manufacturing a semi-finished product for a component arrangement, as well as a semi-finished product for a component arrangement.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: March 3, 2015
    Assignee: MSG Lithoglas AG
    Inventors: J├╝rgen Leib, Simon Maus, Ulli Hansen
  • Patent number: 8953338
    Abstract: The invention discloses a curved display module and a display device. The curved display module includes an enclosure, at least one opening, a flexible display panel and an Optical Clear Adhesive (OCA) layer. There is a first curved surface inside the enclosure. A cavity is formed within the enclosure. The at least one opening are disposed on at least one edge of the enclosure and connected to the cavity. The flexible display panel is disposed on the first curved surface in the cavity. The OCA layer is disposed within the cavity. The OCA layer directly covers the flexible display panel.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: February 10, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Chi-Ming Wu, Wan-Tien Chen, Jen-Shiun Huang, Shin-Yi Hsieh, Chih-Hua Cheng
  • Patent number: 8952261
    Abstract: The present invention enables additional processes required for forming vertical wiring and rewiring in a double face package (DFP) or a wafer level chip size package (WLCSP) to be implemented through use of a component for vertical wiring and rewiring, to thereby simplify the manufacturing process and reduce cost. An electronic component for interconnection is incorporated into an electronic device package in which a circuit element including a semiconductor chip is disposed and which has external electrodes connected to the circuit element via vertical interconnects and horizontal interconnects.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: February 10, 2015
    Assignee: Kyushu Institute of Technology
    Inventors: Masamichi Ishihara, Minoru Enomoto, Shigeru Nomura
  • Patent number: 8941014
    Abstract: In one embodiment, an apparatus includes a cover panel. The apparatus also includes a first optically clear adhesive (OCA) layer coupled to the cover panel. The apparatus also includes a substrate coupled to the first OCA layer. The substrate has drive or sense electrodes of a touch sensor disposed on a first side. The substrate also has a first connection pad region. The first connection pad region includes a first outer zone, a second outer zone, and a first connection pad zone. The first OCA layer extends to portions of at least one of the first outer zone of the first connection pad region, the second outer zone of the first connection pad region, and the first connection pad zone of the first connection pad region.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: January 27, 2015
    Assignee: Atmel Corporation
    Inventor: David Brent Guard
  • Patent number: 8941016
    Abstract: A laminated wiring board, includes: a first substrate in which a conductor circuit is formed on one surface of an insulating layer and an adhesive layer is formed on an other surface of the insulating layer, and conductors are formed in via holes that pass through the insulating layer and the adhesive layer so that the conductor circuit is partially exposed therefrom; an electronic component electrically connected to the conductor circuit by allowing electrodes of the electronic component to be connected to the conductors; an embedding member arranged around the electronic components so that the electronic component is embedded therein; and a second substrate having an adhesive layer laminated to face the adhesive layer of the first substrate and sandwich the electronic component and the embedding member, wherein each of the electrodes of the electronic component is continuous with the conductor circuit through two or more of the conductors.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: January 27, 2015
    Assignee: Fujikura Ltd.
    Inventor: Masahiro Okamoto
  • Publication number: 20150021075
    Abstract: A surface mounting substrate for surface mounting an electronic part using a lead-free solder includes a joint portion of the substrate to which the electronic parts is joined; and a stress relaxation portion formed in a vicinity of the joint portion of the substrate.
    Type: Application
    Filed: October 2, 2014
    Publication date: January 22, 2015
    Inventors: Kokichi OKAMOTO, Takahiro TAGUCHI
  • Patent number: 8937255
    Abstract: A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: January 20, 2015
    Assignee: Hypres Inc.
    Inventor: Vladimir V. Dotsenko
  • Patent number: 8925193
    Abstract: A method, and apparatus resulting from the method, for fabricating a circuit board suitable for mounting electronic components. The method includes drilling a plurality of through-holes in a plurality of dielectric sheets, forming a conductive film on at least one side of each of the plurality of dielectric sheets, and substantially filling each of the plurality of through holes with a conductive material. The conductive material is both electrically and thermally uninterrupted from a first face to a second face of each of the plurality of dielectric sheets. The plurality of dielectric sheets are then sequentially mounted, one atop another, to form the circuit board. The sequential mounting step is performed after the steps of drilling the plurality of through-holes, forming the conductive layer, and substantially filling the plurality of through-holes.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: January 6, 2015
    Assignee: Advantest (Singapore) Pte Ltd
    Inventor: Romi O. Mayder
  • Patent number: 8927880
    Abstract: Disclosed herein are a printed circuit board, including an insulating layer; a circuit wiring formed on one surface or both surfaces of the insulating layer and made of a single metal layer; a via formed in the insulating layer for interconnecting the circuit wirings through the insulating layer; and a pad layer formed on one surface or both surfaces of the insulating layer and adhered to an end portion of the via, the pad layer being formed of a central portion extended from the via and an outside portion made of the same single metal layer as the circuit wiring, and a method for manufacturing the same.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 6, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Kyung Don Mun
  • Patent number: 8921703
    Abstract: A circuit board, structural units and a manufacturing method are provided, wherein one or more high temperature lamination processes are conducted for laminating the structural units and form a multi-layered circuit board.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: December 30, 2014
    Assignee: HTC Corporation
    Inventors: Chin-Wei Ho, Hui-Ling Tsai
  • Patent number: 8912450
    Abstract: A method for attaching a metal surface to a carrier is provided, the method including: forming a first polymer layer over the metal surface; forming a second polymer layer over a surface of the carrier; and bringing the first polymer layer into physical contact with the second polymer layer such that at least one of an interpenetrating polymer structure and an inter-diffusing polymer structure is formed between the first polymer layer and the second polymer layer.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: December 16, 2014
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Manfred Mengel, Khalil Hosseini, Franz-Peter Kalz
  • Patent number: 8895869
    Abstract: Electrode protective films 13a and 13b are formed on the surface of the metal layer using imidazole preflux, as terminal electrodes 35a and 35b of an electronic component. The terminal electrodes of an electronic component on which the protective films are formed are fixed by electroconductive adhesives 33a and 33b supplied to mounting lands 40a and 40b. Thereby an electronic component mounting structure without change in resistance caused by electroconductive adhesives is provided.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: November 25, 2014
    Assignee: Koa Corporation
    Inventor: Toshifumi Mizokami
  • Patent number: 8895866
    Abstract: A printed circuit board structure includes a plurality of circuit layer plates stacked together in which each of the stacked circuit layer plates includes an epoxy resin plate body and a fabric structure completely encapsulated in the epoxy resin plate body, and each circuit layer plate stacked between two circuit layer plates is further provided with filler particles distributed in its epoxy resin plate body, and the two opposite and outermost circuit layer plates thereof have metal soldering pads on the outer surfaces of the epoxy resin plate body thereof, and the two opposite and outermost circuit layer plates do not have the filler particles in its epoxy resin plate body thereof.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: November 25, 2014
    Assignees: Quanta Computer Inc., Tech-Front (Shanghai) Computer Co., Ltd.
    Inventors: Steven Wang, Jin-Chang Wu, Mide Yang
  • Patent number: 8889995
    Abstract: To reduce the RF losses associated with high RF loss plating, such as, for example, Ni/Pd/Au plating, the solder mask is reconfigured to prevent the edges and sidewalls of the wire-bond areas from being plated in some embodiments. Leaving the edges and sidewalls of the wire-bond areas free from high RF loss plating, such as Ni/Pd/Au plating, provides a path for the RF current to flow around the high resistivity material, which reduces the RF signal loss associated with the high resistivity plating material.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: November 18, 2014
    Assignee: Skyworks Solutions, Inc.
    Inventors: Weimin Sun, Peter J. Zampardi, Hongxiao Shao
  • Patent number: 8878075
    Abstract: Providing a connecting structure for connecting first electrodes formed on the upper surface of a first substrate to second electrodes formed on the upper surface of a second substrate glued on the upper surface of the first substrate by an electrically conductive member, wherein the second substrate is smaller in its outer size than the first substrate, the first electrodes are arranged on the first substrate around the periphery of the second substrate, a gap is formed between the first and second substrates at the peripheral edge of the second substrate, an insulating resin is arranged near the first electrodes so as to cover portions of the side surfaces of the second substrate and to fill the gap between the first and second substrates, and the electrically conductive member is arranged over regions leading from the first electrodes through the insulating resin to the second electrodes.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: November 4, 2014
    Assignee: NLT Technologies, Ltd.
    Inventor: Akira Fujita
  • Patent number: 8877878
    Abstract: A sulfonium borate complex that is capable of reducing the amount of fluorine ions generated during thermal cationic polymerization, and is capable of providing a thermal cationic polymerizable adhesive with low-temperature fast curing properties is represented by a structure represented by the formula (1). In the formula (1), R1 is an aralkyl group, R2 is a lower alkyl group, and R3 is a lower alkoxycarbonyl group. X is a halogen atom, and n is an integer of from 1 to 3.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: November 4, 2014
    Assignee: Dexerials Corporation
    Inventors: Yoshihisa Shinya, Jun Yamamoto, Ryota Aizaki, Naoki Hayashi, Misao Konishi, Yasuhiro Fujita
  • Publication number: 20140318840
    Abstract: An embodiment of a stacked structure includes: a first substrate that includes a first electrode; a second substrate that includes a second electrode; and an adhesive resin material that is provided between the first substrate and the second substrate and includes a plurality of conductive vias, the plurality of conductive vias electrically connecting the first electrode and the second electrode.
    Type: Application
    Filed: March 21, 2014
    Publication date: October 30, 2014
    Applicant: FUJITSU LIMITED
    Inventor: TAKASHI KANDA
  • Patent number: 8869387
    Abstract: Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in accordance with one embodiment includes a support member having first package bond sites electrically coupled to leadframe bond sites. A microelectronic die can be carried by the support member and electrically coupled to the first packaged bond sites. A leadframe can be attached to the leadframe bond sites so as to extend adjacent to the microelectronic die, with the die positioned between the leadframe and the support member. The leadframe can include second package bond sites facing away from the first package bond sites. An encapsulant can at least partially surround the leadframe and the microelectronic die, with the first and second package bond sites accessible from outside the encapsulant.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Chin Hui Chong, Choon Kuan Lee, David J. Corisis
  • Patent number: 8861214
    Abstract: Substrates for integrated passive devices are described herein. Embodiments of the present invention provide substrates including a glass layer and at least one passive device disposed thereon. According to various embodiments of the present invention, the glass layer may have a thickness adapted to minimize conductive and/or other interactions between the substrate and the at least one passive device. Other embodiments may be described and claimed.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 14, 2014
    Assignee: Marvell International Ltd.
    Inventors: Albert Wu, Chuan-Cheng Cheng
  • Publication number: 20140300832
    Abstract: An electronic device may have structures that are coupled together using conductive adhesive such as anisotropic conductive film and other adhesives. The structures that are coupled together may include a touch sensor structure formed from electrodes on the inner surface of a display cover layer, a display module having display layers such as a thin-film transistor layer, and circuitry mounted on substrates such as printed circuits. Conductive signal path structures may be used in routing signals within the electronic device. The conductive signal path structures may be formed from pins that are embedded within injection molded plastic, from metal traces such as laser-deposited metal traces that are formed on the surface of a plastic member or other dielectric, from metal structures that run within channels in a plastic, printed circuit traces, and other signal path structures.
    Type: Application
    Filed: April 8, 2013
    Publication date: October 9, 2014
    Applicant: Apple Inc.
    Inventor: Apple Inc.
  • Patent number: 8854827
    Abstract: An electronic control unit is configured in such a way that the groove-shaped concave portion of the second case member includes a first concave portion, in which a groove width at a bottom surface side is narrow, and a second concave portion, in which a groove width at an aperture surface side is wide, and the first concave portion and the second concave portion are linked by an inclined step portion in such a way that a groove width at the step portion is increased in a direction from the bottom surface side to the aperture surface side, and moreover, a tip of the rail-shaped convex portion of the first case member is fitted into the first concave portion at the bottom surface side of the second case member.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: October 7, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takaaki Tanaka, Yasuhiro Takahashi, Toru Kubo, Seiji Kato, Hideki Umemoto
  • Patent number: 8851621
    Abstract: A liquid ejecting head has a flow channel substrate, an actuator formed on the flow channel substrate and having at least one mount, and a flexible wiring substrate electrically connected to the mount to supply a drive signal to the actuator. The mount of the actuator and the wiring substrate are bonded together using an epoxy adhesive agent containing p-aminophenol epoxy resin, bisphenol A epoxy resin, and bisphenol F epoxy resin.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: October 7, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Masahiko Sato, Munehide Kanaya, Toshinobu Yamazaki
  • Publication number: 20140287299
    Abstract: A heat-debonding adhesive member is provided. The heat-debonding adhesive member attaches electronic device components such as a battery and a housing together. The heat-debonding adhesive includes a heat-generating layer that generates heat for debonding structures that are attached together using the adhesive member. The heat-generating layer includes a conductive layer that generates heat when a current flows through the conductive layer. The heat-debonding adhesive includes additional adhesive layers such as a voided polymer film having air-filled voids and one or more pressure-sensitive adhesive layers. A debonding tool provides current to conductive contacts on the conductive layer for generating heat in the heat-generating layer when it is desired to debond the structures that are attached together using the adhesive member.
    Type: Application
    Filed: March 25, 2013
    Publication date: September 25, 2014
    Applicant: Apple Inc.
    Inventor: James R. Krogdahl
  • Patent number: 8842440
    Abstract: A method for manufacturing a printed circuit board includes forming an opening portion in a substrate, positioning chip capacitors in the opening portion of the substrate such that the chip capacitors are accommodated in the opening portion of the substrate, forming a buildup structure including an interlayer resin insulating layer and a conductive layer over a surface of the substrate and the chip capacitors accommodated in the opening portion of the substrate, and forming on a surface of the buildup structure bump structures positioned to mount an IC chip such that the chip capacitors in the opening portion of the substrate are positioned directly below the IC chip.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: September 23, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 8835770
    Abstract: An electronic component that includes an electronic component body, sealing members sealing the electronic component body, and adhesive layers which adhere the electronic component body and the sealing members, respectively. Between the electronic component body and the sealing members, sealed spaces are formed, respectively. The adhesive layers each contain organic fillers and inorganic fillers. The organic fillers are in contact with both the electronic component body and the sealing members. The inorganic fillers each have a minimum particle diameter smaller than the thickness of each of the adhesive layers. When the adhesive layers are viewed in a thickness direction thereof, the inorganic fillers are provided between the organic fillers and the electronic component body and between the organic fillers and each of the sealing members.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: September 16, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Junji Oyama, Takamasa Kuboki, Yasuharu Matsui, Muneyuki Daidai
  • Patent number: 8835772
    Abstract: In order to lower the substantial heating temperature of a thermosetting adhesive and to realize favorable connection reliability during connecting an electrical element to a circuit board by anisotropic conductive connection with using solder particles, a product in which solder particles having a melting temperature Ts are dispersed in an insulating acrylic-based thermosetting resin having a minimum melt viscosity temperature Tv is used as an anisotropic conductive adhesive in producing a connection structure by connecting the circuit board and the electrical element to each other by anisotropic conductive connection.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: September 16, 2014
    Assignee: Dexerials Corporation
    Inventor: Satoshi Igarashi
  • Patent number: 8829360
    Abstract: The connector for PV cells is a strip of electrically conductive material which has a flat cross-section with two broad sides and with two narrow sides which each connect opposite edges of the broad sides. At least one broad side has a corrugated structure running in longitudinal direction of the strip and is pre-tinned in an area the length of which is somewhat less than the length of the edge of a PV cell.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: September 9, 2014
    Assignee: Schlenk Metallfolien GmbH & Co. KG
    Inventors: Thomas Booz, Fabian Distelrath
  • Patent number: 8830691
    Abstract: A printed circuit board including a core substrate including a first resin substrate, a second resin substrate having an opening and a third resin substrate in a multilayer manner while interposing bonding plates, insulating layers and conductive circuit layers alternately laminated on the core substrate, solder bumps formed on an outer surface of the printed circuit board, a first capacitor formed in the opening of the second resin substrate, a conductive pad formed on the first resin substrate and connected to an electrode of the first capacitor, a via hole formed in the first resin substrate and directly connected to the conductive pad and a conductive circuit on the core substrate, and a second capacitor mounted on a surface of the printed circuit board.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: September 9, 2014
    Assignee: IBIDEN Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 8822836
    Abstract: A bonding sheet includes an insulating sheet with cavities formed within the insulating sheet, and adhesive-filling portions made of an electrically conductive adhesive filled in the cavities. An electronic circuit device includes an IC package mounted on a circuit board, with the bonding sheet disposed between the IC package and the circuit board. The IC package is provided with terminal electrodes in the lower surface, and electrode bumps project from the terminal electrodes. The circuit board has recesses in the upper surface, and electrode pads are formed on the bottom of the recesses. The electrically conductive adhesive that flows out from the adhesive-filling portions filled the recesses and fix the electrode bumps and the electrode pads.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: September 2, 2014
    Assignee: NEC Corporation
    Inventor: Eiji Hori
  • Patent number: 8822835
    Abstract: A capacitive touch panel sensor in which waviness generated in a film furnished with a transparent electrode pattern can be small. The touch panel sensor according to the present invention includes a first film, a first transparent electrode pattern formed on the first film, a first adhesive layer laminated on the first film so as to cover the first transparent electrode pattern, a second film laminated on the first adhesive layer, a second adhesive layer laminated on the second film, a third film laminated on the second adhesive layer, and a second transparent electrode pattern formed on the third film, wherein Da/Db is 0.5 to 0.9 where a total thickness of the second film and the second adhesive layer is Da, and a distance between the first transparent electrode pattern and the second transparent electrode pattern is Db.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: September 2, 2014
    Assignee: Nitto Denko Corporation
    Inventors: Mizue Nagata, Tomotake Nashiki
  • Patent number: 8816215
    Abstract: The present invention relates to a disk with an electrical connection element, having a substrate with a first coefficient of thermal expansion, an electrically conductive structure on a region of the substrate, and a connection element with a second coefficient of thermal expansion.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: August 26, 2014
    Assignee: Saint-Gobain Glass France
    Inventors: Bernhard Reul, Mitja Rateiczak, Stefan Ziegler, Andreas Schlarb