Adhesive/bonding Patents (Class 174/259)
  • Patent number: 8300329
    Abstract: Disclosed are an optical element assembly comprising a base member in which occurrence of cracks in the base member upon cutting can be prevented and a method of manufacturing an optical unit. The optical element assembly comprises a base member and a plurality of lens members, wherein at least the base member of the optical element assembly is composed of an acryl resin having an alicyclic structure which is a polymer of a monomer represented by the following formula (1) in which linkage groups R2 and R3 lie between an atomic group A and R1OCO and between an atomic group A and OCOCR2, respectively.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: October 30, 2012
    Assignee: Konica Minolta Opto, Inc.
    Inventor: Takashi Washizu
  • Patent number: 8300421
    Abstract: An electronic component and a method of manufacturing an electronic component including a first surface mount device and a second surface mount device are provided. The first surface mount device and the second surface mount device are joined to a substrate via joint materials such that either or both of the first and second surface mount devices are shifted from the locations corresponding to land electrodes located on the substrate so as to be aligned with each other and are subjected to a reflow process. The outer land electrodes are formed at locations shifted inwardly from the locations corresponding to a virtual arrangement state in which the first surface mount device and the second surface mount device are arranged in series such that an end surface of the first surface mount device is in contact with an end surface of the second surface mount device.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: October 30, 2012
    Assignee: Murata manufacturing Co., Ltd.
    Inventor: Yasuo Yokoyama
  • Publication number: 20120261169
    Abstract: The present invention enables additional processes required for forming vertical wiring and rewiring in a double face package (DFP) or a wafer level chip size package (WLCSP) to be implemented through use of a component for vertical wiring and rewiring, to thereby simplify the manufacturing process and reduce cost. An electronic component for interconnection is incorporated into an electronic device package in which a circuit element including a semiconductor chip is disposed and which has external electrodes connected to the circuit element via vertical interconnects and horizontal interconnects.
    Type: Application
    Filed: November 24, 2010
    Publication date: October 18, 2012
    Inventors: Masamichi Ishihara, Minoru Enomoto, Shigeru Nomura
  • Patent number: 8288659
    Abstract: A wiring board includes a substrate having a surface made of an insulating resin. An adhesion layer is formed on the substrate. A wiring layer is formed on the adhesion layer. The adhesion layer is formed by a nitrided NiCu alloy containing nitrogen therein. A nitrogen content of the nitrided NiCu alloy is within a range from 1 atoms % to 5 atoms %.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: October 16, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Tomoo Yamasaki
  • Patent number: 8278561
    Abstract: A conductive pattern forming film provides a pattern formed on a film substrate having flexibility by pressurizing, under heating, a conductive paste in which powder or fine particles of metal or semiconductor are dispersed and filled. A conductive pattern forming apparatus comprises a sample installation table having a flat placement surface, and a driving body for pressure application which is placed in a manner facing the placement surface and movable, wherein the driving body for pressure application is equipped with a support which is constituted by a flat metal panel having metal spheres along its bottom face.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: October 2, 2012
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Toshihide Kamata, Manabu Yoshida
  • Patent number: 8274181
    Abstract: A structure for transmission in a power supply, particularly to a power structure for transmission for bearing large DC current, wherein the power supply includes a power input port for connecting to DC input power and a DC/DC conversion circuit for converting the DC input power into DC output power. The architecture including at least one power transmission board for disposing the power input port, wherein the power transmission board is electrically connected to the power process board with the DC/DC conversion circuit mounted thereon by at least one power conduction element. Therefore, through the power conduction elements replacing the conventional connecting wires with large diameter to connect the power input port and the power process board without disobeying the safety regulation, not only the space occupied by the bent connection wires can be reduced, but the collisions and damage to other components caused therefrom also can be avoided.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: September 25, 2012
    Assignees: FSP Technology Inc., 3Y Power Technology (Taiwan), Inc.
    Inventor: Shao-Feng Lu
  • Publication number: 20120234586
    Abstract: Embodiments of the invention generally relate to methods of forming flexible substrates for use in photovoltaic modules. The methods include shaping a metal foil and adhering the metal foil to a flexible backsheet. An optional interlayer dielectric and anti-tarnish material may then be applied to the upper surface of the shaped metal foil disposed on the flexible backsheet. The metal foil may be shaped using die cutting, roller cutting, or laser cutting techniques. The die cutting, roller cutting, and laser cutting techniques simplify the flexible substrate formation processes by eliminating resist-printing and etching steps previously used to pattern metal foils. Additionally, the die cutting, roller cutting, and laser cutting techniques reduce the consumption of consumable materials previously used in the patterning of metal foils.
    Type: Application
    Filed: March 14, 2012
    Publication date: September 20, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: JOHN TELLE, Brian J. Murphy, David H. Meakin
  • Publication number: 20120228008
    Abstract: Various aspects of the present invention provide a transfer method for peeling off an MIM structure (comprising lower electrode/dielectric layer/upper electrodes) film formed on a supporting substrate and then transferring onto a transfer substrate with sufficiently uniform and low damage. Various aspects of the present invention also provide a thin film element provided with one or more thin film components which are transferred onto a substrate by using said method.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 13, 2012
    Applicant: TAIYO YUDEN CO., LTD
    Inventors: Ryuichi KONDOU, Kenichi Ota
  • Patent number: 8263862
    Abstract: A packaging system having a housing for providing a hermetically sealed interior space for receiving and supporting optoelectronic components. The housing has at least one section of wall comprising a layer of liquid crystal polymer (LCP). At least one hermetically sealed electrical port is formed in the LCP wall section over a predetermined area and comprises a layer of metal adhered to and overlying the predetermined area on the of the LCP wall section. An electrode passes through the metal from the exterior of the system to the interior space to provide an electrical communication path between the optoelectronic components and the exterior of said packaging system. A solder joint is formed between the electrode and the layer of metal to provide a hermetic connection between the layer of metal and the electrode to assure that the hermeticity of the housing remains unchanged with the electrical port present.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: September 11, 2012
    Assignee: Linden Photonics, Inc.
    Inventors: Amaresh Mahapatra, Stephen M. O'Riorden
  • Patent number: 8263873
    Abstract: Provided is a flexible printed circuit board (FPCB) for a large capacity signal transmission medium that may maintain an impedance suitable for accurately transmitting a large capacity signal such as a low-voltage differential signaling (LVDS) signal and may also have an excellent flexibility. A copper foil large capacity signal wire includes a plurality of first pads and a plurality of second pads that are spaced apart from each other at predetermined intervals and are alternately provided, to receive a large capacity signal from a television main board and to transmit the received large capacity signal to a display device. The first pad has a positive phase and the second pad has a negative phase. A copper foil ground layer is attached at a distance from the cooper foil large capacity signal layer to ground the large capacity signal that is transmitted to and is returned from the display device.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: September 11, 2012
    Assignees: Evertechno Co., Ltd.
    Inventors: Gyoung Duck Choi, Byeong Sik Son
  • Patent number: 8263177
    Abstract: A process is described for treating metal surfaces printed wiring boards and similar substrates to provide improved creep corrosion resistance on such surfaces. A modified organic solderability preservative composition is used in combination with an emulsion polymer to provide a modified polymer coating on the metal surface finish via a chemical reaction to provide enhanced corrosion protection of the surface.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: September 11, 2012
    Inventors: Kesheng Feng, Nilesh Kapadia, Witold Paw
  • Patent number: 8264841
    Abstract: The present invention is directed to improve reliability by preventing deterioration in the structure of an inner wall of a water channel caused by galvanic corrosion. A heat sink in which a water channel of a cooling fluid is formed by stacking and bonding a plurality of thin plates, in which a surface in the water channel is made of the same metal material except for at least an end of a bonded part of the thin plates.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: September 11, 2012
    Assignee: Sony Corporation
    Inventors: Kenji Sasaki, Hidekazu Kawanishi, Yuichi Hamaguchi
  • Patent number: 8258407
    Abstract: A wiring board is provided to protect an electronic device from static electricity and lightning surge without reducing packaging density. A wiring board is provided with a first wiring pattern (3) including mounting pads (8, 10), on which an electronic device (5) is mounted, a second wiring pattern (21) having lower impedance than the first wiring pattern (3), ICT wirings (13, 15) extending from the mounting pads (8, 10) of the first wiring pattern (3), and ICT pads (17, 19) formed at distal ends of the ICT wirings (13, 15). The ICT wirings (13, 15) extend towards the second wiring pattern (21) so that the ICT pads (13, 15) are in the vicinity of the second wiring pattern (21), and discharge gaps (G) are formed between the ICT pads (13, 15) and the second wiring pattern (21).
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: September 4, 2012
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventor: Koji Kishimoto
  • Patent number: 8252365
    Abstract: The method of manufacturing a piezoelectric element includes the steps of: a lower electrode forming step of forming a lower electrode on a surface of a substrate; a piezoelectric film deposition step of depositing a piezoelectric film made of a piezoelectric material by one of epitaxial growth and oriented growth onto a surface of the lower electrode reverse to a surface adjacent to the substrate; an upper electrode forming step of forming an upper electrode onto a surface of the piezoelectric film reverse to a surface adjacent to the lower electrode; and a polarization direction reversal step of reversing a polarization direction of the piezoelectric film by applying an alternating electric field of an intensity not lower than a coercive electric field of the piezoelectric material, between the upper electrode and the lower electrode, and then applying a direct electric field of an intensity not lower than the coercive electric field in a direction from the upper electrode toward the lower electrode.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: August 28, 2012
    Assignee: Fujifilm Corporation
    Inventor: Ryuji Tsukamoto
  • Patent number: 8254140
    Abstract: A mounting substrate includes a substrate, a bonding pad and an induction heating pad. The bonding pad is formed on the substrate, and adhered to a solder ball to mount a semiconductor chip on the substrate. The induction heating pad is disposed adjacent to the bonding pad, the induction heating pad being induction heated by an applied alternating magnetic field to reflow the solder ball. The induction heating pad having a diameter greater than a skin depth in response to the frequency of the applied alternating magnetic field is selectively induction heated in response to a low frequency band of the alternating magnetic field. Accordingly, during a reflow process for a solder ball, the semiconductor chip may be mounted on the mounting substrate to complete a semiconductor package without damaging the mounting substrate, to thereby improve the reliability of the completed semiconductor package.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: August 28, 2012
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Kwang-Yong Lee, Jong-Gi Lee, Sun-Won Kang, Ji-Seok Hong
  • Patent number: 8247700
    Abstract: A wired circuit board has a metal supporting board, an insulating layer formed on the metal supporting board, a conductive pattern formed on the insulating layer and having a pair of wires arranged in spaced-apart relation, and a semiconductive layer formed on the insulating layer and electrically connected to the metal supporting board and the conductive pattern. The conductive pattern has a first region in which a distance between the pair of wires is small and a second region in which the distance between the pair of wires is larger than that in the first region. The semiconductive layer is provided in the second region.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: August 21, 2012
    Assignee: Nitto Denko Corporation
    Inventors: Jun Ishii, Yasunari Ooyabu, Visit Thaveeprungsriporn
  • Patent number: 8242378
    Abstract: A lead-free solder joint is formed between a tin-silver-copper solder alloy (SAC), SACX, or other commonly used Pb-free solder alloys, and a metallization layer of a substrate. Interaction of the SAC with the metallization layer forms an intermetallic compound (IMC) that binds the solder mass to the metallization layer. The IMC region is substantially free of any phosphorous-containing layers or regions.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: August 14, 2012
    Assignee: Agere Systems Inc.
    Inventors: Ahmed Amin, Frank Baiocchi, John Delucca, John Osenbach, Brian T. Vaccaro
  • Patent number: 8238109
    Abstract: A flex-rigid wiring board including a flexible printed wiring board, a rigid printed wiring board, a first connection terminal formed over the rigid printed wiring board and positioned to be mounted onto a motherboard, and a second connection terminal formed over the rigid printed wiring board and positioned to mount an electronic component. The flexible printed wiring board has a first conductive layer, the rigid printed wiring board has a rigid base material, an insulation layer over the rigid base material and a second conductive layer formed over the insulation layer. The insulation layer covers at least a portion of the flexible printed wiring board and at least a portion of the rigid base material while exposing at least a portion of the flexible printed wiring board, and the first conductive layer and the second conductive layer are connected through a plated metallic layer penetrating through the insulation layer.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: August 7, 2012
    Assignee: IBIDEN Co., Ltd.
    Inventor: Katsumi Sagisaka
  • Publication number: 20120193800
    Abstract: A solder includes Sn (tin), Bi (bismuth) and Zn (zinc), wherein the solder has a Zn content of 0.01% by weight to 0.1% by weight.
    Type: Application
    Filed: December 7, 2011
    Publication date: August 2, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Toshiya Akamatsu, Nobuhiro Imaizumi, Seiki Sakuyama, Keisuke Uenishi, Tetsuhiro Nakanishi
  • Patent number: 8230564
    Abstract: A millimeter wave transmission line filter having a plurality of filter pole determining coupled cavities fabricated with a multiple lithographic layer micromachining process. The filter cavities are oriented perpendicular to an underlying substrate element in order to achieve micromachining, fabrication and accuracy advantages. Multiple filters can be used in a frequency multiplex arrangement as in a duplexer. Radio frequencies in the 15 to 300 gigahertz range are contemplated.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: July 31, 2012
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: J. Robert Reid, Jr.
  • Patent number: 8232476
    Abstract: It is an object of the present invention to provide a flexible multilayer wiring board that can be easily reduced in thickness and that also has sufficient durability against repeated bending or heat shock. A preferred mode of the flexible multilayer wiring board comprises a flexible inner layer board obtained by forming an inner layer wiring on both sides of an insulating layer, an outer layer wiring situated on at least one side of the inner layer board, and insulating adhesive sheets lying between the inner layer board and outer layer wiring. One of the insulating adhesive sheets are composed of an imide group-containing polymer.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: July 31, 2012
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Shigehiro Nakamura, Toshihiko Itou, Masayoshi Joumen, Youichirou Mansei
  • Publication number: 20120186865
    Abstract: A conductor layer is formed on one surface of a base insulating layer. The conductor layer includes a collector portion, and a drawn-out conductor portion extending in an elongated shape from the collector portion. A cover layer is formed on the base insulating layer to cover a predetermined portion of the conductor layer. A material for the cover layer includes a paste composition containing a compound expressed by the formula (1).
    Type: Application
    Filed: January 24, 2012
    Publication date: July 26, 2012
    Applicant: NITTO DENKO CORPORATION
    Inventors: Hirofumi EBE, Shinichi INOUE, Yoshihiro FURUKAWA
  • Patent number: 8216668
    Abstract: The present invention provides a resin composition which can produce a multilayer printed wiring board not causing peeling and crack in a thermal shock test such as a cooling/heating cycle, and having high heat resistance and low-thermal expansion characteristics, when the resin composition is used for an insulating layer of the multilayer printed wiring board; and also an insulating sheet provided on a base, a prepreg, a multilayer printed wiring board and a semiconductor device using thereof. The resin composition is used for forming an insulating layer of the multilayer printed wiring board, wherein a surface roughness parameter Rvk value of the insulating layer is from 0.1 ?m to 0.8 ?m, measured after the insulating layer being formed with the resin composition, and subject to roughening treatment.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: July 10, 2012
    Assignee: Sumitomo Bakelite Company, Ltd.
    Inventor: Michio Kimura
  • Patent number: 8212155
    Abstract: Embodiments of an integrated passive device include a high-aspect ratio conductive line positioned on a carrier, a substrate, and a bump that secures the high-aspect ratio conductive line to the substrate.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: July 3, 2012
    Inventors: Peter V. Wright, Kenneth Mays
  • Publication number: 20120156502
    Abstract: Disclosed is an adhesive film in which the adhesive film contains a thermosetting resin (A), a curing agent (B), a compound having flux activity (C) and a film forming resin (D), the minimum melt viscosity of the adhesive film is 0.01 to 10,000 Pa·s, and the adhesive film satisfies the following formula (1) when the exothermic peak temperature of the adhesive film is defined as (a) and the 5% weight loss temperature by thermogravimetry of the adhesive film is defined as (b), (b)?(a)?100 degrees centigrade??(1).
    Type: Application
    Filed: September 9, 2010
    Publication date: June 21, 2012
    Applicant: Sumitomo Bakelite Co., Ltd.
    Inventors: Kenzou Maejima, Satoru Katsurayama
  • Patent number: 8202622
    Abstract: The present invention is a circuit connecting material used for the mutual connection of a circuit member in which electrodes and insulating layers are formed adjacent to each other on the surface of a board, and a circuit member in which electrodes and insulating layers are formed adjacent to each other on the surface of a board, with the edge parts and of the insulating layers being formed with a greater thickness than the electrodes on the basis of the main surfaces, wherein this circuit connecting material contains a bonding agent composition and conductive particles that have a mean particle size of 1 ?m or greater but less than 10 ?m and a hardness of 1.961 to 6.865 GPa, and this circuit connecting material exhibits a storage elastic modulus of 0.5 to 3 GPa at 40° C. and a mean coefficient of thermal expansion of 30 to 200 ppm/° C. at from 25° C. to 100° C. when subjected to the curing treatment.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: June 19, 2012
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Motohiro Arifuku, Itsuo Watanabe, Yasushi Gotou, Kouji Kobayashi, Kazuyoshi Kojima
  • Patent number: 8189344
    Abstract: An integrated circuit package system includes: providing a package substrate; mounting an interposer chip containing active circuitry over the package substrate; attaching a conductive bump stack having a base bump end and a stud bump end, the base bump end on the interposer chip; connecting a stack connector to the interposer chip and the package substrate; and applying a package encapsulant over the interposer chip, the stack connector, and the conductive bump stack with the stud bump end of the conductive bump stack substantially exposed.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: May 29, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Sang-Ho Lee, Soo-San Park, DaeSik Choi
  • Patent number: 8178191
    Abstract: A multilayer wiring board includes a core insulating layer with a first conductive wiring, a first insulating layer with a softening temperature lower than the core insulating layer, and a second insulating layer formed on the core insulating layer through the first insulating layer, the second insulating layer with a second conductive wiring electrically connected to the first conductive wiring and a softening temperature higher than the first insulating layer. The first insulating layer is mainly formed of a liquid crystal polymer. The core insulating layer and the second insulating layer are mainly formed of a polyimide resin or a bismaleimide triazine resin. The first conductive wiring and the second conductive wiring are electrically connected through a conductive via formed penetrating through the first insulating layer and the second insulating layer in a thickness direction.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: May 15, 2012
    Assignee: Hitachi Cable, Ltd.
    Inventors: Shigeo Nishino, Hiroyuki Takasaka, Nagayoshi Matsuo, Hiroyuki Okabe
  • Patent number: 8178788
    Abstract: An electronic component package includes a film board where an electronic component is mounted, and a lid part mounted on the film board so as to cover a surface of the film board. The electronic component is provided in a cavity formed by the film board and the lid part, and the electronic component is connected to a signal wiring conductor formed at the film board.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: May 15, 2012
    Assignee: Fujitsu Limited
    Inventors: Takatoshi Yagisawa, Tadashi Ikeuchi
  • Publication number: 20120111622
    Abstract: The present invention relates to a double-sided pressure-sensitive adhesive tape or sheet for use in a wiring circuit board, which includes a pressure-sensitive adhesive layer formed of a pressure-sensitive adhesive composition comprising an acrylic polymer and a tackifier resin containing a phenolic hydroxyl group; and a release liner comprising a releasing treatment layer formed of a silicone release agent. The double-sided pressure-sensitive adhesive tape or sheet of the invention has a good adhesiveness and, even after a high-temperature step, it is capable of exerting an excellent anti-repulsion property. Further, since the release liner can be easily peeled off even after the high-temperature step, the workability is excellent and the productivity is improved.
    Type: Application
    Filed: January 19, 2012
    Publication date: May 10, 2012
    Applicant: NITTO DENKO CORPORATION
    Inventors: Noritsugu DAIGAKU, Takahiro Nonaka, Masahiro Oura
  • Patent number: 8164915
    Abstract: A system for electronic components mounted on a circuit board is disclosed. One embodiment provides placing an elastic, anisotropically conductive material on top of a printed circuit board. An electronic component is placed over the elastic, anisotropically conductive material, fixing the electronic component on the printed circuit board.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: April 24, 2012
    Assignee: Qimonda AG
    Inventor: Jens Niemax
  • Patent number: 8163381
    Abstract: Provided, are multi-layer chip carriers comprising an asymmetric cross-linked polymeric dielectric film, and processes for making the chip carriers.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: April 24, 2012
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Pui-Yan Lin, Govindasamy Paramasivam Rajendran, George Elias Zahr
  • Patent number: 8164001
    Abstract: A multilayer printed circuit board includes an inner magnetic layer essentially consisting of magnetic material. The inner magnetic layer may be formed by an action of chemical bond or van der Waals force. The inner magnetic layer may comprise a plurality of magnetic units, each of which provides magnetism, and may be formed by magnetically coupling the magnetic units with each other by using a strong interaction. The inner magnetic layer may essentially consist of a ferrite film. The ferrite film may be formed directly on the inner conductive layer by means of an electroless plating method. The ferrite film may essentially consist of an oxide metal composition, the metal composition being represented by the formula of FeaNibZncCod, where: a+b+c+d=3.0; 2.1?a?2.7; 0.1?b?0.3; 0.1?c?0.7; and 0?d?0.15.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: April 24, 2012
    Assignee: NEC Tokin Corporation
    Inventors: Shigeyoshi Yoshida, Koichi Kondo, Hiroshi Ono, Satoshi Arai, Tadashi Kubodera
  • Patent number: 8158269
    Abstract: A composite material for an electrical/electronic part, which is used as a material for use in an electrical/electronic part formed by punching process, containing a metal base material of, for example, a copper-type metal material and a substantially one layer of an insulating film provided on at least a part of the metal base material, in which a metal layer formed of Ni or a Ni—Zn alloy is interposed between said metal base material and said insulating film, such that the peel width of said insulating film at the end of the material obtained after said punching process, is less than 10 ?m.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: April 17, 2012
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Chikahito Sugahara, Satoru Zama, Akira Tachibana
  • Patent number: 8158887
    Abstract: An adhesive film including a first adhesive layer containing a first main resin component and dispersed conductive particles, and a second adhesive layer containing a second main resin component and adhering to the first adhesive layer, each of the adhesive layers containing a secondary resin component, wherein the first main resin component has a glass transition temperature higher than that of the secondary resin component, and the second main resin component has a glass transition temperature higher than that of the secondary resin component and lower than that of the first main resin component, and a reaction peak temperature of each of the adhesive layers is lower than the glass transition temperature of the first main resin component and higher than the glass transition temperature of the second main resin component, and is a temperature at which a calorific value of the adhesive layer is maximum during temperature rise.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: April 17, 2012
    Assignees: Sony Corporation, Sony Chemical & Information Device Corporation
    Inventors: Tomoyuki Ishimatsu, Hiroki Ozeki
  • Patent number: 8152950
    Abstract: A method of making a multi-layer circuit board that has a first film and at least two more films, second and third films, each being made of a thermoplastic polymer capable of forming an optically anisotropic melt phase, the first film having a low melting point, the second and third films having respective melting points higher than the melting point of the first film and at least one of the second and the third films having a circuit pattern thereon, and the first to third films are thermo compressed together with the first film interposed between the second and third films. This method entails causing at least one of the circuit patterns on one of the second and third films to contact an opposing surface of the other of the second and third films through the first film during the thermo compression bonding of the first to third films.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: April 10, 2012
    Assignee: Kuraray Co., Ltd.
    Inventors: Toshinori Tsugaru, Tatsuya Sunamoto, Tadao Yoshikawa
  • Publication number: 20120080219
    Abstract: A method of manufacturing an electronic device in which an electronic component is flip-chip mounted on a circuit board, the method includes supplying, on an electrode of the circuit board or a terminal of the electronic component, a first resin material of a thickness smaller than a gap between the circuit board and the electronic component, after supplying the first resin material, connecting the terminal to the electrode by melting a solder material disposed on the electrode or the terminal at a first temperature with keeping the terminal in contact with the electrode, after connecting the terminal to the electrode, filling the gap between the circuit board and the electronic component with a second resin material, and heating the second resin material at a second temperature lower than the first temperature.
    Type: Application
    Filed: August 12, 2011
    Publication date: April 5, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Shuichi TAKEUCHI, Kenji KOBAE, Yoshiyuki SATOH, Naoki ISHIKAWA, Takeshi MIYAKOSHI, Tetsuya TAKAHASHI
  • Patent number: 8148641
    Abstract: An anisotropic conductive material prevents conduction resistance from varying among bumps or among linear terminals when connecting an IC chip or a flexible wire to a wiring board via the anisotropic conductive material. The anisotropic conductive material is formed by dispersing conductive particles in an insulating binder. The minimum melt viscosity [?0] thereof is in a range of from 1×102 to 1×106 mPa·sec, and satisfies the following equation (1): 1<[?1]/[?0]?3??(1) where in the equation (1), [?0] represents the minimum melt viscosity of the anisotropic conductive material, and [?1] represents a melt viscosity at a temperature T1 which is 30° C. lower than a temperature T0 at which the minimum melt viscosity is exhibited.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: April 3, 2012
    Assignees: Sony Corporation, Sony Chemical & Information Device Corporation
    Inventors: Yoshito Tanaka, Jun Yamamoto
  • Publication number: 20120073869
    Abstract: A conductive adhesive includes 10 to 90 wt % of Sn—Bi system solder powder and the remainder of an adhesive containing organic acid, and the Sn—Bi system solder powder is composed of solder particles having a particle size L1 of 20 to 30 ?m and solder particles having a particle size L2 of 8 to 12 ?m, and a mixing ratio of the Sn—Bi system solder powder is such that the solder particles having a particle size of 20 to 30 ?m occupy 40 to 90 wt % with respect to the whole solder powder, and the remainder is occupied by solder particles having a particle size of 8 to 12 ?m.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 29, 2012
    Applicant: Panasonic Corporation
    Inventors: Arata KISHI, Naomichi OHASHI, Atsushi YAMAGUCHI
  • Publication number: 20120055705
    Abstract: This invention relates to 9,10-Dihydro-9-Oxa-10-Phosphaphenantrene-10-oxide derived additive flame-retardants, which are useful in epoxy resin compositions. The epoxy resin compositions may be used in making prepregs or laminates for printed wiring boards and composite materials.
    Type: Application
    Filed: May 19, 2010
    Publication date: March 8, 2012
    Applicant: Albemarle Corporation
    Inventors: Kimberly M. White, Yu Li Angell, Scott E. Angell, Arthur G. Mack
  • Patent number: 8129623
    Abstract: The invention relates to a resin film having a high adhesiveness to other materials, an adhesive sheet, a circuit board and an electronic apparatus in which an adhesive layer and the resin film are firmly adhered. A resin film (1) includes a plurality of projected portions (10) each having a filler (9) in an apex portion (10a) and a resin material. The projected portions (10) are formed on at least one surface of a sheet portion (16).
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: March 6, 2012
    Assignee: Kyocera Corporation
    Inventors: Tadashi Nagasawa, Masaharu Shirai, Kenji Kume, Yutaka Tsukada
  • Publication number: 20120048606
    Abstract: The adhesive composition of the invention contains (a) organic fine particles comprising at least one selected from the group consisting of alkyl (meth)acrylate ester-butadiene-styrene copolymer or complexes thereof, alkyl (meth)acrylate ester-silicone copolymer or complexes thereof and silicone-(meth)acrylic acid copolymer or complexes thereof.
    Type: Application
    Filed: July 29, 2008
    Publication date: March 1, 2012
    Applicant: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Hiroyuki Izawa, Toshiaki Shirasaka, Shigeki Katogi, Sunao Kudou, Keiko Tomizawa
  • Patent number: 8124881
    Abstract: A printed board comprising a packaging surface on which an electronic component is packaged, an adhesion prohibited portion which is provided at a region of the printed board different from a region where the electronic component is provided, and to which adhesion of the adhesive material is prohibited, and a blocking step portion which is formed at a region between the region where the electronic component is provided and the region where the adhesion prohibited portion is provided, which blocks any adhesive material which has spilled out from between the bottom surface of the electronic component and the packaging surface from reaching the adhesion prohibited portion.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: February 28, 2012
    Assignee: Kyocera Corporation
    Inventor: Noriyuki Shirasawa
  • Patent number: 8125790
    Abstract: The invention discloses design concepts and means and methods that can be used for enhancing the reliability and extending the operating life of electronic devices, and assemblies incorporating such devices, and substrates and/or PCBs, especially if such assemblies are exposed to severe environmental conditions such as thermal cycling or power cycling. The main thrust of the invention is to provide flexible joints, such as columns, between the attached components, and preferably to orient such joints, so that they would present their softest bending direction towards the thermal center or fixation point of the assemblies. Joints with rectangular or elongated cross-section are preferred, and they should be oriented so that the wide face of each joint would be facing the thermal center, perpendicular to the thermal deformation ray emanating from the thermal center towards the center of each respective joint. The concepts apply equally to leadless packages as well as to leaded packages.
    Type: Grant
    Filed: August 24, 2008
    Date of Patent: February 28, 2012
    Inventor: Gabe Cherian
  • Patent number: 8124226
    Abstract: The present invention provides a circuit creation technology that improves conductive line manufacture by adding active and elemental palladium onto the surface of a substrate. The palladium is disposed in minute amounts on the surface and does not form a conductive layer by itself, but facilitates subsequent deposition of a metal onto the surface, according to the pattern of the palladium, to form the conductive lines.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: February 28, 2012
    Assignee: SRI International
    Inventors: Sunity Sharma, Jaspreet Singh Dhau
  • Publication number: 20120043126
    Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same, including: forming a protective layer on which a cover film is stacked on a base substrate; exposing the protective layer on which the cover film is stacked to photosensitize the protective layer and photodegrade the cover film; and developing the photodegraded cover film and the photosensitized protective layer to form an opening exposing a pad unit of a circuit layer which is an outermost layer of the base substrate on the protective layer, whereby the productivity of the printed circuit board can be improved without performing a process of separating a cover film.
    Type: Application
    Filed: August 19, 2011
    Publication date: February 23, 2012
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dae Jo HONG, Chang Sup RYU, Cheol Ho CHOI
  • Publication number: 20120043125
    Abstract: Provided is a method of forming a circuit board including an adhesion portion. The method may include forming a mask pattern including an opening on a board; performing a surface treatment process at a bottom of the opening; combining a linker with the surface on which a surface treatment process is performed; and forming a metal pattern combined with the linker in the opening.
    Type: Application
    Filed: July 29, 2011
    Publication date: February 23, 2012
    Inventors: Taehoon Kim, Jonggi Lee, Seungduk Baek
  • Patent number: 8119192
    Abstract: The method of manufacturing a piezoelectric element includes: a lower electrode forming step of forming a lower electrode on a surface of a substrate; a piezoelectric film deposition step of depositing a piezoelectric film made of a piezoelectric material by one of epitaxial growth and oriented growth onto a surface of the lower electrode reverse to a surface adjacent to the substrate; an upper electrode forming step of forming an upper electrode onto a surface of the piezoelectric film reverse to a surface adjacent to the lower electrode; and a polarization direction reversal step of reversing a polarization direction of the piezoelectric film by maintaining, after the upper electrode forming step, a state for a prescribed duration where a temperature of the piezoelectric film is set to a first temperature while application of an electric field to the piezoelectric film in a direction from the upper electrode toward the lower electrode is performed, then keeping the application of the electric field while lo
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: February 21, 2012
    Assignee: Fujifilm Corporation
    Inventor: Ryuji Tsukamoto
  • Patent number: 8116093
    Abstract: A printed circuit board (PCB) includes a substrate having a first group of at least two via holes and a second group of at least two via holes formed therein, a first pad set of terminal pads and a second pad set of terminal pads formed on the substrate, and a first group of conductive connection members and a second group of conductive connection members formed in the substrate. The first group of the via holes are surrounded by the first pad set of the terminal pads and the second group of the via holes are surrounded by the second pad set of the terminal pads. The first and the second groups of conductive connection members fill up the first and second groups of the via holes. The first group of the conductive connection members are connected to the first pad set of the terminal pads and the second group of the conductive connection members are connected to the second pad set of the terminal pads.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: February 14, 2012
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Kwang-Soo Park, Jong-Hoon Kim
  • Patent number: 8115109
    Abstract: A circuit board in which end faces (36a) of wires are located in positions withdrawn from the end in a joint region of a first board (31a), end faces (36b) of wires are located in positions withdrawn from the end in a joint region of a second board (31b), a gap (W) between the end faces (36a) of the wires of the first board (31a) and the end faces (36b) of the wires of the second board (31b) is filled with a conductor (16A), and the first board (31a) and the second board (31b) are jointed by means of a resin.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: February 14, 2012
    Assignee: Panasonic Corporation
    Inventors: Masayoshi Koyama, Norihito Tsukahara, Susumu Matsuoka