Abstract: A receiving antenna of a wireless power receiving apparatus for wireless power charging according to one embodiment of the present invention comprises: a substrate; a soft magnetic layer disposed on the substrate; and a receiving coil which is wound in parallel with a plane of the soft magnetic layer and is embedded on one surface of the soft magnetic layer, wherein at least one surface of the receiving coil is slantly embedded on the one surface of the soft magnetic layer.

Abstract: A printed circuit board includes a body, a first conductive pattern layer disposed on a first surface of the body, and a second conductive pattern layer disposed on a second surface of the body. The first conductive pattern layer and the second conductive pattern layer form a capacitor. The present disclosure further provides an motor having the printed circuit board.

Abstract: In various aspects, an organic optoelectronic component and method for producing an organic optoelectronic component are described. An organic optoelectronic component may include a first electrode, an organic functional layer structure above the first electrode, a second electrode above the organic functional layer structure, an adhesive layer structure, and a protective film. The adhesive layer structure may contain a first adhesive layer above the first adhesive layer, and a second adhesive layer above the first adhesive layer. The first adhesive layer may be cured. The second adhesive layer may be adherent and elastic. The protective film may be above the second adhesive layer. The protective film may contain at least one region that is at least partly separated in a lateral direction.

Abstract: A capacitor includes a body including a plurality of dielectric layers, first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween, and first and second insulating regions. The first insulating region is disposed in each of the first internal electrodes and includes a first connection electrode disposed therein. The second insulating region is disposed in each of the second internal electrodes and includes a second connection electrode disposed therein. The products D1×Td and D2×Td are greater than 20 ?m2, where Td is a thickness of the dielectric layer, and D1 and D2 are widths of the first and second insulating regions, respectively.

Abstract: A composite electronic component includes: a composite body in which a multilayer ceramic capacitor and a ceramic chip are coupled to each other. The multilayer ceramic capacitor includes a first ceramic body, and first and second external electrodes disposed on both end portions of the first ceramic body. The ceramic chip includes a second ceramic body disposed on a lower portion of the multilayer ceramic capacitor, and first and second terminal electrodes disposed on both end portions of the second ceramic body and connected to the first and second external electrodes. A width of first regions of the second ceramic body in which the first and second terminal electrodes are disposed is wider than a width of a second region of the second ceramic body between the first regions.

Abstract: A semiconductor device package includes a metal carrier, a passive device, a conductive adhesive material, a dielectric layer and a conductive via. The metal carrier has a first conductive pad and a second conductive pad spaced apart from the first conductive pad. The first conductive pad and the second conductive pad define a space therebetween. The passive device is disposed on top surfaces of first conductive pad and the second conductive pad. The conductive adhesive material electrically connects a first conductive contact and a second conductive contact of the passive device to the first conductive pad and the second conductive pad respectively. The dielectric layer covers the metal carrier and the passive device and exposes a bottom surface of the first conductive pad and the second conductive pad. The conductive via extends within the dielectric layer and is electrically connected to the first conductive pad and/or the second conductive pad.

Abstract: A lead component mounting machine is provided in which lead wires are pinched and held from both sides by a pair of pawl portions, and the lead wires are inserted into through-holes of a board. The holding by the pawl portions is loosened, and a component main body is pushed in by a pushing-in device until the component main body comes into contact with the pawl portions. Subsequently, the strength of the holding by the pawl portions is increased, and the cutting and clinching of the lead wires is performed. Sliding movement of the lead wires is in a state of being suppressed by the pawl portions.

Abstract: A semiconductor wafer with a test key structure is provided. The semiconductor wafer includes a semiconductor substrate including a scribe line region, a chip region, and a seal ring region between the scribe line region and the chip region. A test pad structure and a test element are disposed over the semiconductor substrate corresponding to the scribe line region. A conductive line is disposed over the semiconductor substrate corresponding to the seal ring region, and has two ends extending to the scribe line region and electrically connected between the test pad structure and the test element.

Abstract: A sealing structure (200) seals a light emitting unit (140) and includes a first inorganic film (210), a second inorganic film (220), a first resin-containing film (230), and a second resin-containing film (240). The film thickness of the first inorganic film (210) is equal to or greater than 1 nm and equal to or less than 300 nm. The first resin-containing film (230) is in contact with the first inorganic film (210) and includes a first resin. The second inorganic film (220) is positioned on an opposite side of the first inorganic film (210) with the first resin-containing film (230) interposed between the first and second inorganic films. The second resin-containing film (240) is positioned between the first resin-containing film (230) and the second inorganic film (220) and is in contact with the second inorganic film (220). The second resin-containing film (240) includes a second resin.

Abstract: An interposer includes an interposer substrate having a series of vias, and a series of metallic interconnects in the series of vias. The interposer substrate has a first surface and a second surface opposite the first surface. The interposer substrate includes a dielectric material. A first pitch of the series of vias at a first end of the series of vias is different than a second pitch of the series of vias at a second end of the series of vias.

Abstract: According to one embodiment, an electronic apparatus includes, for example, a casing having an opening with a perimeter, and a circuit board including a first surface facing away from the casing and a second surface facing the casing, a first conductor which extends over the opening in the casing and at least a portion of which is located over the first surface, a second conductor at least portion of which extends over the second surface and is exposed to the interior of the casing at the opening in the casing, and a third conductor extending through the first surface and the second surface and electrically connected to the first conductor and the second conductor at a location outward of the perimeter of the opening.

Abstract: A printed circuit board includes a first trace, a second trace, and a first via. The first trace is in a first conductive layer. The second trace is in a second conductive layer. The first via interconnects the first trace and the second trace, and communicates a first signal from the first trace to the second trace through a third conductive layer. The third conductive layer has a higher impedance than the first conductive layer and the second conductive layer.

Abstract: An electronic component includes: a plurality of multilayer capacitors stacked in multiple rows and columns and each having external electrodes on both ends thereof in a first direction; and a board including a body and a connection portion. The connection portion includes: a plurality of positive electrode land patterns; a plurality of negative electrode land patterns; positive and negative electrode terminal patterns formed on a lower surface of the body to be spaced apart from each other in the first direction; a positive electrode connection portion connecting the plurality of positive electrode land patterns to the positive electrode terminal pattern; and a negative electrode connection portion connecting the plurality of negative electrode land patterns to the negative electrode terminal pattern.

Abstract: A semiconductor device includes a printed circuit board that includes a first electrode, a resin substrate that includes a first face directed toward the printed circuit board, a second electrode formed in a second portion surrounding a first portion of the first face, a second face opposite the first face, and a third electrode formed in a third portion of the second face, the third portion overlapping the first portion in a plan view, a semiconductor chip that includes a coupling terminal joined to the third electrode, a conductive member that is formed between the printed circuit board and the resin substrate and contains a conductive particle and resin, and a solder bump that is formed between the printed circuit board and the resin substrate and is joined to the first electrode and the second electrode.

Abstract: A component carrier includes a first level stack of first plural of electrically conductive layer structures and/or first electrically insulating layer structures; a first component aligned within a first through hole cut out in the first level stack such that one of an upper or a lower surface of the first component is substantially flush with an respective upper or a lower surface of the first level stack second electrically conductive layer structures and/or second electrically insulating layer structures attached onto the upper and the lower surface of the first level stack thereby covering the first component at the upper and the lower surface of the first component and pressed to form a second level stack. A second component is aligned within a second through hole cut out in the second level stack such that one of upper or a lower surface of the second component is substantially flush with an upper or a lower surface of the second level stack.

Abstract: A jointing device for metal mask plate welding includes a jointing device body. A height of the jointing device body is smaller than a welding height of a welding gun. The jointing device body has a through-hole corresponding to a welding area of a metal mask. A width of the through-hole is larger than a welding spot diameter of the welding gun. The jointing device body is used for jointing the metal mask to a metal mask receiving frame.

Abstract: A coil substrate includes insulating layers, and conductive layers laminated on the insulating layers in a plate thickness direction of the insulating layers, respectively. The conductive layers include three or more conductive layers and a set of conductive layers such that the set of conductive layers includes a first outermost conductive layer on one end side in the plate thickness direction and does not include a second outermost conductive layer on the opposite end side in the plate thickness direction and that the set of conductive layers includes coil portions each having a spiral form respectively and aligned in the plate thickness direction.

Abstract: A semiconductor package includes a connection member having a first surface and a second surface disposed to oppose each other and including an insulating member having a plurality of insulating layers and a plurality of redistribution layers disposed on the plurality of insulating layers, respectively; a semiconductor chip disposed on the first surface of the connection member and having connection pads electrically connected to the plurality of redistribution layers; and an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, wherein at least one of the plurality of redistribution layers includes a dummy electrode pattern in which a plurality of holes are arranged, and each of the plurality of holes has a shape including a plurality of protruding regions that protrude externally from different positions.

Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, an under bump supporting layer, an attachment layer and solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface and a patterned circuit layer disposed on the first surface, wherein an outer surface of the patterned circuit layer and the first surface are coplanar. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface to encapsulate the chip. The under bump supporting layer is disposed on the first surface and includes openings for exposing the outer surface. The attachment layer covers the inner surface of each opening and the exposed portion of the patterned circuit layer. The solder balls are disposed in the openings respectively and electrically connected to the patterned circuit layer.

Abstract: A coupled via structure includes a plate via penetrating through an board body and having first and second plates spaced apart from each other by a first gap distance, a contact pad connected to the plate via on a surface of the board body and having first and second contacts connected to the first and second plates, respectively, and a connection line connected to the contact pad on the surface of the board body and having first and second lines connected to the first and second contacts, respectively, and spaced apart from the first line by a second gap distance. Accordingly, the deviation of the characteristic impedance is reduced (or, alternatively, minimized) between the coupled via structure and the coupled signal line.

Abstract: A multilayer capacitor and a board having the same provide high capacitance and low equivalent series inductance (ESL). The multilayer capacitor includes a capacitor body including an active region, including first and second internal electrodes, and first and second cover regions. Third and fourth internal electrodes are alternately disposed in the cover region adjacent to a mounting surface. First and second external electrodes respectively contact the first and second internal electrodes to provide capacitance. First and second via electrodes are disposed in the cover region, where the first via electrode connects the third internal electrode and a first band portion of the first external electrode to each other, and where the second via electrode connects the fourth internal electrode and a second band portion of the second external electrode to each other.

Abstract: A multilayer capacitor includes: a capacitor body including an active region including a plurality of first and second internal electrodes alternately exposed, respectively, through opposite end surfaces of the capacitor body in a length direction, and upper and lower cover regions disposed on upper and lower surfaces of the active region, respectively; and first and second external electrodes formed on the opposite end surfaces of the capacitor body in the length direction, respectively. The lower cover region of the capacitor body may have a space portion.

Abstract: In one implementation, a multilayered printed circuit board is configured to redirect current distribution. The current may be distributed by steering, blocking, or otherwise manipulating current flows. The multilayered printed circuit board includes at least one power plane layer. The power plane layer does not distribute current evenly. Instead, the power plane layer includes multiple patterns with different resistances. The patterns may include a hatching pattern, a grid pattern, a directional pattern, a slot, a void, or a continuous pattern. The pattern is a predetermined spatial variation such that current flows in a first area differently than current flows in a second area.

Abstract: Insulating layers of a redistribution layer of a semiconductor package may be formed as a polymer film having inorganic fillers formed therein. The inorganic fillers may trap reactive materials to inhibit and/or substantially prevent the metal conductors, such as chip pads of the semiconductor chip being packaged, from being damaged by the reactive material. As a result, the reliability and the durability of the semiconductor package may be improved.

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface, and disposed in the recess portion so that the inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other, wherein the stopper layer includes an insulating material.

Abstract: A polymer film is applied onto a surface of a laminated printed circuit board subassembly having vias. Holes are created in the polymer film to access the vias while the polymer film remains covering adjacent areas. The polymer film with holes allows placement of hole-fill paste in the vias while preventing unwanted hole-fill paste placement or migration to adjacent areas. After filling the vias with hole-fill paste, the hole-fill paste is preferably at least partially hardened or cured, and the polymer film is preferably removed, facilitating further assembly of a printed circuit board without unwanted hole-fill paste in other areas which could be difficult to remove, The invention includes improved processes for fabricating printed circuit boards, and is particularly useful for irregular circuit boards and rigid flex circuit boards. The invention also includes covered laminated printed circuit board subassemblies, covered with a removable polymer film.

Abstract: Provided is a paste thermosetting resin composition containing solder powder, a thermosetting resin binder, an activator, and a thixotropy imparting agent. The solder powder has a melting point ranging from 100° C. to 240° C., inclusive. The thermosetting resin binder contains a main agent and a curing agent. The main agent contains a di- or higher functional oxetane compound.

Abstract: A package structure is provided. The package structure includes a molding compound. The package structure also includes an integrated circuit chip having a chip edge in the molding compound. The package structure further includes a passivation layer below the integrated circuit chip and the molding compound. In addition, the package structure includes a redistribution layer in the passivation layer. The package structure also includes first bumps electrically connected to the integrated circuit chip through the redistribution layer. The first bumps are inside the chip edge and arranged along the chip edge. The package structure further includes second bumps electrically connected to the integrated circuit chip through the redistribution layer. The second bumps are outside the chip edge and arranged along the chip edge. The first bumps are next to the second bumps. The first and second bumps are spaced apart from the chip edge.

Abstract: A package and method of manufacturing a package is disclosed. In one example, the package includes a carrier having an accommodation through hole. A component is arranged at least partially within the accommodation through hole. A connection structure connects the carrier with the component.

Abstract: A package system comprising a first interconnect structure arranged over a first surface of a first substrate; a plurality of first through silicon via (TSV) structures in and extending through the first substrate; a molding compound material surrounding the first substrate; at least one through via in the molding compound material with the through via being offset from the first substrate in a direction parallel to the first surface; a second interconnect structure over a second surface of the first substrate; and a first integrated circuit mounted over the first surface of the substrate, with the first integrated circuit being electrically coupled to at least one of the first TSV structures through the first interconnect structure and a connecting bump while the first interconnection structure is electrically coupled to the through via.

Abstract: A glazing includes at least one substrate, one portion of which includes an electrically conductive element, the conductive element including a connector made of chromium-containing steel, which connector is soldered with a solder based on tin, silver and copper to an electrically conductive track, wherein the electrically conductive track, which is formed by fritting a silver paste including a mixture of silver powder and glass frit, has a resistivity measured at 25° C. lower than or equal to 3.5 ??·cm and a porosity level lower than 20%, the porosity level being measured by scanning electron microscopy from a cross section through the portion of the substrate including the electrically conductive track and having been polished beforehand by ion milling.

Abstract: The electronic device includes a printed circuit board having a first main surface, an electronic part mounted on the first main surface, and a first connection member connecting the printed circuit board and the electronic part. The printed circuit board includes at least one projection formed on the first main surface so as to project in a direction crossing the first main surface. The projection is formed outside the bottom surface of the electronic part which is located at the side of the first main surface. The first connection member is in contact with at least part of the projection, at least part of the bottom surface of the electronic part, and at least part of a lateral surface of the electronic part intersecting the bottom surface.

Abstract: A surface-mounted integrated circuit (IC) package is disclosed that has unwanted flux removed from surface-mounted IC. A bottom termination component (BTC) includes lands and a thermal pad. The lands provide an electrical connection from the BTC and the thermal pad provides heat transfer from the BTC. The thermal pad includes vias that are configured to remove flux generated from solder applied to the surface-mounted IC as the surface-mounted IC is assembled. A printed circuit board (PCB) is mounted to the BTC and is electrically connected to the BTC via the lands and receives heat transfer from the BTC via the thermal pad and includes a reservoir. The reservoir is configured to pull flux positioned between the lands into the reservoir as the flux is generated from the solder applied to the surface-mounted IC as the BTC is mounted to the PCB and as the surface-mounted IC is assembled.

Abstract: A semiconductor die package includes a semiconductor die, a film for improving die warpage bonded to a first face of the semiconductor die, a plurality of electrically conductive bumps formed on a second face of the semiconductor die, a substrate onto which the electrically conductive bumps of the second face of the semiconductor die are bonded to electrically connect the semiconductor die and the substrate, and a mold compound applied these components to form an exposed surface of the semiconductor die package that is coplanar with an exposed surface of the film.

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers.

Abstract: There is provided a semiconductor device, enhanced with process capability and reliability by way of flow control of an adhesive material to fix semiconductor chips. The semiconductor device includes a first semiconductor chip including a first surface and a second surface opposite to each other, a flow regulating structure formed at the first surface of the first semiconductor chip, and a second semiconductor chip mounted on the first surface of the first semiconductor chip. The second semiconductor chip overlaps at least a portion of the flow regulating structure.

Abstract: A multi-piece wiring substrate includes a matrix substrate provided with dividing grooves arranged along boundaries of wiring substrate regions in a first principal face and a second principal face, the dividing grooves including first dividing grooves, second dividing grooves, third dividing grooves, and fourth dividing grooves, depths of the first dividing grooves and depths of the second dividing grooves being set to be greater than depths of the third dividing grooves and depths of the fourth dividing grooves, first curved parts being provided so that the depths of the third dividing grooves gradually increase as going toward respective corners of the wiring substrate regions, and second curved parts being provided so that the depths of the fourth dividing grooves gradually increase as going toward the respective corners of the wiring substrate regions.

Abstract: An electrical conductive module comprises: a circuit board, which has an upper side and a lower side opposite to each other in an up-down direction, the upper side of the circuit board is provided with a plurality of upper side pads, the lower side of the circuit board is provided with a plurality of lower side pads, the lower side pads and the upper side pads are provided in pairs, the lower side pad and the upper side pad in each pair are electrically connected together via a connecting through hole and printed wires which are provided alongside; the circuit board is provided with a plurality of conducting through holes for interposing the lower side pads and the upper side pads in different pairs; and a plurality of conducting posts, which each have a soldering end and a mating end opposite to each other in the up-down direction, the soldering end is soldered to the upper side pad on the circuit board correspondingly. The present disclosure can simplify structure and reduce production cost.

Abstract: Embodiments of the invention include flexible circuit board interconnections and methods regarding the same. In an embodiment, the invention includes a method of connecting a plurality of flexible circuit boards together comprising the steps applying a solder composition between an upper surface of a first flexible circuit board and a lower surface of a second flexible circuit board; holding the upper surface of the first flexible circuit board and the lower surface of the second flexible circuit board together; and reflowing the solder composition with a heat source to bond the first flexible circuit board and the second flexible circuit board together to form a flexible circuit board strip having a length longer than either of the first flexible circuit board or second flexible circuit board separately.

Abstract: A stacked package configuration is described that includes a bottom package and an upper package. The bottom package includes a substrate having a top surface with first circuitry and metal first pads. A molded layer is then formed over the substrate. Holes through the molded layer are then laser drilled to expose the first pads. The holes and first pads align with leads of an upper package, which contains further circuit components. The holes are then partially filled with a solder paste. A thermal epoxy is applied between the molded layer and the upper package. The leads of the upper package are then inserted into the holes, and the solder paste is reflowed to electrically, thermally, and mechanically connect the upper package to the bottom package. The reflow heat also cures the epoxy. A ball grid array is then formed on the bottom of the substrate.

Abstract: A method of producing an optoelectronic semiconductor component includes providing a carrier including two metal layers, wherein the metal layers are detachable from one another, securing an optoelectronic semiconductor chip on the first metal layer of the carrier, and mechanically detaching the second metal layer from the first metal layer.

Abstract: A printed circuit board (PCB) includes a first insulating layer, a pad disposed on the first insulating layer, and a first reference layer on which the first insulating layer is disposed, the first reference layer including a dielectric passage for forming a return path of a signal that is transmitted to the pad, and a conductive line disposed in the dielectric passage and disposed to form a transmission path of the signal. The PCB further includes a second insulating layer on which the first reference layer is disposed, and a second reference layer on which the second insulating layer is disposed, the second reference layer further forming the return path. A capacitance of the pad corresponds to a distance between the pad and the second reference layer.

Abstract: Provided are an electronic device employing a polymer nanosheet, having an electronic element and a conductive wiring that are connected to each other in a solder-free manner, and exhibiting a high conformability and adhesiveness to an object for attaching including a biological tissue such as skin; and a method for manufacturing the same. The electronic device includes the electronic element; and the polymer nanosheet adhering to the electronic element. Specifically, the polymer nanosheet adheres to the electronic element in a manner such that one surface of the electronic element is entirely covered by the polymer nanosheet. It is preferred that the polymer nanosheet have a thickness of smaller than 1 ?m. Further, a conductive wiring capable of being electrically connected to the electronic element; and a power source for supplying power to the electronic element, may also be formed on the polymer nanosheet.

Abstract: A method for manufacturing an electronic component attached board includes preparing a first support plate, forming aggregate wiring boards on the first plate such that the aggregate boards each including wiring board side by side are formed in connected state on surface of the first plate, separating the first plate from the aggregate boards, dividing the aggregate boards into individual aggregate boards each including the wiring boards, bonding a second support plate to surface of each individual aggregate board such that each individual aggregate board is bonded to surface of the second plate, mounting electronic components on the wiring boards on the second plate such that each wiring board has an electronic component thereon, dividing the wiring boards into individual wiring boards, and separating the second plate from the individual wiring board. The surface of the first plate has size larger than size of the surface of the second plate.

Abstract: Devices comprising at least two electrodes with a layer disposed therebetween are disclosed. In some embodiments, the layer disposed therebetween may be an insulator. In some embodiments, the layer may be capable of being deformed. Deforming the layer may cause a change in one or more materials properties of the device, such as the electrical properties and/or the optical properties of the device.

Abstract: A printed circuit board includes: a core member including a through-hole; a sub-circuit board disposed in the through-hole; a first insulating layer disposed on opposing surfaces of the core member and opposing surfaces of the sub-circuit board; and an insulating material disposed between an inner wall of the through-hole and the sub-circuit board.

Abstract: Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; a first encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; an electronic component disposed on the other surface of the frame opposing one surface of the frame in which the semiconductor chip is disposed; a second encapsulant covering at least portions of the electronic component; and a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer, wherein the connection pads and the electronic component are electrically connected to each other through the wiring layers and the redistribution layer.

Abstract: A printed circuit board according to an embodiment of the present invention, which is configured to be disposed on an inner surface of an airtight case having an opening so as to hermetically cover the opening, includes a shielding layer containing a liquid crystal polymer as a main component at least in a region covering the opening. An electronic component according to another embodiment of the present invention includes an airtight case having an opening and a printed circuit board disposed on an inner surface of the airtight case so as to hermetically cover the opening, wherein the printed circuit board includes a shielding layer containing a liquid crystal polymer as a main component at least in a region covering the opening.

Abstract: A fingerprint sensor package, including a sensing side for sensing fingerprint information and a separate connection side for electrically connecting the fingerprint sensor package to a host device, is disclosed. The fingerprint sensor package can also include a sensor integrated circuit facing the sensing side and substantially surrounded by a fill material. The fill material includes vias at peripheral locations around the sensor integrated circuit. The fingerprint sensor package can further include a redistribution layer on the sensing side which redistributes connections of the sensor integrated circuit to the vias. The connections can further be directed through the vias to a ball grid array on the connection side. Some aspects also include electrostatic discharge traces positioned at least partially around a perimeter of the connection side. Methods of manufacturing are also disclosed.