With Particular Conductive Connection (e.g., Crossover) Patents (Class 174/261)
  • Patent number: 10534890
    Abstract: An apparatus for detecting printed circuit board (“PCB”) design violations includes an analysis module that analyzes a position of a trace on a PCB design to determine conductivity of a design material over which the trace is being added and/or an electrical property of the trace at the position. The apparatus further includes an identification module that identifies, in real time, a void violation on the PCB design in response to the design material including a non-conductive material and/or a reference voltage violation on the PCB design in response to the position including a voltage and a notification module that notifies a user of the void violation and/or the reference voltage violation. At least a portion of said modules include hardware circuits, a programmable hardware device, and/or executable code stored on one or more non-transitory computer-readable storage media.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alberto Garza, Emile L. Kowalski, Julio A. Maldonado, Jose L. Rodriquez
  • Patent number: 10527509
    Abstract: A sensor such as a load cell includes a metal body containing the sensor electronics and flexure elements. Power is brought into the electronics and signals are taken out via header pins arranged in any of various groupings so as to extend through holes in the body. The pins are fixed by means of fused glass or ceramic material and the body is sealed to tolerate harsh environmental conditions.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 7, 2020
    Assignee: FUTEK Advanced Sensor Technology
    Inventors: Javad Mokhbery, Richard Walker, Maciej Lisiak
  • Patent number: 10528184
    Abstract: The invention includes a substrate, a touch sensor layer, an insulative film and a signal transmission layer. The touch sensor layer has sensing columns. Each sensing column has a first sensing electrode and second sensing electrodes. The first sensing electrode is connected to a first contact through a first transparent path. Each second sensing electrode is connected to a second contact through a second transparent path. The second contacts are arranged in the same order of the second sensing electrodes connected thereto. The insulative film covers the second contacts. The signal transmission layer has first signal wires, second signal wires and signal output terminals. Two end of each first signal wire are separately connected to the first contact and one of the signal output terminals. Each second signal wire connects the second contacts in a line and is connected to one of the signal output terminals.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: January 7, 2020
    Assignee: YOUNG FAST OPTOELECTRONICS CO., LTD.
    Inventors: Chih-Chiang Pai, Meng-Guei Lin, Chin-Fong Lin, Li-Yeh Yang, Chiu-Wen Chen
  • Patent number: 10530083
    Abstract: In some embodiments, an apparatus comprises a biosensing garment and an electronics assembly. The biosensing garment includes a sensor, a conductive pathway, and a connection region including one or more connectors that are disposed on a PCB. The connection region is electrically coupled to the conductive pathway and the sensor. The connection region is further configured to be electronically coupled to the electronics assembly via at least one conductive contact. In some embodiments, the electronics assembly includes at least one conductive contact that is configured to be electronically coupled to at least one portion of the PCB.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: January 7, 2020
    Assignee: HONEYWELL SAFETY PRODUCTS USA, INC.
    Inventor: Thierry Dumont
  • Patent number: 10518518
    Abstract: Smartcards with metal layers manufactured according to various techniques disclosed herein. One or more metal layers of a smartcard stackup may be provided with slits overlapping at least a portion of a module antenna in an associated transponder chip module disposed in the smartcard so that the metal layer functions as a coupling frame. One or more metal layers may be pre-laminated with plastic layers to form a metal core or clad subassembly for a smartcard, and outer printed and/or overlay plastic layers may be laminated to the front and/or back of the metal core. Front and back overlays may be provided. Various constructions of and manufacturing techniques (including temperature, time, and pressure regimes for laminating) for smartcards are disclosed herein.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: December 31, 2019
    Assignee: Féinics AmaTech Teoranta
    Inventors: David Finn, Mustafa Lotya, Darren Molloy
  • Patent number: 10510722
    Abstract: A semiconductor device includes a first electronic component, a second electronic component and a plurality of interconnection structures. The first electronic component has a first surface. The second electronic component is over the first electronic component, and the second electronic component has a second surface facing the first surface of the first electronic component. The interconnection structures are between and electrically connected to the first electronic component and the second electronic component, wherein each of the interconnection structures has a length along a first direction substantially parallel to the first surface and the second surface, a width along a second direction substantially parallel to the first surface and the second surface and substantially perpendicular to the first direction, and the length is larger than the width of at least one of the interconnection structures.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Weiming Chris Chen, Tu-Hao Yu, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
  • Patent number: 10483156
    Abstract: A method includes electrically joining two or more semiconductor chips to a silicon bridge chip, and electrically joining the two or more semiconductor chips to a substrate structure, the silicon bridge chip extends into a recess in the substrate structure such that a top surface of the silicon bridge chip is substantially flush with a top surface of the substrate structure.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10483222
    Abstract: A semiconductor device and a manufacturing method thereof are disclosed. A first insulation layer is formed on a semiconductor die, a redistribution layer electrically connected to a bond pad is formed on the first insulation layer, and a second insulation layer covers the redistribution layer. The second insulation layer is made of a cheap, non-photosensitive material. Accordingly, the manufacturing cost of the semiconductor device can be reduced.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: November 19, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Jong Sik Paek, Eun Sook Sohn, In Bae Park, Won Chul Do, Glenn A. Rinne
  • Patent number: 10477672
    Abstract: An electronic device includes a printed circuit board. The printed circuit board includes a plurality of different signaling planes and a plurality of different reference planes. A single ended via interconnects the plurality of different signaling planes. A return via interconnects the plurality of different reference planes. The electronic device includes a shared void that includes the single ended via and the return via.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: November 12, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Melvin K. Benedict, Karl J. Bois
  • Patent number: 10470294
    Abstract: Methods and systems for reducing the number of, and values of, passive components, such as capacitors, in System-in-Package devices below vendor recommendations for an active component are provided.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: November 5, 2019
    Assignee: OCTAVO SYSTEMS LLC
    Inventors: Erik James Welsh, Peter Linder
  • Patent number: 10470311
    Abstract: A printed circuit board (PCB) may include a plurality of horizontally disposed signal layers. The PCB may include a first vertically disposed differential via electrically connected to a first horizontally disposed signal layer, of the plurality of horizontally disposed signal layers, and a second horizontally disposed signal layer of the plurality of horizontally disposed signal layers. The PCB may include a second vertically disposed differential via electrically connected to the first signal horizontally disposed layer and the second horizontally disposed signal layer. The PCB may include a first set of clearances encompassing the first vertically disposed differential via and the second vertically disposed differential via, a second set of clearances encompassing the first vertically disposed stub, and a third set of clearances encompassing the second vertically disposed stub.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 5, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: Matthew Twarog, Hui He, Thomas W. Jetton
  • Patent number: 10468362
    Abstract: A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: November 5, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Hiroki Yamamoto
  • Patent number: 10462907
    Abstract: A printed 3D functional part includes a 3D structure comprising a structural material, and at least one functional electronic device is at least partially embedded in the 3D structure. The functional electronic device has a base secured against an interior surface of the 3D structure. One or more conductive filaments are at least partially embedded in the 3D structure and electrically connected to the at least one functional electronic device.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: October 29, 2019
    Assignee: President and Fellows of Harvard College
    Inventors: Jennifer A. Lewis, Michael A. Bell, Travis A. Busbee, John E. Minardi, II
  • Patent number: 10462901
    Abstract: Methods and structures are provided for implementing embedded wire repair for printed circuit board (PCB) constructs. A repair wire layer is provided within the PCB stack with reference planes on opposite sides of the repair wire layer. When a repair connection is required, an appropriate plated through hole (PTH) is drilled to form the repair connection using the repair wire layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: October 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Samuel Connor, Stuart B. Benefield, Matthew S. Doyle, Joseph Kuczynski, Jonathan Jackson
  • Patent number: 10453782
    Abstract: A multi-row wiring member for semiconductor device configured of a plurality of wiring members arrayed in a matrix includes a permanent resist, a first plating layer forming internal terminals, a plating layer forming wiring portions and a second plating layer forming external terminals. The first plating layer is formed in the permanent resist with lower faces thereof uncovered in the bottom surface of the permanent resist. The plating layer forming wiring portions is formed on the first plating layer in the permanent resist. The second plating layer is formed in the permanent resist on partial areas within areas of the plating layer forming wiring portions, with upper faces thereof being uncovered on a top-surface side of the permanent resist. On a bottom-surface side of the permanent resist, a metal frame is formed at the margin around an aggregate of individual wiring members for semiconductor devices arrayed in a matrix.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 22, 2019
    Assignee: OHKUCHI MATERIALS CO., LTD.
    Inventors: Kaoru Hishiki, Ichinori Iidani
  • Patent number: 10438883
    Abstract: A wiring board includes an insulator layer having a top surface, and a plurality of pads arranged in a pad arrangement region on the top surface of the insulator layer. The pad arrangement region includes a first region in which a first plurality of pads among the plurality of pads are arranged at a first density, and a second region in which a second plurality of pads among the plurality of pads are arranged at a second density lower than the first density. At least one dummy pad is arranged juxtaposed to at least one of the second plurality of pads in the second region of the pad arrangement region.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: October 8, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kei Imafuji
  • Patent number: 10438814
    Abstract: An object is to provide a novel method in place of the above-described conventional technology, as a technique for obtaining a thin film with a wiring pattern applied. A method for manufacturing a wiring pattern according to the present invention is characterized in that the method includes: a laminate forming step of forming a laminate by bringing a first member that has a resist layer and a metal layer formed on the resist layer into contact with a second member that includes a substrate; a resist layer patterning step of subjecting the resist layer to patterning; and an etching step of selectively removing the metal layer.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: October 8, 2019
    Assignee: NIKON CORPORATION
    Inventors: Makoto Nakazumi, Yasutaka Nishi, Kei Nara
  • Patent number: 10431542
    Abstract: An interconnect structure is provided in which a seed enhancement spacer is present on vertical surfaces, but not a horizontal surface, of a diffusion barrier liner that is located in an opening present in an interconnect dielectric material layer. An interconnect metal or metal alloy structure is present on physically exposed sidewalls of the seed enhancement spacer and on the physically exposed horizontal surface of the diffusion barrier liner.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Joseph F. Maniscalco, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10427585
    Abstract: An electrical power supply device for at least one light source of the light emitting diode type and at least one electronic component, including a circuit for driving the electrical power supply of the light source or each light source, the drive circuit including at least one electrical conductor track and a housing for accommodating an insert, and an insert in an electrically conducting material, the insert being inserted in the accommodation housing and including a first end portion electrically connected to the conductor track, and a second end portion suited to being electrically connected to at least one electronic component so as to supply electrical power to the electronic component.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: October 1, 2019
    Assignee: VALEO ILUMINACION
    Inventors: Jose-David Roldan, Miguel-Angel Pena, Antonio Domingo Illan
  • Patent number: 10412841
    Abstract: A FPCB includes a base layer defining at least one first through hole. A conductive paste block is formed in each first through hole. Each conductive paste block includes a first and a second end portion. The base layer has opposite surfaces, and a first conductive wiring layer is formed on each surface of the base layer. The first end portion at least protrudes from the base layer and is exposed from the first conductive wiring layer. An insulating layer and a second conductive wiring layer are formed on each first conductive wiring layer. At least one second through hole is defined in each insulating layer. The second through hole positioned near the first end portion extends to the first end portion and forms a recess. A conductive via is formed in each second through hole and the corresponding recess, and is electrically connected to the conductive paste block.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: September 10, 2019
    Assignees: Avary Holding (Shenzhen) CO., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.
    Inventor: Tzu-Chien Yeh
  • Patent number: 10408420
    Abstract: A light emitting device includes a light emitting element with first and second electrodes formed on the same surface side; a base with first and second conductive members, each including a wide part facing the an electrode and a narrow part extending away from the wide part; first and second bonding members each electrically connecting a corresponding electrode with a conductive member, and continuously covering the wide and narrow parts of a corresponding conductive member; and one or more light reflecting members at least partially covering the conductive members.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: September 10, 2019
    Assignee: NICHIA CORPORATION
    Inventor: Kazuhiro Kamada
  • Patent number: 10395832
    Abstract: A method of manufacturing an electronic component includes forming a component body into which elements are built; and a metal plate electrode that is joined to the component body by conductive paste so as to be electrically coupled to the elements, the metal plate electrode exceeding in size a surface of the component body onto which the conductive paste is deposited.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 27, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Tomokazu Nakashima, Masayuki Itoh, Yoshinori Mesaki
  • Patent number: 10396339
    Abstract: A bi-metal tab includes an internal tab segment that can be coupled to a battery cell terminal within an interior of the cell and an external tab segment that can be coupled to an element external to the cell. One tab segment includes a pin tab segment that comprises a pin, and another tab segment includes a socket tab segment comprised of a separate metal material, that comprises a socket. The socket can be at least partially enclosed, on at least two opposing sides, by the structure of the socket tab segment, and the socket and pin of the separate segments can be configured to couple, to form the tab, where at least two surfaces of the pin are in flush contact with the socket tab segment structure. A protection layer that restricts electronic transport across the tab based on exposure to particular physical conditions can be included between the tab segments.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: August 27, 2019
    Assignee: Apple Inc.
    Inventors: Qingcheng Zeng, Donald G. Dafoe, Andrew Chu, Ashley S. Harvey, Junwei Jiang
  • Patent number: 10383221
    Abstract: An aspect of the present invention makes it possible to reduce stress at a boundary between a coverlay and a terminal section of a flexible circuit board and reduce the possibility of disconnection in the terminal section in the flexible circuit board. An aspect of the present invention provides a flexible circuit board including: a reinforcing plate bonded to a whole of a terminal section and a portion of a coverlay; and a flexible plate including a holding portion and a bonding portion, the flexible plate bonding to the coverlay via only the bonding portion, the flexible plate being spaced apart from the reinforcing plate.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: August 13, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Ryohsuke Sugiyama, Takayuki Yanagi
  • Patent number: 10374313
    Abstract: A multilayer electronic component includes a body and a coil. The body includes a plurality of sheets each containing magnetic powder particles. The coil includes an uppermost coil pattern disposed on a top surface of an uppermost sheet among the plurality of sheets, a lowermost coil pattern disposed on a bottom surface of a lowermost sheet among the plurality of sheets, and side coil patterns disposed on edges of central sheets disposed between the uppermost sheet and the lowermost sheet in a central portion of the body. The magnetic powder particles have shape anisotropy, and a major axes of the magnetic powder particles are aligned with each other within the body. A multilayer chip antenna can include the multilayer electronic component.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Soon Kwang Kwon, Chang Ryul Jung, Jung Wook Seo, In Gyu Kim
  • Patent number: 10371719
    Abstract: A printed circuit board (PCB) test fixture includes a substrate, a first insulation layer formed on the substrate, a conductor layer formed on the first insulation layer and electrically connected to the upper electrodes through at least one first connection member, a second insulation layer formed on the first insulation layer, and multiple conductive cones arranged on the second insulation layer in a matrix form. A part of the conductive cones is electrically connected to the conductor layer through at least one second connection member. The circuit layout of the conductor layer, the at least one first connection member and the at least one second connection member is employed to supply testing power to a part of the conductive cones and an adjustable arrangement of the conductive cones to enhance density of test probes upon electrical testing.
    Type: Grant
    Filed: April 17, 2016
    Date of Patent: August 6, 2019
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Chiao-Cheng Chang, Yi-Nong Lin
  • Patent number: 10367117
    Abstract: The present invention provides an apparatus and a method for transferring micro light-emitting diodes. Said apparatus for transferring the micro light-emitting diodes comprises a main body, and a spraying module, a cooling module and a heating module disposed on said main body. The spraying module sprays metallic adhesive liquid onto the micro light-emitting diodes that wait to transfer, the cooling module cools the metallic adhesive liquid on the wait-to-transfer micro light-emitting diodes, thereby curing the metallic adhesive liquid to adhesively bond the main body with the wait-to-transfer micro light-emitting diodes together implementing the transfer of the micro light-emitting diodes, After transferred to reach the position, the cured metallic adhesive liquid is heated by the heating module, thereby melting the metallic adhesive liquid to separate the main body from the wait-to-transfer micro light-emitting diodes.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: July 30, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Macai Lu, Jiangbo Yao
  • Patent number: 10356904
    Abstract: The invention relates to an electronic device having an electrically isolating support structure, an electrically conducting conductor path on a surface of the support structure, and an electrically conducting contact structure which extends from the surface into the support structure and is electrically connected to the conductor path at a connection point, thereby forming a common conductor track. The conductor path and the contact structure transition into each other in an enlargement-free manner at the connection point.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: July 16, 2019
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellshaft
    Inventors: Johannes Stahr, Wolfgang Schrittwieser, Mike Morianz, Christian Vockenberger, Markus Leitgeb
  • Patent number: 10340056
    Abstract: A flat cable includes at least one cable portion and at least one rib portion. The at least one cable portion has a plurality of conductor wires arranged in parallel at predetermined intervals on a plane, and a coating portion that collectively covers the plurality of conductor wires arranged in parallel. The coating portion is made of an insulating resin. The at least one rib portion is provided in parallel with the cable portion on the plane. bus bar is to be fixed to the at least one rib portion and the at least one rib portion is made of only the same resin as the coating portion. A body including the at least one cable portion and the at least one rib portion is substantially bilaterally symmetrical in a cross-sectional structure of the body.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: July 2, 2019
    Assignee: YAZAKI CORPORATION
    Inventor: Takeshi Oshima
  • Patent number: 10339968
    Abstract: Provided is a base unit for use in a disk drive apparatus including a motor arranged to be capable of rotating about a central axis extending in a vertical direction. The base unit includes a base member arranged to extend radially to support the motor, and including a predetermined adhesion region and an outside region outside of the adhesion region; and a connector electrically connected to a wire arranged on the base member. The connector is adhered to the base member through an adhesive at the adhesion region of the base member. A wettability of the adhesive on the adhesion region is higher than a wettability of the adhesive on the outside region of the base member.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: July 2, 2019
    Assignee: NIDEC CORPORATION
    Inventors: Shingo Suginobu, Takumi Shimomura, Masahiro Imahori
  • Patent number: 10340576
    Abstract: A zero insertion loss directional coupler includes an input port, an antenna port, an isolation port, and a detect port. The coupler has a first signal trace, a second signal trace, and an inductive winding. The first signal trace is on one of two layers and is connected to the input port and the antenna port, while the inductive winding is on another one of the two layers. A first terminal of the inductive winding is connected to the isolation port. A first terminal of the second signal trace is connected to the detect port and a second terminal of the second signal trace is connected to a second terminal of the inductive winding.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: July 2, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Lisette L. Zhang, Oleksandr Gorbachov
  • Patent number: 10325853
    Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Wei Lin, Ming-Da Cheng
  • Patent number: 10304787
    Abstract: Void formation in a semiconductor device is to be prevented. The semiconductor device includes a semiconductor element, signal lines, and a protective layer. In the semiconductor device, the semiconductor element is mounted on a substrate. The signal lines in the semiconductor device are connected to the semiconductor element on the substrate. Further, the protective layer in the semiconductor device is provided in an inter-line region interposed between both edges of two adjacent signal lines among the signal lines on the substrate.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: May 28, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Jun Suzuki
  • Patent number: 10293627
    Abstract: A printed matter is provided. The printed matter includes a porous printing medium and a printed layer. The printed layer contains silver and has a printed surface having an image clarity (2 mm), defined in Japanese Industrial Standards H8686-2, of 5.0 or more and a b* value in the range of from ?7.0 to +4.0.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: May 21, 2019
    Assignee: Ricoh Company, Ltd.
    Inventors: Tatsuya Tomura, Yoshimasa Miyazawa, Takuya Fujita
  • Patent number: 10297935
    Abstract: The invention discloses a circuit board output structure, which includes a power output section disposed on a circuit board and at least one metal connection stand electrically connected to the power output section. Each metal connection stand includes a first connection piece showing an included angle with respect to the circuit board. A plurality of connection holes for electrically connecting output wires are formed on the first connection piece. When it is required to change an output specification, the replacement can be more simple and convenient since the metal connection stand may be directly replaced without replacing the whole circuit board. Because the first connection piece has the included angle specified with respect to the circuit board, R angle and stress of the inserted output wires may be reduced to prevent the output wires from damage, detaching from the circuit board or having poor electrical contact after the assembly.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: May 21, 2019
    Assignee: 3Y POWER TECHNOLOGY (TAIWAN), INC.
    Inventors: Shao-Feng Lu, Chuan-Kai Wang
  • Patent number: 10290959
    Abstract: Provided is a cable mounting substrate for mounting plural cables each of which includes a center conductor, an insulation covering the center conductor and an outer conductor covering the insulation. The cable mounting substrate includes a plate-shaped base, a ground pattern that is arranged on the base and electrically connected to the outer conductor, and a solder member that is provided on the ground pattern and is melted to electrically connect and fix the outer conductor to the ground pattern. The solder member includes a recessed portion having a shape along an outer shape of the outer conductor.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: May 14, 2019
    Assignee: Hitachi Metals, Ltd.
    Inventors: Takashi Kumakura, Hideharu Nagai
  • Patent number: 10292263
    Abstract: The invention provides transient printed circuit board devices, including active and passive devices that electrically and/or physically transform upon application of at least one internal and/or external stimulus.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: May 14, 2019
    Assignee: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS
    Inventors: John A. Rogers, Xian Huang
  • Patent number: 10283270
    Abstract: An electronic component includes: a component body into which elements are built; and a metal plate electrode that is joined to the component body by conductive paste so as to be electrically coupled to the elements, wherein the metal plate electrode exceeds in size a surface of the component body onto which the conductive paste is deposited.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: May 7, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Tomokazu Nakashima, Masayuki Itoh, Yoshinori Mesaki
  • Patent number: 10262906
    Abstract: The method of manufacturing a functional inlay, comprises at least the steps of: (1) providing a substrate with a wire antenna embedded therein and with an aperture wherein two wire antenna portions are positioned over said aperture; (2) acquiring the positions and the dimensions of said wire antenna portions and of said aperture; (3) determining if the acquired positions and dimensions meet predetermined tolerances; (4) if the acquired dimensions and positions meet said tolerances, then placing a chip in fie aperture so that said wire portions are positioned over connections pads of said chip and then bonding said wire portions to said connection pads.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: April 16, 2019
    Assignee: ASSA ABLOY AB
    Inventors: Laurent Pellanda, Julien Richard
  • Patent number: 10257921
    Abstract: Embedded air gap transmission lines and methods of fabrication are provided. An apparatus having an air gap transmission line can include a first conductive plane, a core dielectric layer having a bottom surface in contact with the first conductive plane, a conductor having a bottom surface in contact with a top surface of the core dielectric layer, and a second conductive plane positioned over, and spaced apart from, a top surface of the conductor such that a gap separates the conductor from the second conductive plane. The top surface of the conductor is separated from the bottom surface of the second conductive plane by a first distance measured along an axis normal to the first conductive plane, and the bottom surface of the conductor is separated from the first conductive plane by a second distance greater than the first distance measured along the axis.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: April 9, 2019
    Assignee: Google LLC
    Inventors: Richard Roy, Pierre-luc Cantin, Teckgyu Kang, Woon Seong Kwon
  • Patent number: 10256175
    Abstract: A printed wiring board includes a support plate, a laminate formed on the support plate and including first conductor pads on a first surface side of the laminate and second conductor pads on a second surface side of the laminate, and a solder resist layer interposed between the support plate and the laminate and having openings formed such that the openings are exposing the first conductor pads respectively. The laminate includes a resin insulating layer and has a first surface on the first surface side and a second surface on the second surface side on the opposite side with respect to the first surface of the laminate, the second conductor pads are embedded in the second surface of the laminate such that the second conductor pads have surfaces recessed from the second surface of the laminate respectively.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: April 9, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Teruyuki Ishihara, Hiroyuki Ban, Haiying Mei
  • Patent number: 10251277
    Abstract: A bridge section 12 is disposed in an area where mounting sections 11 are opposed to each other such that it is displaced toward a predetermined side. Accordingly, even if the line width of the bridge section 12 is formed larger than that in the related art, the self-alignment phenomenon can occur appropriately in a reflow process. It is thus possible to provide a resin-sealed module having high resin-charging properties and including a circuit substrate on which the bridge section 12 is not broken even if the size of a common land electrode 10 is reduced in accordance with a smaller size of a circuit component 5 and on which a sufficient gap between plural circuit components 5 mounted on the circuit substrate is reliably secured.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: April 2, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shota Ishihara, Tetsuya Oda, Tatsunori Kan, Kenichi Atsuchi
  • Patent number: 10244629
    Abstract: An apparatus that includes: a printed circuit board (PCB) that includes: a multilayer lamination of one or more ground layers, one or more power layers, and multiple signal layers; multiple vias that pass through one or more layers of the multilayer lamination, wherein a first via of the multiple vias includes: a first portion that has a first diameter, and a second portion that has a second diameter that is smaller than the first diameter, wherein a second via of the multiple vias includes: a third portion that has a third diameter, and a fourth portion that has a fourth diameter that is smaller from the third diameter; and wherein the first portion of the first via is adjacent to the fourth portion of the second via and the second portion of the first via is adjacent to the third portion of the second via is disclosed.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: March 26, 2019
    Assignee: Innovium, Inc.
    Inventors: Vittal Balasubramanian, Yongming Xiong
  • Patent number: 10242605
    Abstract: A display device and chip bonding method thereof are provided. The display device includes a flexible display panel and a chip bonded to the non-display area of the flexible display panel with the extension directions of individual bumps satisfying, depending on the area in which the bumps are located, the following requirements: in each row of bumps, at least the individual bumps in lateral zones have their extension lines on the same side converging at a same point on the reference line, and the two bumps belong to a same bump group have their extension lines respectively forming an angle with respect to the reference line, the angles being equal to each other.
    Type: Grant
    Filed: November 5, 2016
    Date of Patent: March 26, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Liqiang Chen, Hong Li
  • Patent number: 10234644
    Abstract: The optical-electrical printed circuit board disclosed herein includes a waveguide link assembly and a printed circuit board assembly. The printed circuit board assembly has first and second PCB layers between which optical waveguides of the waveguide link assembly are disposed. The end faces the optical waveguides are accessible through an access aperture in the printed circuit board assembly. An optical interconnector can be used to optically connect the optical waveguides to waveguides of an optical-electrical integrated circuit operably disposed on the printed circuit board assembly to form a photonic device. A waveguide bending structure can be used to bend the optical waveguides to facilitate optical coupling to the optical interconnector or directly to the waveguides of the optical-electrical integrated circuit. Methods of forming an optical-electrical printed circuit board, a photonic assembly and a photonic device are also disclosed.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: March 19, 2019
    Assignee: Corning Optical Communications LLC
    Inventors: Douglas Llewellyn Butler, James Scott Sutherland
  • Patent number: 10229042
    Abstract: A technique relates comparing content. A first set of content in a first document and a second set of content in a second document are normalized. The first set of content in the first document and the second set of content in the second document are tokenized. The first set of content having been tokenized and the second set of content having been tokenized are compared in order to find differences in the second set of content with respect to the first set of content. The differences are compiled in a changes map. The differences in the changes map are analyzed to determine types of the differences in the first set of content and the second set of content, and predefined differences are to be excluded. A report of the differences is generated, and the report delineates the types of the differences while excluding the predefined differences.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Scott B. Greer, Rosalind Toy A. Radcliffe, Justin Z. Spadea, Timothy W. Wilson
  • Patent number: 10224682
    Abstract: A coaxial cable includes a coaxial wire in which an inner insulator, an outer conductor and a sheath are sequentially and coaxially provided around a center conductor, and a substrate having a surface on which a first contact pad and a second contact pad are arranged. The sheath is removed at one end portion of the coaxial wire by a predetermined length, so that the inner insulator and the outer conductor are exposed, and a tip end of the inner insulator is removed by a predetermined length, so that the center conductor is exposed. The exposed portion of the center conductor is soldered to the first contact pad with the exposed portion of the inner insulator being bent relative to the sheath, and the exposed portion of the outer conductor is soldered to the second contact pad with being bent in a direction different from the bending direction of the inner insulator. A part of the coaxial wire covered by the sheath is standing at an angle of 30° or greater relative to the surface of the substrate.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 5, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yoshimasa Watanabe, Kazuhiro Sato, Hitomi Yoshida
  • Patent number: 10219372
    Abstract: A flexible printed board electrically connected to an electronic component (for example, a liquid crystal panel) by thermal compression bonding, including a flexible substrate, a terminal portion formed on one surface of the flexible substrate and having a plurality of connection terminals to be connected to the electronic component, a wire portion having a plurality of wires formed on the other surface of the flexible substrate, and a plurality of through wires formed inside through holes penetrating the flexible substrate in a compression bonding connection area to the electronic component of the terminal portion to connect the connection terminals of the terminal portion and the respective wires of the wire portion.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: February 26, 2019
    Assignee: FUJIKURA LTD.
    Inventors: Yuki Ishida, Yusuke Nakatani
  • Patent number: 10191180
    Abstract: A detector assembly includes an insulating substrate, a printed circuit board, a resistive, plate, a drilled board, a drift volume, and a cathode. A surface of the printed circuit board exposed to the resistive plate includes printed circuit lines for measuring first and second coordinates of a charge event. A mechanical assembly applies a force between the insulating substrate and the resistive a plate to form an electrical contact between the printed circuit lines on the printed circuit board and the resistive plate without the use of an electrical adhesive.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: January 29, 2019
    Assignee: Lingacom Ltd.
    Inventors: David Yaish, Yosef Kolkovich, Amnon Harel
  • Patent number: 10185042
    Abstract: Provided are an array substrate of an X-ray detector, a digital X-ray detector including the same, a method for manufacturing an array substrate of an X-ray detector, and a method for manufacturing an X-ray detector. More specifically, provided are an array substrate of an X-ray detector which is capable of tracking a defective line with high accuracy since the array substrate includes a first line extended in a first direction, a second line extended in the first direction and apart from the first line, and a plurality of line identifiers provided between the first line and the second line, a digital X-ray detector including the same, a method for manufacturing an array substrate of an X-ray detector, and a method for manufacturing an X-ray detector.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: January 22, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: JaeHo Yoon, MoonSoo Kang, JaeKwang Lee, ShiHyung Park