Abstract: Disclosed is key button (4) that includes a display surface on which character section (A) is formed, and a side face extending in a direction to intersect the display surface. The key button further includes transmission section (6) made of a light transmissive material, which constitutes the display surface and the side face, and shielding section (7) made of a light shielding material, which covers only a part of transmission section (6) other than character section (A) of the display surface.

Abstract: A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/° C., and a second element at the second side can comprise a plurality of insulated structures separated from one another by at least one gap. Conductive structure extends through at least one insulated structure and is electrically coupled with the terminals and the conductive elements. The at least one gap can reduce mechanical stress in connections between the terminals and another component.

Abstract: A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.

Abstract: A wiring board includes a first resin insulating layer, conductor pads on the first insulating layer including first and second conductor pads, a second resin insulating layer on the first insulating layer covering the first and second pads, an outermost conductor layer on the second insulating layer including first and second outermost wiring layers, via conductors through the second insulating layer including a first via conductor connecting the first wiring layer and first pad and a second via conductor connecting the second wiring layer and second pad, and a solder resist layer on the second insulating layer such that the solder resist layer is covering the first wiring layer and has one or more openings exposing the second wiring layer. The first wiring layer includes first main metal, and the second wiring layer includes second main metal which is different from the first metal of the first wiring layer.

Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.

Abstract: A wiring substrate includes, a base wiring substrate including a first wiring layer, a first insulating layer in which the first wiring layer is buried and a first via hole is formed under the first wiring layer, and a second wiring layer formed under the first insulating layer and connected to the first wiring layer through the first via hole, and a re-wiring portion including a second insulating layer formed on the base wiring substrate and having a second via hole formed on the first wiring layer, and a re-wiring layer formed on the second insulating layer and connected to the first wiring layer through the second via hole. The re-wiring layer is formed of a seed layer and a metal plating layer provided on the seed layer, and the seed layer is equal to or wider in width than the metal plating layer.

Abstract: A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter.

Abstract: A printed circuit board includes a first, second, and third dielectric layers, and a first, second, and third trace layers. The first trace layer and the second trace layer are formed on opposite surfaces of the first dielectric layer. The second dielectric layer is formed on the second trace layer, a first blind hole is defined in the first surface and terminated at a position in the first dielectric layer, a first conductive via is formed in the first blind hole. A second blind hole is formed in the second dielectric layer and the first dielectric layer. A second conductive via is formed in the second blind hole. The third trace layer is electrically connected with the second conductive via. The first trace layer is electrically connected with the second trace layer through the first conductive via and the second conductive via.

Abstract: A printed circuit board with circuit visible includes a wiring layer, a first adhesive layer, a first dielectric layer, and a cover film, which are stacked in described order, the wiring layer comprising at least one electrical contact pad. The cover film has at least one opening corresponding to the electrical contact pad. The cover film includes a second dielectric layer and a second adhesive layer. A flow initiation temperature of the first adhesive layer is in a range from 85 degrees centigrade to 90 degrees centigrade, and a hardening temperature of the first adhesive being lower than 150 degrees centigrade.

Abstract: An electronic device may include a display. The display may be an organic light-emitting diode display. The organic light-emitting diode display may have a substrate layer, a layer of organic light-emitting diode structures, and a layer of sealant. Vias may be formed in the substrate layer by laser drilling. The vias may be filled with metal using electroplating or other metal deposition techniques. The vias may be connected to contacts on the rear surface of the display. Components such as flexible printed circuits, integrated circuits, connectors, and other circuitry may be mounted to the contacts on the rear surface of the display.

Abstract: A fan-out wafer level package is provided. The fan-out wafer level package includes a semiconductor element, a molding compound, a first fan-out structure, a conductive heat spreader, and a plurality of solder balls. The semiconductor element includes a plurality of bonding pads. The molding compound covers the semiconductor element. The first fan-out structure is formed on the semiconductor element, wherein the first fan-out structure has a plurality of fan-out contacts electrically connected to the bonding pads. The conductive heat spreader is formed on the first fan-out structure, wherein the conductive heat spreader has a plurality of through holes filled with a conductive material. The solder balls are formed on the conductive heat spreader, wherein the solder balls are electrically connected to the first fan-out structure via the through holes filled with the conductive material.

Abstract: An embodiment of a stacked structure includes: a first substrate that includes a first electrode; a second substrate that includes a second electrode; and an adhesive resin material that is provided between the first substrate and the second substrate and includes a plurality of conductive vias, the plurality of conductive vias electrically connecting the first electrode and the second electrode.

Abstract: The present invention relates to a via structure having an open stub and a printed circuit board having the same. In accordance with an embodiment of the present invention, a via structure having an open stub including: a signal transmission via passing through an insulating layer; upper and lower via pads for connecting first and second transmission lines, which are respectively formed on and under the insulating layer, and the signal transmission via; and at least one open stub connected to an outer periphery of each via pad to have a shunt capacitance with each ground pattern formed on and under the insulating layer is provided. Further, a printed circuit board with a via having an open stub is provided.

Abstract: An interposer has conductive elements at a first side and terminals at a second side opposite therefrom, for connecting with a microelectronic element and a second component, respectively. The component includes a first element having a thermal expansion coefficient less than 10 ppm/° C., and an insulating second element, with a plurality of openings extending from the second side through the second element towards the first element. A conductive structure extending through the openings in the second element and through the first element electrically connects the terminals with the conductive elements.

Abstract: A wiring board includes a substrate having first and second surfaces and a first penetrating hole through the substrate, a first conductive circuit on the first surface of the substrate, a second conductive circuit on the second surface of the substrate, an interlayer insulation layer on the substrate and the first or second circuit, and a third conductive circuit on the interlayer layer. The interlayer layer has a via conductor in the interlayer layer and connecting the third circuit and the second conductor. The substrate has a first through-hole conductor connecting the first and second circuits and on the inner wall of the first hole, a filler filled inside the first conductor and forming a second penetrating hole, and a second through-hole conductor in the second hole. The via conductor is shifted from the center of the second conductor in the direction parallel to the first surface of the substrate.

Abstract: A fin field effect transistor including a first insulation region and a second insulation region over a top surface of a substrate. The first insulation region includes tapered top surfaces, and the second insulation region includes tapered top surfaces. The fin field effect transistor further includes a fin extending above the top surface between the first insulation region and the second insulation region. The fin includes a first portion having a top surface below the tapered top surfaces of the first insulation region. The fin includes a second portion having a top surface above the tapered top surfaces of the first insulation region.

Abstract: A printed circuit board includes: a first insulating layer; a second insulating layer of which one surface is formed to be in contact with the other surface of the first insulating layer; a first circuit pattern formed to be embedded in one surface of the first insulating layer; a second circuit pattern formed to be embedded between the first insulating layer and the second insulating layer; a third circuit pattern formed to be protruded from the other surface of the second insulating layer; and a landless fill-plating layer for filling a hole which penetrates the first insulating layer.

Abstract: A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.

Abstract: A wiring board includes a first multilayer wiring board having first conductive layers and having a surface, a second multilayer wiring board having second conductive layers and positioned such that the second multilayer wiring board has a surface facing the surface of the first multilayer wiring board, and an adhesive layer including an adhesive sheet and interposed between the first multilayer wiring board and the second multilayer wiring board such that the adhesive layer is adhering the first multilayer wiring board and the second multilayer wiring board. The first multilayer wiring board has a first pad on the surface of the first multilayer wiring board, the second multilayer wiring board has a second pad on the surface of the second multilayer wiring board, and the first pad and the second pad are positioned such that the first pad and the second pad face each other across the adhesive layer.

Abstract: A printed circuit board includes a motherboard and a daughterboard. The motherboard includes at least one first signal pad and defines at least one via under the at least one first signal pad. The daughterboard includes at least one second signal pad and defines at least one via under the at least one second signal pad. The at least one first signal pad and the at least one second signal pad are sucked into the respective vias on the motherboard and the daughterboard according to siphon principle to allow each of the first signal pads and the second signal pads to form uneven top surfaces, the uneven top surfaces of the at least one first signal pads and the at least one second signal pads are connected to each other for electronically connecting the daughterboard to the motherboard.

Abstract: Provided is a circuit board having a tie bar buried therein. The circuit board includes a dielectric stack, at least a first tie bar, at least a first gold finger and at least a first microvia. The dielectric stack includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located on the second dielectric layer. The dielectric stack includes a wireline region and a gold finger region. The first tie bar is buried in the gold finger region between the first dielectric layer and the second dielectric layer. The at least a first gold finger is located in the gold finger region on the first dielectric layer. The first microvia is located in the gold finger region in the first dielectric layer, and electrically connects the first gold finger to the first tie bar.

Abstract: One aspect relates to an electrical bushing for use in a housing of an implantable medical device. The electrical bushing includes at least one electrically insulating base body and at least one electrical conducting element. The electrical bushing includes a holding element to hold the electrical bushing in or on the housing. The conducting element is set-up to establish, through the base body, at least one electrically conductive connection between an internal space of the housing and an external space. The conducting element is hermetically sealed with respect to the base body. The at least one conducting element includes at least one cermet. The holding element is made, to at least 80% by weight with respect to the holding element, from a material selected from the group consisting of a metal from any of the subgroups IV, V, VI, VIII, IX, and X of the periodic system.

Abstract: In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location.

Abstract: A method of and device for forming vias on an electronic board (such as a PCB board) comprises forming one or more holes on the electronic board, placing a nanomaterial inside the one or more holes, and forming one or more filled holes on the electronic board. The nanomaterial can be nanocopper, which can be either push/pull into the holes on the electronic board or a combination of push and pull. The push/pull can be performed by using a mechanical device or by a person. A capping layer can be on both side of the via. The vias formed by using the nanomaterials provides a high efficient vertical heat transferring path from one side of the electronic board to the other side of the electronic board.

Abstract: A flexible multilayer substrate includes a multilayer body including a plurality of laminated resin layers. The multilayer body includes an innermost surface, which is a surface on an inner side when the substrate is bent, and an outermost surface, which is a surface on an outer side when the substrate is bent. Each of the plurality of resin layers includes a skin layer on one surface. Lamination of the multilayer body includes a skin layer joint plane at one location at a central portion in the thickness direction, and the skin layer and other surface come in contact with each other at another location along the central portion in the thickness direction. A skin layer joint plane is arranged on a side closer to the innermost surface than a central plane in the thickness direction of the multilayer body.

Abstract: A wiring board includes a first insulating layer containing a thermosetting resin, a first wiring layer stacked on an upper surface of the first insulating layer, a second insulating layer stacked on the upper surface of the first insulating layer, a second wiring layer stacked on an upper surface of the second insulating layer, and a third insulating layer stacked on the upper surface of the second insulating layer. The second and third insulating layers contain a first photosensitive resin. An outer side surface of the second insulating layer is flush with an outer side surface of the first insulating layer. An outer side surface of the third insulating layer is located inside the outer side surface of the second insulating layer in a plan view. The upper surface of the second insulating layer connecting to the outer side surface thereof is exposed from the third insulating layer.

Abstract: One disclosed embodiment comprises formation of a padless via in a substrate. The padless via includes a hole through a metal layer blanketing the substrate, as well as the underlying substrate. An inner wall of the padless via hole receives a seed layer of a conductive material. Electrolytic differential plating is then performed, resulting in a preferential accumulation of a conductive plating material on the via inner wall, relative to that deposited on a surface of the substrate. In one embodiment, the differential plating is performed by addition of an organic suppressant to a plating bath.

Abstract: A wiring board includes a substrate body provided with a through hole penetrating the substrate body from one surface to another surface; and a through wiring formed in the through hole and including a first metal layer formed on a part of an inner side surface of the through hole at the one surface side, a first wiring layer that covers the first metal layer to fill a part of the through hole at the one surface side, a second metal layer continuously formed on the rest part of the inner side surface of the through hole at the other surface side and on an end portion of the first wiring layer at the other surface side, and a second wiring layer that covers the second metal layer to fill a part of the through hole at the other surface side.

Abstract: Disclosed herein are an interposer board and a method of manufacturing the same. According to a preferred embodiment of the present invention, the interposer substrate may include: a base substrate; a circuit pattern formed on the base substrate; and a through via formed to penetrate through the base substrate and have a height lower than that of the circuit pattern.

Abstract: A multilayer printed wiring board includes a multilayered structure having conductor circuit layers and interlaminar insulative layers, the interlaminar insulative layers including an outermost interlaminar insulative layer, the conductor circuit layers including an outermost conductor circuit layer formed over the outermost interlaminar insulative, a filled-viahole formed in the outermost interlaminar insulative layer and having one or more metal plating fillings and completely closing a hole formed through the outermost interlaminar insulative layer such that the metal plating of the filled-viahole extends out of the hole and forms a substantially flat surface, and solder bumps including a first solder bump formed on the substantially flat surface of the filled-viahole and a second solder bump formed on a surface portion in the outermost conductor circuit layer.

Abstract: An interconnection element is disclosed that includes a plurality of drawn metal conductors, a dielectric layer, and opposed surfaces having a plurality of wettable contacts thereon. The conductors may include grains having lengths oriented in a direction between the first and second ends of the conductors. A dielectric layer for insulating the conductors may have first and second opposed surfaces and a thickness less than 1 millimeter between the first and second surface. One or more conductors may be configured to carry a signal to or from a microelectronic element. First and second wettable contacts may be used to bond the interconnection element to at least one of a microelectronic element and a circuit panel. The wettable contacts may match a spatial distribution of element contacts at a face of a microelectronic element or of circuit contacts exposed at a face of component other than the microelectronic element.

Abstract: A wiring board includes multiple insulating layers including first, second, third, fourth and fifth insulation layers laminated in the order of the first, second, third, fourth and fifth insulation layers. The first insulation layer has a first conductor including plating, the second insulation layer has a second conductor including plating, the third insulation layer has a third conductor including conductive paste, the fourth insulation layer has a fourth conductor including plating, the fifth insulation layer has a fifth conductor including plating, and the first conductor, the second conductor, the third conductor, the fourth conductor and the fifth conductor are formed along the same axis and are electrically continuous with each other.

Abstract: A circuit substrate includes a resin layer; and an inorganic insulating layer including a groove portion penetrating the inorganic insulating layer in a thickness direction thereof. A part of the resin layer is in the groove portion.

Abstract: A cover insulating layer is formed on a base insulating layer. One of write wiring traces includes first to third lines, and the other write wiring trace includes fourth to sixth lines. The one and other write wiring traces constitute a signal line pair, the second and fifth lines are arranged on an upper surface of the cover insulating layer, and the third and sixth lines are arranged on an upper surface of the base insulating layer. At least parts of the second and fifth lines are respectively opposed to the sixth and third lines with the cover insulating layer sandwiched therebetween. The second and third lines are electrically connected to the first line, and the fifth and sixth lines are electrically connected to the fourth line. The fourth line is electrically connected to at least one of the fifth and sixth lines through a jumper wiring on a lower surface of the base insulating layer.

Abstract: An electronic module with EMI protection is disclosed. The electronic module comprises a component (1) with contact terminals (2) and conducting lines (4) in a first wiring layer (3). There is also a dielectric (5) between the component (1) and the first wiring layer (3) such that the component (1) is embedded in the dielectric (5). Contact elements (6) provide electrical connection between at least some of the contact terminals (2) and at least some of the conducting lines (4). The electronic module also comprises a second wiring layer (7) inside the dielectric (5). The second wiring layer (7) comprises a conducting pattern (8) that is at least partly located between the component (1) and the first wiring layer (3) and provides EMI protection between the component (1) and the conducting lines (4).

Abstract: A printed circuit board of the present invention includes a base body, a through-hole that penetrates through the base body in the thickness direction, and a through-hole conductor that covers an inner wall of the through-hole. The base body has a fiber layer including a plurality of glass fibers and a resin that covers the plurality of glass fibers. The glass fibers have a groove-shaped concavity on a surface exposed to the inner wall of the through-hole. The concavity is filled with a part of the through-hole conductor.

Abstract: A thin package structure with enhanced strength includes a support carrier plate and a thin circuit board. The thin circuit board is formed on the support carrier plate and includes a first circuit layer, a dielectric layer and a second circuit layer. The first circuit layer includes the first circuit patterns and the first connection pads. The dielectric layer covers the first circuit layer. The second circuit layer is formed on or embedded in an upper surface of the dielectric layer and includes the second circuit patterns and the second connection pads. Connection plugs are formed in the dielectric layer to connect the first and second connection pads. The support carrier plate provides mechanical strength to avoid warping or deforming. It is feasible to direct test the package structure without disassembling so as to improve the convenience in testing.

Abstract: Disclosed herein are a glass core substrate and a method for manufacturing the same. According to an embodiment of the present invention, there is provided the glass core substrate including: a glass core laminate including a glass layer and insulating layers which are stacked on upper and lower portions of the glass layer; a through hole formed by penetrating through the glass core laminate and provided with at least one crack which is formed at a penetrating inner wall by penetrating into the glass layer; and a conductive material filled in the through hole and the crack. Further, the method for manufacturing a glass core substrate is provided.

Abstract: A semiconductor package includes a package substrate including a first wiring embedded in the package substrate, a second wiring embedded in the package substrate, the second wiring electrically insulated from the first wiring, and a capacitor embedded in the package substrate, the capacitor including a first electrode electrically connected to the first wiring and a second electrode electrically connected to the second wiring. At least a first semiconductor chip is disposed on the package substrate. A plurality of connection terminals are disposed between the package substrate and the first semiconductor chip and contact the package substrate, and form at least a first group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the first wiring, and at least a second group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the second wiring.

Abstract: A packaging substrate having an embedded through-via interposer is provided, including an encapsulant layer, a through-via interposer embedded in the encapsulant layer and having a plurality of conductive through-vias therein, a redistribution layer embedded in the encapsulant layer and formed on the through-via interposer so as to electrically connect with first end surfaces of the conductive through-vias, and a built-up structure formed on the encapsulant layer and the through-via interposer for electrically connecting second end surfaces of the conductive through-vias.

Abstract: Disclosed herein is a printed circuit board having electronic components embedded therein. The printed circuit board having electronic components embedded therein includes: a metal core layer connected to a ground terminal of an external power supply to be grounded and having a cavity or a groove part formed thereon; an electronic component accommodated in the cavity and having a plurality of terminals, a ground terminal included in the plurality of terminals being connected to the metal core layer; an internal insulating layer stacked on both sides of the metal core layer; and circuit patterns formed on an external surface of the internal insulating layer.

Abstract: A method of manufacturing a wiring substrate that has a wiring including a through glass via and is formed of a glass substrate includes forming an alteration layer that penetrates the wiring substrate and is patterned, forming the wiring on a front surface of the wiring substrate in which the alteration layer has been formed, and filling an electrode material in a hole formed by removing the alteration layer, thereby forming the through glass via that connects the wiring on the front surface of the wiring substrate and the wiring on a back surface side thereof.

Abstract: A substrate includes a first wiring substrate, a second wiring substrate, and an adhesive sheet. The first wiring substrate includes a number of first connecting pads and a first penetrating room. The second wiring substrate includes a number of second connecting pads. The adhesive sheet includes a number of through holes and a second penetrating room. The through holes are filled with a conducting material. The adhesive sheet and the first wiring substrate are orderly pressed on the second wiring substrate. The conducting material is connected to the first connecting pads and the second connecting pads. The first penetrating room of the first wiring substrate and the second penetrating room of the adhesive sheet cooperatively form a receiving recess.

Abstract: A power distribution network comprises an interposer and a package substrate, each of which has a major upper surface and a major lower surface substantially parallel to the upper surface. A single copper island is formed on the lower surface of the interposer opposite and substantially co-extensive with a single copper island formed on the upper surface of the package substrate. A plurality of leads extend from the copper island on the lower surface of the interposer, each lead coupling to a different silicon through via that extends through the interposer to the upper surface of the interposer. This structure has significant improvements in performance and cost over prior art structures.

Abstract: An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized.

Abstract: A wiring board includes a first via hole in a first insulating layer to expose a first wiring layer. A first via in the first via hole includes an end surface. A second wiring layer is arranged on the first insulating layer and the end surface of the first via. A second insulating layer covers the second wiring layer. A second via hole in the second insulating layer exposes the second wiring layer. A second via in the second via hole is arranged above the first via through the second wiring layer. The outer surface of the first insulating layer is lower in surface roughness than an inner surface of the first via hole.

Abstract: In at least one embodiment, a circuit board assembly that includes a printed circuit board is provided. The printed circuit board includes a top surface and a bottom surface for supporting at least one through-hole electrical component. The printed circuit board defines at least one component hole extending from the top surface to the bottom surface for receiving the at least one through-hole electrical component. The at least one component hole includes a first section having a first diameter and a second section having a second diameter. The first diameter is different from the second diameter. Each of the first and the second sections are configured to receive solder paste for forming a solder joint with the at least one through-hole electrical component.

Abstract: A PCB includes at least three single layer circuit boards laminated together. The single layer circuit boards include two outer circuit boards and at least one inner circuit board. Each single layer circuit board includes a dielectric layer and a conductive layer on a surface of the dielectric layer. The dielectric layer is selected from a material of thermoplastic resin. Each single layer circuit board defines at least one blind hole passing through the dielectric layer and is ended at the conductive layer. Each blind hole is filled with a filler material electrically connected to the conductive layer. The conductive layer of the at least one inner circuit board forms a first conductive circuit pattern, and the conductive layers of the outer circuit boards each form a second conductive circuit pattern. The second conductive circuit pattern is electrically connected to the first conductive circuit pattern by the filler material.

Abstract: A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.

Abstract: The present invention relates to a device with portions of the device on plural substrate surfaces. The device includes a low resistivity substrate having first and second surfaces with a first electrically-conductive device component disposed over a first surface. An intermediate electrically-insulating layer may be disposed between the electrically-conductive component and the low resistivity substrate. A second electrically-conductive component is disposed over the second surface of the low resistivity substrate. A cavity formed in the low resistivity substrate is at least partially filled with a high resistivity material. One or more electrically-conducting pathways are formed in the high resistivity material electrically connecting the first electrically conductive component and the second electrically-conductive component to form a device. Exemplary devices include inductors, capacitors, antennas and active or passive devices incorporating such devices.