Abstract: A method of manufacturing a multilayer printed wiring board includes forming a first interlaminar resin insulating layer, a first conductor circuit on the first interlaminar resin insulating layer, a second interlaminar resin insulating layer, opening portions in the second interlaminar resin insulating layer to expose a face of the first conductor circuit, an electroless plating film on the second interlaminar resin insulating layer and the exposed face, and a plating resist on the electroless plating film. The method further includes substituting the electroless plating film with a thin film conductor layer, having a lower ion tendency than the electroless plating film, and a metal of the exposed face, forming an electroplating film including the metal on a portion of the electroless plating film and the thin film conductor layer, stripping the plating resist, and removing the electroless plating film exposed by the stripping.

Abstract: A method includes forming a first substrate by (a) applying an electrodepositable dielectric coating onto a conductive surface; (b) curing the dielectric coating; (c) depositing an adhesion layer and a seed layer onto the dielectric coating; (d) applying a layer of a first removable material to the seed layer; (e) forming openings in the first removable material to expose areas of the seed layer; (f) electroplating a first conductive material to the exposed areas of the seed layer; (g) applying a layer of a second removable material; (h) forming openings in the second removable material to expose areas of the first conductive material; (i) plating a second conductive material to the exposed areas of the first conductive material; (j) removing the first and second removable materials; (k) removing unplated portions of the seed layer; repeating steps (a) through (k) to form a second substrate; and laminating the first and second substrates together with a layer of dielectric material between the first and secon

Abstract: The manufacture of a submillimetric grid includes the production of a mask having submillimetric openings, referred to as a network mask, on the main face, from a solution of colloidal nanoparticles with a given glass transition temperature Tg, the drying of the masking layer at a temperature below the Tg; the formation of the electroconductive grid from the network mask including in this order: deposition of at least one electroconductive material, referred to as grid material, having an electricity resistivity of less than 10?5 ohm.cm; removal of the masking layer, revealing the mother grid; optional deposition, by electrodeposition, of an electroconductive material, referred to as overgrid material, the surface subjacent to the mother grid then being dielectric; a detachment, of the mother grid or the overgrid, of a thickness of at least 500 nm. The invention also relates to the detached grid.

Abstract: Approaches for formation of a circuit via which electrically connects a first thin film metallization layer a second thin film metallization layer are described. Via formation involves the use of an anodization barrier and/or supplemental pad disposed in a via connection region prior to anodization of the first metallization layer. The material used to form the barrier is substantially impermeable to the anodization solution during anodization, and disrupts the formation of oxide between the electrically conducting layer and the barrier. The supplemental pad is non-anodizable, and is covered by the barrier to substantially prevent current flow through the pad during anodization. Following anodization, the barrier is removed. If the supplemental pad is sufficiently conductive, it can be left on the first metallization layer after removal of the barrier.

Abstract: A wiring board includes an insulation layer containing a resin and a silica-type filler and having a roughened surface, and a conductive layer formed on the roughened surface of the insulation layer and having a first conductive portion and a second conductive portion positioned adjacent to the first conductive portion. The roughened surface of the insulation layer has a roughness under the first conductive portion, a roughness under the second conductive portion, and a roughness between the first conductive portion and the second conductive portion, and the roughness between the first conductive portion and the second conductive portion is set less than at least one of the roughness under the first conductive portion and the roughness under the second conductive portion.

Abstract: A method of manufacturing a printed circuit board is disclosed. A method of manufacturing a printed circuit board, which includes: forming at least one interlayer connector on a first carrier, stacking at least one insulation layer on the first carrier such that the interlayer connector is exposed, removing the first carrier, and forming at least one circuit pattern on the insulation layer such that the circuit pattern is electrically coupled with the interlayer connector, can be used to increase the density of circuit patterns, as the method can provide electrical connection between circuit patterns and vias without using lands.

Abstract: A plasma treatment is performed on the surface of one side of a polyimide film made of a resin. When wettability is imparted to the surface of the one side of the polyimide film, the plasma treatment is performed on the surface of the one side of the polyimide film to which sprayed water adhere.

Abstract: A method and composition for electroplating Cu onto a substrate in the manufacture of a microelectronic device involving and electrolytic solution containing a source of Cu ions and a substituted pyridyl polymer compound for leveling.

Abstract: To improve thermal resistance of a double-sided wiring glass substrate. A through-hole is filled with a copper post composed of metallic copper to thereby electrically connect the front and rear surfaces of the double-sided wiring glass substrate. The filling with the copper post is performed by first sealing, with copper, one opening part of the through-hole using an electrolytic plating method and then further plating copper from the one sealed opening part to the other opening part. As a result, the front and rear surfaces of the double-sided wiring glass substrate can be surely electrically connected as well as high thermal resistance of the whole double-sided wiring glass substrate can be secured.

Abstract: To improve thermal resistance of a double-sided wiring glass substrate. A through-hole is filled with a copper film layer composed of metallic copper for electrically connecting the front and rear surfaces of the double-sided wiring glass substrate. The copper film layer is formed by first forming an electroless plating copper layer and then forming an electrolytic plating copper layer on a sidewall of the through-hole. As a result, the front and rear surfaces of the double-sided wiring glass substrate can be surely electrically connected as well as high thermal resistance of the whole double-sided wiring glass substrate can be secured.

Abstract: The objective of present invention is to provide an electroplating solution capable of forming the upper face of a via-hole and the upper face of a conductor circuit in the same layer in approximately the same plane at the time of manufacturing a multilayer printed circuit board. The electroplating solution of the present invention is characterized by containing 50 to 300 g/L of copper sulfate, 30 to 200 g/L of sulfuric acid, 25 to 90 mg/L of chlorine ion, and 1 to 1000 mg/L of an additive comprising at least a levelling agent and a brightener.

Abstract: A method of fabricating a multi-trace via substrate is disclosed. A substrate at least having a first surface and a hole is provided, wherein the hole has a hole wall. A first conductive layer is formed on the entire surface of the substrate and the hole wall. A photoresist layer applied over the entire surface of the first conductive layer is selectively patterned to define a plurality of laterally separated regions on the first conductive layer. A patterned photoresist layer is used as a mask and a second conductive layer substantially thicker than the first conductive layer is electroplated on the laterally separated regions. The patterned photoresist layer is removed. The portion of the first conductive layer not covered by the second conductive layer is substantially removed to form a plurality of laterally separated traces extended on the first surface and through the hole.

Abstract: A through-hole type laminated circuit board is given with high reliability of electrical connection using copper foil and conductive paste containing low melting point metal without generating harmful void and crack at boundary between the copper foil and conductive paste metal. The laminated circuit board is made by laminating a multiple number of resin boards with roughening treated copper foils at least on their one surface sides with roughening projection deposition of less than 150 mg/dm2 to make surface roughness Rz of 0.3 to 10 ?m and height of the projection to be 0.3 to 10 ?m. Surface roughness of the original foil is 0.1 to 5 ?m and the amount of copper metal atoms of roughening treated layer is set at 4 times or less than the amount of diffusible conductive paste metal atoms containing low melting point metal into the roughening treated layer on the foil surface.

Abstract: A method for manufacturing a wiring structure of a wiring board is provided. In the method, a substrate including an insulation layer and a film disposed on the insulation layer is provided. Next, a barrier layer completely covering the film is formed. Next, an intaglio pattern partially exposing the insulation layer is formed on an outer surface of the barrier layer. Next, an activated layer is formed on the outer surface and in the intaglio pattern. Then, the activated layer on the outer surface is removed, and the activated layer in the intaglio pattern is remained. After the activated layer on the outer surface is removed, a conductive material is formed in the intaglio pattern by using a chemical deposition method. After forming the conductive material, the barrier layer and the film are removed.

Abstract: The present invention is a method of manufacturing miniaturized organic laminate substrate PCB, semiconductors, semiconductor wafers and semiconductor devices that have a 50% reduction in physical dimensions with respect to prior art existing organic laminate substrate PCB, semiconductors, semiconductor wafers and semiconductor devices. The base planar substrate has a vapor deposited 0.02 mil thick copper cladding thereon its first planar surface that has been affixed atop a hydrophillic layer, and an adhesive layer on its second planar surface. The copper cladding has sufficient peel strength and a low enough etch factor so as to allow 10 micron (or smaller) electrical trace pathways to be formed thereon when the steps of a specifically designed manufacturing methodology are followed.

Abstract: A method and apparatus for establishing more uniform deposition across one or more faces of a workpiece in an electroplating process. The apparatus employs eductors in conjunction with a flow dampener member and other measures to provide a more uniform current distribution and a more uniform metal deposit distribution as reflected in a coefficient of variability that is lower than conventional processes.

Abstract: Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.

Abstract: A wiring circuit board that suppresses the softening phenomenon of circuit interconnect lines with time and that maintains a high tensile strength over an extended period of time, and a method of manufacturing the same are provided. The circuit interconnect lines formed on an insulation layer for the wiring circuit board are made of a metal coating material having a metal composed principally of copper and containing 800 to 3000 ppm of bismuth.

Abstract: Disclosed is a method for manufacturing an electroconductive material-filled throughhole substrate that is free from any void part in the electroconductive material filled into the throughholes. The method comprises forming an electroconductive base layer on one side of a core substrate having throughholes, and precipitating and growing an electroconductive material from one direction within the throughholes by electroplating using the electroconductive base layer as a seed layer to fill the electroconductive material into the throughholes without forming any void part and thus to manufacture an electroconductive material-filled throughhole substrate.

Abstract: A plating apparatus for use in forming a plated film in trenches, via holes, or resist openings that are defined in a surface of a semiconductor wafer, and forming bumps to be electrically connected to electrodes of a package, on a surface of a semiconductor wafer. The plating apparatus has a plating tank for holding a plating solution, a holder for holding a workpiece and bringing a surface to be plated of the workpiece into contact with the plating solution in the plating tank, and a ring-shaped nozzle pipe disposed in the plating tank and having a plurality of plating solution injection nozzles for injecting the plating solution to the surface to be plated of the workpiece held by the holder to supply the plating solution into the plating tank.

Abstract: A printed circuit board according to an aspect of the invention may include: a board portion having an electrode portion provided on a surface thereof; a solder resist layer provided on the surface of the board portion and having an opening therein to expose the electrode portion to the outside; and a bump layer having the same diameter as the opening and providing an electrical connection with an external chip component.

Abstract: For use for a circuit board where a through hole and a blind via hole co-exist, an electrolytic copper plating bath in which the covering power for the through hole and the plugging performance for the blind via hole are sufficient, and an electroplating method that uses the electrolytic copper plating bath, are disclosed. The electrolytic copper plating bath is mainly composed of a water-soluble copper salt, sulfuric acid and chloride ions. A polyamide polyamine, obtained on processing by heating of an epichlorohydrin modified product of a polycondensation product of diethylene triamine, adipic acid and ?-caprolactam, is contained in the bath as a leveler.

Abstract: A package substrate and a manufacturing method thereof are provided, including: forming a solder mask on a package substrate body having a plurality of conductive pads; forming a plurality of first-step openings in the solder mask by exposure and development; forming a plurality of second-step openings in the solder mask by a laser-based or plasma-based drilling process; and removing a solder mask foot from the bottom of each of the first-step openings so as to expose large surface areas of the conductive pads. Hence, the contact area between a conductive element and a corresponding one of the conductive pads is large enough to enhance bonding and electrical connection therebetween.

Abstract: A circuit board, a chip package structure and a fabrication method of the circuit board are provided. By applying the fabrication method, a plurality of conductive channels can be formed in a single through hole of the circuit substrate. Unlike the conductive channels respectively formed in the through holes according to the related art, the conductive channels of the proposed circuit board can be formed in a single through hole. As such, it is conducive to the expansion of available layout area of the circuit board, the increase in layout flexibility, and the improvement of layout density of the circuit board.

Abstract: A printed wiring board is manufactured by a method in which an opening is formed in a substrate, and a seed layer for electrolytic plating is formed on an inner wall of the opening and a surface of the substrate. The substrate with the seed layer is placed in an electrolytic plating solution, and an insulative body is placed in the electrolytic plating solution. The substrate and the insulative body are moved relative to each other to form an electrolytic plated film on the substrate and fill the opening with the electrolytic plated film. A conductive circuit is formed on the substrate. The electrolytic plating solution includes copper sulfate, sulfuric acid, and iron ions.

Abstract: Provided are a flex-rigid wiring board in which resin that is easily affected by chemicals can be protected reliably without any increase in the number of manufacturing process steps, and a method for manufacturing the flex-rigid wiring board. The flex-rigid wiring board consists of a flexible section (A) and a rigid section (B). The flexible section (A) includes a base film (24) which is an insulating layer and a sheet of copper foil (26) which is a conductor layer. The rigid section (B) is provided integrally with the flexible section (A) and includes circuit patterns (28, 29). One surface of the base film (24) of the flexible section (A) is entirely covered with the sheet of copper foil (26). The sheet of copper foil (26) is removed by etching during an intermediate process step. At a boundary of the flexible section (A) and the rigid section (B), a portion extending from the removed sheet of copper foil (26) located into the rigid section (B).

Abstract: A plurality of wiring traces and a plurality of lead wires for plating are formed on a base insulating layer. Each wiring trace and each lead wire for plating are integrally formed with each other. An electrode pad is provided at an end of each wiring trace, and the lead wire for plating is provided to extend from each electrode pad toward the opposite side to the wiring trace. A width of each lead wire for plating is set larger than a width of each wiring trace.

Abstract: A manufacturing process of an embedded type flexible or rigid printed circuit board includes multiple steps. First, a layer of dry film is applied to a layer of copper foil. Then a circuit pattern is formed on the copper foil through photolithography processes. An etching stop layer is electroplated on the copper foil according to the circuit pattern. The etching stop layer is then electroplated with copper. The copper foil is softened by a high temperature process after removing the dry film. Then the layer of the copper foil is etched after coating with an organic layer and the organic layer is solidified.

Abstract: An aqueous acidic copper electroplating composition containing an improved additive system for use at elevated temperatures. The improved additive system comprises (a) a suppressor comprising at least one high molecular weight polymer; (b) a brightener comprising at least one divalent sulfur compound; and (c) a leveler comprising a heterocyclic nitrogen compound. The improved electroplating composition is usable for plating through holes in printed circuit boards.

Abstract: The method for manufacturing an electronic part includes a step of forming an opening hole onto an insulating member sandwiched between a conductor film and a lower conductor layer, from the conductor film, a step of making a surface of the lower conductor layer adhering the insulating member as bottom of the opening hole, and making a metal plating as a conductor portion grow in the opening hole from the lower conductor layer. In the method, after metal plating has reached the conductor film, the metal plating is grown on the conductor film and the conductor portion as electrode, to thereby form a thickness enough to form an upper conductive layer.

Abstract: A device-incorporated substrate and a method of manufacturing a device-incorporated substrate, as well as a printed circuit board and a method of manufacturing a printed circuit board in which a fine-pitch conductor pattern can be formed on an insulating layer with high precision while securing the dimensional stability of the conductor pattern, are provided. A transfer sheet (61) has a structure that includes two layers, a metal base material (62) and a dissolvee metal layer (64), and a conductor pattern (55) is formed on the dissolvee metal layer (64) through electroplating. Then, after the transfer sheet (61) on which the conductor pattern (55) is formed is adhered onto an insulating base material (51), the transfer sheet (61) is removed through a step of separating the metal base material (62) from the dissolvee metal layer (64), and a step of selectively dissolving and removing the dissolvee metal layer (64) with respect to the conductor pattern (55).

Abstract: To generate a very uniform copper deposit in particular in blind micro vias (BMVs) and trenches, an aqueous, acid bath for the electrolytic deposition of copper is provided, said bath containing at least one copper ion source, at least one acid ion source, at least one brightener compound and at least one leveler compound, wherein at least one leveler compound is selected from the group comprising synthetically produced non-functionalized peptides and synthetically produced functionalized peptides and synthetically produced functionalized amino acids.

Abstract: A conductor circuit and method of manufacturing a conductor circuit. The method includes forming a continuous conductor pattern on an insulating substrate, and connecting a short-circuit wire at a first position on the continuous conductor pattern such that two or more points on the continuous conductor pattern are short-circuited to each other by the short-circuit wire at the first position. An electrolytic plating film is formed on the continuous conductor pattern while the short-circuit wire is connected to the continuous conductor pattern at the first position, and the short-circuit wire is removed from the first position on the continuous conductor pattern to uncover a first exposed portion of the continuous conductor pattern.

Abstract: A printed circuit board (“PCB”) (100) includes a first routing layer (110), a second routing layer (120) and a via hole structure (150) electrically connecting the two routing layers. The via hole structure (150) includes a connecting hole (158) extending between the first routing layer (110) and the second routing layer (120), an inner conductor (154) positioned in the connecting hole (158), an outer conductor (152) substantially surrounds the inner conductor (154), and an insulating medium (156) positioned between the inner conductor and the outer conductor. The outer conductor (152) is insulated from the inner conductor (154), the outer conductor (152) is configured to connected to the ground, and the inner conductor (154) is configured to transmit signals.

Abstract: [Subject Matter] To provide a method for manufacturing a wiring substrate where rigidity is enhanced in an insulative portion made by oxidizing aluminum. [Solution(s)] Aluminum oxide insulative portion 24 is formed on aluminum plate 20 as shown in FIG. 1(A) through anodic oxidation (FIG. 1(C)). Then, holes (nano-holes) (24h) in aluminum oxide 24 are filled with resin 30 (FIG. 1(E)). Accordingly, the rigidity (strength) of insulative portion 24 will be enhanced and cracking will not occur during heat cycles. Also, the insulation reliability of aluminum oxide will increase, and short circuiting may be prevented at through holes 26 (aluminum portions) separated by aluminum oxide 24.

Abstract: A printed wiring board includes a first insulation layer, a first conductive circuit formed on the first insulation layer, a second insulation layer formed on the first insulation layer and the first conductive circuit and having an opening portion reaching the first conductive circuit, a second conductive circuit formed on the second insulation layer, and a via conductor formed in the opening portion and connecting the first conductive circuit and the second conductive circuit. The via conductor is formed an inner-wall surface of the opening portion and has a seed layer including a nitride compound and/or a carbide compound containing Ti, Zr, Hf, V, Nb, Ta or Si and a plated-metal film formed in the opening portion, and the plated-metal film and the first conductive circuit have at least portions making direct contact.

Abstract: A via hole is formed in a first cladding layer laminated on a wiring board. A conductive material is filled in the via hole so as to form a first conductor portion (a portion of a conductive via) having a mushroom-like shape projecting from a surface of the first cladding layer. Then, a second cladding layer is formed to cover the first conductor portion, the first cladding layer and a core layer, and a via hole is formed in the second cladding layer. A conductive material is filled in the via hole so as to form a second conductor portion (a remaining portion of the conductive via) connected to the first conductor portion.

Abstract: A method of plating, which allows compositions of plating patterns of a plurality of layers to be uniform without any operational complexity, is provided. The area of the plating layer electrodeposited including plating patterns is constant in each of the plurality of layers. Accordingly, a value of plating-current density is easily maintained constant without any special operation. Consequently, the plating patterns in each of the plurality of layers is easily formed to have an uniform composition.

Abstract: An initial pulse current cycle is supplied to at least one through-hole via. The pulse current cycle includes a forward pulse current. The magnitude of the forward pulse current is lower than the magnitude of the reverse pulse current. A corresponding forward and reverse current density is generated across the via causing conductive material to be deposited within the via, thereby reducing the effective aspect ratio of the via. At least one subsequent pulse current cycle is supplied. The magnitudes of the forward and reverse pulse currents of the subsequent pulse current cycle are determined in relation to the reduced effective aspect ratio. A subsequent corresponding forward and reverse current density is generated across the through-hole via causing conductive material to be deposited within the via, thereby further reducing the effective aspect ratio of the via.

Abstract: There is provided a wiring substrate. The wiring substrate includes: an insulating layer; first electrode pads having first exposed surfaces, the first exposed surfaces being exposed from the insulating layer; and second electrode pads having second exposed surfaces, the second exposed surfaces being exposed from the insulating layer. There is a level difference between the first exposed surfaces and the second exposed surfaces.

Abstract: The present invention relates to an embedded substrate having a circuit layer element with an oblique side surface and a method for making the same. The embedded substrate includes a dielectric layer and a circuit layer element. The dielectric layer has an upper surface and an accommodating groove. The circuit layer element is disposed in the accommodating groove. The circuit layer element has an upper surface, a chemical copper layer, a plating copper layer and an oblique side surface. The elevation of the upper surface is equal to or lower than that of the upper surface of the dielectric layer. The chemical copper layer includes palladium (Pd). The plating copper layer is disposed on the chemical copper layer. The oblique side surface is disposed on the upper surface of the circuit layer element, where is close to the wall of the accommodating groove, and extends downward from the upper surface of the circuit layer element to the wall of the accommodating groove.

Abstract: A multi-layered wafer support apparatus is provided for performing an electroplating process on a semiconductor wafer (“wafer”). The multi-layered wafer support apparatus includes a bottom film layer and a top film layer. The bottom film layer includes a wafer placement area and a sacrificial anode surrounding the wafer placement area. The top film layer is defined to be placed over the bottom film layer. The top film layer includes an open region to be positioned over a surface of the wafer to be processed, i.e., electroplated. The top film layer provides a liquid seal between the top film layer and the wafer, about a periphery of the open region. The top film layer further includes first and second electrical circuits that are each defined to electrically contact a peripheral top surface of the wafer at diametrically opposed locations about the wafer.

Abstract: According to the present invention, a circuit board having a further-microfabricated circuit pattern that can be manufactured in further simplified steps is obtained. For such purpose, a mold 10, which has protrusions 11 formed in a pattern corresponding to a circuit pattern, is used to apply a conductive material layer (metal paste) 13 to head portions of the protrusions 11 of the mold 10. The mold is heat- and pressure-welded to the surface of a substrate 20 that is made of a resin film or the like. Accordingly, a pattern comprising the protrusions 11 and the conductive material layer (metal paste) 13 are transferred to the substrate 20. After transfer, the resin substrate (resin molding 30) is immersed in a copper sulfate plating bath for electrolytic plating treatment. Copper ions in the plating bath were deposited inside each recess 31 while the conductive material layer 13 is used as a base material for the formation of a metal wiring 32.

Abstract: A method of preparing printed circuit boards (PCB) or flexible printed circuit boards (FPCB) by direct printing includes: 1) a step of printing a pattern on substrate with a paste composition including conductive particles, polyamic acid as binder and solvent; 2) a step of baking the printed substrate to imidize the polyamic acid; and 3) a step of electro-plating the printed substrate. Printed circuit boards (PCB) or flexible printed circuit boards (FPCB) are produced by applying an addition method of direct printing while to simplify processes, to save time and cost, and to minimize waste.

Abstract: A manufacturing method of a non-etched circuit board is disclosed herein, which employs a metal substrate having a metal barrier layer and an electroplated copper layer to transmit an electrical current to form a circuit layer. A patterned photoresist layer is formed on the electroplated copper layer to define the location of the circuit layer and form circuits or conductive via on the board by electroplating. An electroplated nickel layer or an electroplated gold layer is further formed on the circuit layer for protecting the circuits and improving the fine line capability. During or after the process, the metal substrate, the metal barrier layer, and the electroplated copper layer are removed to enlarge the wiring space, so that a high-density circuit board can be obtained.

Abstract: A method of fabricating a circuit board includes: forming an adhesion auxiliary layer on a surface of an insulating base board; forming an adhesion layer on a surface of the adhesion auxiliary layer, the adhesion layer comprising a polymer compound having a polymerizable group and a functional group capable of interacting with a plating catalyst or a precursor thereof; fixing the adhesion layer to the adhesion auxiliary layer by applying energy to the adhesion layer; applying a plating catalyst or a precursor thereof to the adhesion layer; forming a first metal film by electroless plating on the adhesion layer; and performing electroplating by using the first metal film; and the method further includes partly removing, by irradiating a laser beam, an area corresponding to a non-circuit portion in any of the adhesion auxiliary layer, the adhesion layer, or the first metal film.

Abstract: A plating bath, able to form a resistance layer with a uniform thickness distribution on the roughened surface of a conductive base, including nickel ions and sulfamic acid or its salt as essential components and at least one of phosphoric acid, phosphorous acid, hypophosphorous acid, and salts of the same; a conductive base having a thin resistance layer with a stable resistance, and a resistance circuit board material using the same.

Abstract: On both surfaces of an electric insulating material 1, a surface conductive layer 2A and a back surface conductive layer 2B are formed by transcription. Further, a via hole 5 penetrating through the surface conductive layer 2A and the electric insulating material 1 is provided. After forming a photosensitive plating resist pattern 14, the via hole 5 is filled with a copper plating filler 15, and the surface wiring layer 9A and the back surface wiring layer 9B are formed. Thereafter, the photosensitive plating resist pattern 14 as well as the surface conductive layer 2A and the back surface conductive layer 2B provided under the photosensitive plating resist pattern 14 are removed to fabricate a double-sided wiring board 11.

Abstract: The present invention provides a printed wiring board free from undercuts, which can be formed by an additive method without a dry treatment and a dry treatment apparatus, and a production method thereof. A printed wiring board of the present invention has a conductor circuit free from undercuts which is produced by carrying out additional plating to fill undercuts.

Abstract: A through hole is formed in a circuit board (300) that has fibers (312) dispersed in a polymer matrix. Copper is sputtered within the through hole to form a sufficiently conductive layer for electrolytic plating (308) over the sputtered copper layer (306).