Etching Of Coating Patents (Class 205/223)
  • Patent number: 7066234
    Abstract: A simple, cost-effective stamping or molding in the nanometer range is enabled using a stamping surface or molding face with a surface layer having hollow chambers that have been formed by anodic oxidation.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: June 27, 2006
    Assignee: AlCove Surfaces GmbH
    Inventor: Thomas Sawitowski
  • Patent number: 7048841
    Abstract: Contact assemblies, electroplating machines with contact assemblies, and methods for making contact assemblies that are used in the fabrication of microelectronic workpieces. The contact assemblies can be wet-contact assemblies or dry-contact assemblies. A contact assembly for use in an electroplating system can comprise a support member and a contact system coupled to the support member. The support member, for example, can be a ring or another structure that has an inner wall defining an opening configured to allow the workpiece to move through the support member along an access path. In one embodiment, the support member is a conductive ring having a plurality of posts depending from the ring that are spaced apart from one another by gaps. The contact system can be coupled to the posts of the support member. The contact system can have a plurality of contact members projecting inwardly into the opening relative to the support member and transversely with respect to the access path.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: May 23, 2006
    Assignee: Semitool, Inc.
    Inventors: Robert W. Batz, Jr., John M. Pedersen, John L. Klocke, LinLin Chen
  • Patent number: 7045039
    Abstract: A method for depositing a multi-layered protective and decorative coating on an article comprising first depositing at least one coating layer on the article by electroplating, removing the electroplated article from the electroplating bath and subjecting it to pulse blow drying to produce a spot-free surface on the electroplated article, and then depositing, by physical vapor deposition, at least one vapor deposited coating layer on the electroplated article. The electroplated layers are selected from copper, nickel and chrome. The physical vapor deposited layers are selected from non-precious refractory metals, non-precious refractory metal alloys, non-precious refractory metal compounds, and non-precious refractory metal alloy compounds.
    Type: Grant
    Filed: June 17, 1999
    Date of Patent: May 16, 2006
    Assignee: Masco Corporation of Indiana
    Inventors: Dennis Foster, Larry M. McHugh, Heinrich Andreas Moebius
  • Patent number: 7029597
    Abstract: A process for selectively etching a surface of an anodized aluminum article. A preferred process includes: providing an aluminum sheet or web including first and second sides having anodized finishes; etching the first side to improve the adhesion capabilities of that side but not etching the second side so that the second side retains its anodized finish. The anodized aluminum may be colored before etching, thus the second side retains its color after etching. In a more preferred embodiment, sodium hydroxide or phosphoric acid is used to etch the anodized aluminum. Optionally, the etching of the second side is prevented by administering gas or liquid over the second side, masking the second side with a protective film, or shielding the second side with a shield. Further, the gas or liquid administered over the second side may be controlled to increase or decrease the rate of etching on the first side.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: April 18, 2006
    Assignee: Lorin Industries, Inc.
    Inventors: Gregory S. Marczak, Rick A. Minner
  • Patent number: 7029567
    Abstract: An edge cleaning system and method is disclosed in which a directed stream of a mild etching solution is supplied to an edge area of a rotating workpiece, including the front surface edge and bevel, while a potential difference between the workpiece and the directed stream is maintained. In one aspect, the present invention provides an edge cleaning system that is disposed in the same processing chamber that is used for deposition or removal processing of the workpiece. In another aspect, the mild etching solution used for edge removal is also used to clean the front surface of the wafer, either simultaneously with or sequentially with the edge removal process.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: April 18, 2006
    Assignee: Asm Nutool, Inc.
    Inventor: Bulent M. Basol
  • Patent number: 7022210
    Abstract: A locally distributed electrode is made by placing a conducting metallic oxide layer and a counter electrode in contact with a noble metal electroplating solution and applying a negative potential to the metallic oxide layer relative to the counter electrode, such that the noble metal is electrodeposited from the solution preferentially at defect sites on a surface of the metallic oxide layer. The noble metal nuclei are selectively electrodeposited at the defect sites to form a locally distributed electrode made up of a dot matrix of metallic islands. For reversible electrochemical mirror (REM) devices, the presence of the noble metal renders mirror metal electrodeposition at the defect sites reversible so that the defects become part of the dot matrix electrode and extraneous deposition of the mirror metal on the conducting metallic oxide is avoided.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: April 4, 2006
    Assignee: Rockwell Scientific Licensing, LLC
    Inventor: D. Morgan Tench
  • Patent number: 7001641
    Abstract: Seed layer treatment to remove impurities in the seed layer that might lead to the formation of voids in interconnect circuit features. In one embodiment, the seed layer is heated in a reducing environment. In another embodiment, the seed layer is washed with a surfactant that is compatible with a surfactant used when forming the remainder of the circuit feature on the seed layer. Yet another embodiment combines both techniques.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: February 21, 2006
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Christopher D. Thomas, Vinay B. Chikarmane
  • Patent number: 6986838
    Abstract: A nanomachined and micromachined electrode (10) is disclosed that is produced by providing a layer of aluminum (11) positioned upon a conductive substrate (12), anodizing the layer of aluminum to produce a layer of aluminum oxide (13) having an array of pores (14), depositing a sacrificial metal (17) within the pores of the aluminum oxide layer, etching the aluminum oxide layer so as to leave an array of sacrificial metal rods (18), depositing a layer of electrode material (19) between the array of sacrificial metal rods, and etching the sacrificial metal rods so that a layer of copper remains having an array of pores (20) where the sacrificial metal rods had existed. The layer of copper is the electrode (10).
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: January 17, 2006
    Assignee: Johnson Research & Development Co., Inc.
    Inventors: Davorin Babic, John M. Baxley, Paul D. Browne
  • Patent number: 6946066
    Abstract: The present invention relates to a method for forming a planar conductive surface on a wafer. In one aspect, the present invention uses a no-contact process with electrochemical deposition, followed by a contact process with electrochemical mechanical deposition.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: September 20, 2005
    Assignee: ASM Nutool, Inc.
    Inventors: Bulent M. Basol, Cyprian E. Uzoh, Homayoun Talieh
  • Patent number: 6936349
    Abstract: A housing made of a magnesium material is colored by a non-painting process. In this process, an anode oxide film is grown on the surface of the housing by subjecting the housing to anodization. The anode oxide film is colored without a paint being applied to the surface of the film.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: August 30, 2005
    Assignee: Fujitsu Limited
    Inventors: Yasuo Naganuma, Masami Tsutsumi
  • Patent number: 6932896
    Abstract: Systems and methods to remove or lessen the size of metal particles that have formed on, and to limit the rate at which metal particles form or grow on, workpiece surface influencing devices used during electrodeposition are presented. According to an exemplary method, the workpiece surface influencing device is occasionally placed in contact with a conditioning substrate coated with an inert material, and the bias applied to the electrodeposition system is reversed. According to another exemplary method, the workpiece surface influencing device is conditioned using mechanical contact members, such as brushes, and conditioning of the workpiece surface influencing device occurs, for example, through physical brushing of the workpiece surface influencing device with the brushes. According to a further exemplary method, the workpiece surface influencing device is rotated in different direction during electrodeposition.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: August 23, 2005
    Assignee: Nutool, Inc.
    Inventors: Bulent M. Basol, Cyprian Uzoh, Homayoun Talieh
  • Patent number: 6887367
    Abstract: The invention relates to a process which is suitable for applying a permanently adhering, stable, dirt and water repellent coating to metallic surfaces, specifically chromium surfaces, specifically sanitary and kitchen fixtures, and also to the components coated in this manner. The process is based on first chemically activating the surface and then coating it by means of a sol.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: May 3, 2005
    Assignees: Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung E.V., FEW Chemicals GmbH
    Inventors: Siegfried Berg, Thomas Bolch, Friedrich Auer
  • Patent number: 6878260
    Abstract: A process for forming an interface (106) between a plated and a non-plated area (102, 104) on the surface of a plastic component (100) is disclosed. First, an anti-plating layer (110) is formed over the surface of the plastic component. Thereafter, a low-power laser beam (10) is used to remove a portion of the anti-plating layer and to form an interface between the plated area and the non-plated area. A seeding layer (120) is formed on the plated area so that the plated area is electrically conductive. Finally, a metallic layer (130) is electrically plated over the seeding layer. The metallic layer connects with the anti-plating layer via the interface. The cost of producing the anti-plating layer is low. Moreover, since the laser etching operation is able to produce a high-quality interface boundary between the plated and the non-plated area, yield of the process is improved.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: April 12, 2005
    Assignee: High Tech Computer, Corp.
    Inventors: Che-Hung Huang, Steven Hsu
  • Patent number: 6866764
    Abstract: An inexpensive process for depositing an electrically conductive material on selected surfaces of a dielectric substrate may be advantageously employed in the manufacture of printed wiring boards having high quality, high density, fine-line circuitry, thereby allowing miniaturization of electronic components and/or increased interconnect capacity. The process may also be used for providing conductive pathways between opposite sides of a dielectric substrate and in decorative metallization applications.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: March 15, 2005
    Assignee: Michigan Molecular Institute
    Inventors: David A. Dalman, Petar R. Dvornic
  • Patent number: 6837979
    Abstract: The present invention provides a method and apparatus for plating a conductive material to a substrate and also modifying the physical properties of a conductive film while the substrate is being plated. The present invention further provides a method and apparatus that plates a conductive material on a workpiece surface in a “proximity” plating manner while a pad type material or other fixed feature is making contact with the workpiece surface in a “cold worked” manner. In this manner, energy stored in the cold worked regions of the plated layer is used to accelerate and enhance micro-structural recovery and growth. Thus, large grain size is obtained in the plated material at a lower annealing temperature and a shorter annealing time.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: January 4, 2005
    Assignee: ASM-Nutool Inc.
    Inventors: Cyprian Emeka Uzoh, Homayoun Talieh
  • Publication number: 20040256359
    Abstract: A method of preparing high capacity hydrous ruthenium oxide micro-ultracapacitors. A laser direct-write process deposits a film of hydrous ruthenium oxide in sulfuric acid under ambient temperature and atmospheric conditions. A dual laser process combining infrared and ultraviolet light is used for fabricating a complete wet electrochemical cell in a single processing step. Ultraviolet laser micromachining is used to tailor the shape and size of the deposited material into planar electrodes. The micro-ultracapacitors have improved size, weight, and cost efficiency and exhibit high specific power and high specific energy.
    Type: Application
    Filed: June 9, 2004
    Publication date: December 23, 2004
    Inventors: Craig B. Arnold, Alberto Pique
  • Patent number: 6833063
    Abstract: The present invention provides an edge cleaning system and method in which a directed stream of a mild etching solution is supplied to an edge area of a rotating workpiece, including the front surface edge and bevel, while a potential difference between the workpiece and the directed stream is maintained. In one aspect, the present invention provides an edge cleaning system that is disposed in the same processing chamber that is used for deposition or removal processing of the workpiece. In another aspect, the mild etching solution used for edge removal is also used to clean the front surface of the wafer, either simultaneously with or sequentially with the edge removal process.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: December 21, 2004
    Assignee: Nutool, Inc.
    Inventor: Bulent M. Basol
  • Publication number: 20040251142
    Abstract: Disclosed methods reduce the discontinuities that between individual layers of a structure that is formed at least in part using electrochemical fabrication techniques. Discontinuities may exist between layers of a structure as a result of up-facing or down-facing regions defined in data descriptive of the structure or they may exist as a result of building limitations, e.g., those that result in non-parallel orientation between a building axis and sidewall surfaces of layers. Methods for reducing discontinuities may be applied to all regions or only to selected regions of the structure. Methods may be tailored to improve the accuracy between an original design of the structure and the structure as fabricated or they may simply be used to smooth the discontinuities between layers. Methods may include deposition operations that selectively favor filling of the discontinuities and/or etching operations that selectively favor removal of material from protrusions that define discontinuities.
    Type: Application
    Filed: April 21, 2004
    Publication date: December 16, 2004
    Applicant: Microfabrica Inc.
    Inventors: Adam L. Cohen, Michael S. Lockard, Dennis Smalley
  • Publication number: 20040245110
    Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.
    Type: Application
    Filed: July 7, 2004
    Publication date: December 9, 2004
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yoshiyuki Tonami, Yoshihiro Koshido
  • Publication number: 20040238370
    Abstract: A method of manufacturing a printed circuit board is disclosed. A seed layer is removed while etching of a circuit pattern is prevented. In a printed circuit board manufacturing process according to a semi-additive method, a seed layer is formed by electroless copper plating. Using a resist pattern, a circuit pattern is formed by electrolytic copper plating. After the formation of the circuit pattern, the exposed regions of seed layer are subjected to etching. According to the invention, an etching liquid at a temperature of about 15° C. or less is used. As a temperature of the etching liquid is lowered, a potential difference between the seed layer and the circuit pattern increases. Due to the increase in potential difference, the seed layer becomes more susceptible to being etched, while the circuit pattern becomes less susceptible to being etched.
    Type: Application
    Filed: May 7, 2004
    Publication date: December 2, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ryoichi Watanabe, Tatsuji Yamada, Shogo Mizumoto, Fumio Kumokawa
  • Publication number: 20040231794
    Abstract: A substrate processing apparatus (10) has a substrate holder (12) for detachably holding a substrate (W) so that a surface, to be processed, of the substrate faces downward, and a sealing ring (18) for sealing a peripheral portion of the surface, to be processed, of the substrate (W) held by the substrate holder (12). The substrate processing apparatus (10) also has a plurality of ejection nozzles (40) disposed below the substrate holder (12) for ejecting a treatment solution toward the surface, to be processed, of the substrate (W) held by the substrate holder (12), and a mechanism for rotating and vertically moving the substrate holder (12) and the ejection nozzles (40) relative to each other.
    Type: Application
    Filed: May 18, 2004
    Publication date: November 25, 2004
    Inventors: Akihisa Hongo, Xinming Wang
  • Patent number: 6808617
    Abstract: A polishing method and polishing apparatus able to easily flatten an initial unevenness with an excellent efficiency of removal of excess copper film and suppress damage to a lower interlayer insulation film, and a plating method and plating apparatus able to deposit a flat copper film. The polishing method comprises the steps of measuring thickness equivalent data of a film on a wafer, making a cathode member smaller than the surface face a region thereof, interposing an electrolytic solution between the surface and the cathode member, applying a voltage using the cathode member as a cathode and the film an anode, performing electrolytic polishing by electrolytic elution or anodic oxidation and chelation and removal of a chelate film in the same region preferentially from projecting portions of the film until removing the target amount of film obtained from the thickness equivalent data, and repeating steps of moving the cathode member to another region to flattening the regions over the entire surface.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: October 26, 2004
    Assignee: Sony Corporation
    Inventors: Shuzo Sato, Yuji Segawa, Akira Yoshio, Takeshi Nogami
  • Patent number: 6808641
    Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: October 26, 2004
    Assignee: Murata Manufacturing Co., Ltd
    Inventors: Yoshiyuki Tonami, Yoshihiro Koshido
  • Publication number: 20040206630
    Abstract: The invention relates to a method for producing a textured metal strip. In order to be able to implement a method of this type in a comparatively simple manner and thus cost-effectively, a metal layer (4) is galvanically produced on a textured substrate (1) having electrical conductivity, and the metal layer (4), while producing the textured strip (4a), is removed from the substrate (1).
    Type: Application
    Filed: January 23, 2004
    Publication date: October 21, 2004
    Inventors: Ursus Kruger, Marc de Vogelaere
  • Publication number: 20040200728
    Abstract: A method and apparatus for forming interconnects embedding a metal such as copper (Cu) into recesses for interconnects formed on the surface of a substrate such as a semiconductor substrate. The method includes providing a substrate having fine recesses formed in the surface, subjecting the surface of the substrate to plating in a plating liquid, and subjecting the plated film formed on the surface of the substrate to electrolytic etching in an etching liquid.
    Type: Application
    Filed: May 4, 2004
    Publication date: October 14, 2004
    Inventors: Akihisa Hongo, Naoki Matsuda, Kanji Ohno, Ryoichi Kimizuka
  • Patent number: 6790336
    Abstract: A copper damascene process for a mechanically weak low k dielectric layer is described. Electropolishing is used to etch back the copper. A sacrificial conductive layer beneath the barrier layer assures complete planarization of the copper.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: September 14, 2004
    Assignee: Intel Corporation
    Inventor: Tatyana Andryushchenko
  • Patent number: 6773570
    Abstract: A method and apparatus are described for performing both electroplating of a metal layer and planarization of the layer on a substrate. Electroplating and electroetching of metal (such as copper) are performed in a repeated sequence, followed by chemical-mechanical polishing. An electroplating solution, electroetching solution, and a non-abrasive slurry are dispensed on a polishing pad in the respective process steps. The substrate is held against the pad with a variable force in accordance with the process, so that the spacing between substrate and pad may be less during electroplating than during electroetching.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: August 10, 2004
    Assignee: International Business Machines Corporation
    Inventors: Laertis Economikos, Hariklia Deligianni, John M. Cotte, Henry J. Grabarz, Bomy Chen
  • Publication number: 20040134788
    Abstract: Multilayer structures are electrochemically fabricated via depositions of one or more materials in a plurality of overlaying and adhered layers. Selectivity of deposition is obtained via a multi-cell controllable mask. Alternatively, net selective deposition is obtained via a blanket deposition and a selective removal of material via a multi-cell mask. Individual cells of the mask may contain electrodes comprising depositable material or electrodes capable of receiving etched material from a substrate. Alternatively, individual cells may include passages that allow or inhibit ion flow between a substrate and an external electrode and that include electrodes or other control elements that can be used to selectively allow or inhibit ion flow and thus inhibit significant deposition or etching. Single cell masks having a cell size that is smaller or equal to the desired deposition resolution may also be used to form structures.
    Type: Application
    Filed: October 1, 2003
    Publication date: July 15, 2004
    Applicant: Microfabrica Inc.
    Inventors: Adam L. Cohen, Dennis R. Smalley, Gang Zhang
  • Patent number: 6758956
    Abstract: The invention relates to a method for darkening a superficial layer of a workpiece which contains zinc by anodic oxidation. The workpiece is oxidized in a soaking bath containing an aqueous solution comprised of a hydroxide and of a nitrate. The anodic oxidation may be carried out in an aqueous solution containing NH4NO3 or NaNO3, and having a pH value ranging from 8 to 14, at a dipping bath temperature (T) ranging from 15 to 45° C., and with a current density (i) ranging from 3×10−4 to 0.5 A/cm2. The workpiece is placed in the soaking bath at the beginning of the anodic oxidation after the voltage has already been applied.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: July 6, 2004
    Assignee: Ewald Dorken AG
    Inventors: Thomas Kruse, Peter Meisterjahn
  • Patent number: 6755957
    Abstract: A method of plating for filling via holes, in which each via hole is formed in an insulation layer covering a substrate so as to expose, at its bottom, part of a conductor layer located on the substrate. A copper film is formed on the top surface of the insulation layer covering the substrate, and the side walls and bottoms of the respective via holes. A strike plating of copper is provided on the copper film, and the substrate is immersed in an aqueous solution containing a plating promoter to thereby deposit the plating promoter on the surface of the copper strike. The plating promoter is removed from the copper strike plating located on the top surface insulation layer while leaving the plating promoter on the side walls and bottoms of the respective via holes. The substrate is subsequently electroplated with copper to fill the via holes.
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: June 29, 2004
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kenji Nakamura, Masao Nakazawa
  • Publication number: 20040094427
    Abstract: A method and apparatus are described for performing both electroplating of a metal layer and planarization of the layer on a substrate. Electroplating and electroetching of metal (such as copper) are performed in a repeated sequence, followed by chemical-mechanical polishing. An electroplating solution, electroetching solution, and a non-abrasive slurry are dispensed on a polishing pad in the respective process steps. The substrate is held against the pad with a variable force in accordance with the process, so that the spacing between substrate and pad may be less during electroplating than during electroetching.
    Type: Application
    Filed: November 14, 2002
    Publication date: May 20, 2004
    Applicant: International Business Machines Corporation
    Inventors: Laertis Economikos, Hariklia Deligianni, John M. Cotte, Henry J. Grabarz, Bomy Chen
  • Patent number: 6736952
    Abstract: An electrochemical planarization apparatus for planarizing a metallized surface on a workpiece includes a polishing pad and a platen. The platen is formed of conductive material, is disposed proximate to the polishing pad and is configured to have a negative charge during at least a portion of a planarization process. At least one electrical conductor is positioned within the platen. The electrical conductor has a first end connected to a power source. A workpiece carrier is configured to carry a workpiece and press the workpiece against the polishing pad. The power source applies a positive charge to the workpiece via the electrical conductor so that an electric potential difference between the metallized surface of the workpiece and the platen is created to remove at least a portion of the metallized surface from the workpiece.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: May 18, 2004
    Assignee: SpeedFam-IPEC Corporation
    Inventors: Ismail Emesh, Saket Chadda, Nikolay N. Korovin, Brian L. Mueller
  • Patent number: 6736956
    Abstract: The present invention is directed to a method of etching anode foil in a non-uniform manner which increases the overall capacitance gain of the foil while retaining foil strength. In particular, by using a mask to protect a mesh grid of the foil from further etching, a previously etched foil can be further etched, prior to the widening step. Alternatively, the mask may be used in the initial etch, eliminating the need for the second process. In effect the foil may be etched to a higher degree in select regions, leaving a web of more lightly etched foil defined by the mask to retain strength. According to the present invention, the foil is placed between two masks with a grid of openings which expose the foil in these areas to the etching solution. The exposed area can be as little as 10% of the total foil to as much as 95% of the total foil, preferably 30% to 70% of the total foil area.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: May 18, 2004
    Assignee: Pacesetter, Inc.
    Inventors: Ralph Jason Hemphill, Thomas V. Graham, Thomas Flavian Strange
  • Patent number: 6726826
    Abstract: A method of manufacturing a semiconductor component includes depositing a first electrically conductive layer (675) over a substrate (270), forming a patterned plating mask (673) over the first electrically conductive layer, coupling a first plating electrode (250) to the first electrically conductive layer without puncturing the plating mask, and plating a second electrically conductive layer onto portions of the first electrically conductive layer. A plating tool for the manufacturing method includes an inner weir (220) located within an outer weir (210), an elastic member (230) over a rim (211) of the outer weir, a pressure ring (240) located over the rim of the outer weir and the elastic member, and a plurality of cathode contacts (250, 251, 252, 253) located between the pressure ring and the outer weir. The substrate is positioned between the elastic member and the pressure ring.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: April 27, 2004
    Assignee: Motorola, Inc.
    Inventors: Timothy Lee Johnson, Joseph English, David Austin, George F. Carney, Kandis Mae Knoblauch, Douglas G. Mitchell
  • Patent number: 6726829
    Abstract: Disclosed herewithin is an apparatus for fabricating a stent which involves processing a tubular member whereby no connection points to join the edges of a flat pattern are necessary. The process includes the steps of: a) preparing the surface of a tubular member, b) coating the outside surface of the tubular member with a photo-sensitive resist material, c) placing the tubular member in an apparatus designed to simultaneously rotate the tubular member while passing a specially configured photographic frame negative between a light source and the tubular member, d) exposing the tubular member to a photoresist developer, e) rinsing the excess developer and uncured resist from the exposed tubular member, f) sealing the inner lumen of the tubular member, and g) treating the tubular member with a chemical or electro-chemical process to remove uncovered metal. By modifying the photographic negative, this process can be employed to fabricate a virtually unlimited number of stent designs and configurations.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: April 27, 2004
    Assignee: SciMed Life Systems, Inc.
    Inventor: Thomas Trozera
  • Publication number: 20040055875
    Abstract: The present invention relates to an apparatus having a nanodevice for controlling the flow of charged particles in an electrolyte. Such apparatus comprises an electrolytic bath container divided by a polymeric foil into a first and a second compartment, wherein each compartment comprises an electrode connected to a voltage supply. Further the apparatus comprises at least one asymmetric pore forming a via hole through said foil, wherein said pore provides a narrow opening of a diameter in the range of several nanometers down to about one nanometer on a front side of said foil and a wide opening in the range of several ten nanometers up to several hundred nanometers on a back side of said foil.
    Type: Application
    Filed: September 25, 2002
    Publication date: March 25, 2004
    Inventors: Zuzanna Siwy, Jan Behrends, Niels Fertig, Andrzej Fulinski, Charles R. Martin, Reinhard Neumann, Christina Trautmann, Eugenia T. Molares
  • Publication number: 20040050711
    Abstract: The present invention relates to a method and apparatus for separating out metal copper according to an electroplating of copper using, for example, a solution of copper sulfate to produce copper interconnections on a surface of a substrate. The substrate is brought into contact, at least once, with a processing solution containing at least one of organic substance and sulfur compound which are contained in a plating solution. Thereafter, the substrate is brought into contact with the plating solution to plate the substrate.
    Type: Application
    Filed: September 12, 2003
    Publication date: March 18, 2004
    Inventors: Koji Mishima, Mizuki Nagai, Ryoichi Kimizuka, Tetsuo Matsuda, Hisashi Kaneko
  • Patent number: 6706166
    Abstract: A method for improving an electrodeposited metal film uniformity and preventing metal deposition and peeling of deposited metal from an electrode during an electrodeposition and electropolishing process including providing a first anode electrode assembly and a semiconductor wafer plating surface disposed in an electrolyte bath including a plating metal for deposition onto the semiconductor wafer plating surface; providing at least one additional anode electrode assembly including the plating metal disposed peripheral to the first anode electrode assembly for selectively applying the cathodic electrical potential during an electropolishing process; and, periodically alternating between an electrodeposition process and electropolishing process with respect to the semiconductor wafer plating surface such that the plating metal is preferentially plated onto the at least one additional electrode assembly.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: March 16, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Shih-Wei Chou, Ming-Hsing Tsai
  • Patent number: 6692630
    Abstract: The invention provides a pretreatment process for electroplating aluminum parts or strip, in which the zincating solution is modified to improve the adhesion of the subsequent electroplate to the substrate. The aluminum part or strip, such as an aluminum coin blank or strip for coin blanks, is pretreated with an improved zincate solution which provides hydroxide ions in an amount in the range of 75-175 gpl, zinc ions in an amount in the range of 15-40 gpl, nickel ions in an amount in the range of 2-10 gpl and copper ions in an amount in the range of 1.5-5 gpl. The pretreatment process preferably includes a copper strike applied from a copper cyanide strike bath at a pH in the range of 8.5-11.0, using a current density in the range of 0.1-10 A/dm2. The pretreatment and electroplating steps are preferably conducted by barrel plating, in accordance with another aspect of the invention.
    Type: Grant
    Filed: August 9, 2001
    Date of Patent: February 17, 2004
    Assignee: The Westaim Corporation
    Inventors: Louis Charles Morin, Angie Kathleen Molnar
  • Publication number: 20040020782
    Abstract: In some embodiments, multilayer structures are electrochemically fabricated from at least one structural material (e.g. nickel), at least one sacrificial material (e.g. copper), and at least one sealing material (e.g. solder). In some embodiments, the layered structure is made to have a desired configuration which is at least partially and immediately surrounded by sacrificial material which is in turn surrounded almost entirely by structural material. The surrounding structural material includes openings in the surface through which etchant can attack and remove trapped sacrificial material found within. Sealing material is located near the openings. After removal of the sacrificial material, the box is evacuated or filled with a desired gas or liquid. Thereafter, the sealing material is made to flow, seal the openings, and resolidify. In other embodiments, a post-layer formation lid or other enclosure completing structure is added.
    Type: Application
    Filed: May 7, 2003
    Publication date: February 5, 2004
    Applicant: MEMGen Corporation
    Inventors: Adam L. Cohen, Michael S. Lockard, Dennis R. Smalley, Vacit Arat, Christopher J. Lee
  • Publication number: 20040011653
    Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.
    Type: Application
    Filed: July 18, 2002
    Publication date: January 22, 2004
    Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
  • Publication number: 20040007470
    Abstract: Multi-layer structures are electrochemically fabricated by depositing a first material, selectively etching the first material (e.g. via a mask), depositing a second material to fill in the voids created by the etching, and then planarizing the depositions so as to bound the layer being created and thereafter adding additional layers to previously formed layers. The first and second depositions may be of the blanket or selective type. The repetition of the formation process for forming successive layers may be repeated with or without variations (e.g. variations in: patterns; numbers or existence of or parameters associated with depositions, etchings, and or planarization operations; the order of operations, or the materials deposited). Other embodiments form multi-layer structures using operations that interlace material deposited in association with some layers with material deposited in association with other layers.
    Type: Application
    Filed: May 7, 2003
    Publication date: January 15, 2004
    Applicant: MEMGen Corporation
    Inventor: Dennis R. Smalley
  • Publication number: 20040007468
    Abstract: Multilayer structures are electrochemically fabricated from at least one structural material (e.g. nickel), that is configured to define a desired structure and which may be attached to a substrate, and from at least one sacrificial material (e.g. copper) that surrounds the desired structure. After structure formation, the sacrificial material is removed by a multi-stage etching Operation. In some embodiments sacrificial material to be removed may be located within passages or the like on a substrate or within an add-on component. The multi-stage etching Operations may be separated by intermediate post processing activities, they may be separated by cleaning Operations, or barrier material removal Operations, or the like. Barriers may be fixed in position by contact with structural material or with a substrate or they may be solely fixed in position by sacrificial material and are thus free to be removed after all retaining sacrificial material is etched.
    Type: Application
    Filed: May 7, 2003
    Publication date: January 15, 2004
    Applicant: MEMGen Corporation
    Inventors: Adam L. Cohen, Michael S. Lockard, Dale S. McPherson
  • Patent number: 6673227
    Abstract: The parts are produced by two-component injection molding. Those regions that are to be metallized consist of a first plastic and those regions that are not to be metallized consist of a second plastic. After the entire surface of the parts has been seeded, the seeding is selectively removed with the aid of a solvent in the regions which are not to be metallized. The first plastic is insoluble and the second plastic soluble in the solvent. The selective metallization then takes place by electroless metal deposition and, if appropriate, electrodeposition of metal.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: January 6, 2004
    Assignee: Siemens Production & Logistics Systems AG
    Inventor: Luc Boone
  • Patent number: 6638411
    Abstract: The present invention relates to a method and apparatus for separating out metal copper according to an electroplating of copper using, for example, a solution of copper sulfate to produce copper interconnections on a surface of a substrate. The substrate is brought into contact, at least once, with a processing solution containing at least one of organic substance and sulfur compound which are contained in a plating solution. Thereafter, the substrate is brought into contact with the plating solution to plate the substrate.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: October 28, 2003
    Assignees: Ebara Corporation, Kabushiki Kaisha Toshiba
    Inventors: Koji Mishima, Mizuki Nagai, Ryoichi Kimizuka, Tetsuo Matsuda, Hisashi Kaneko
  • Publication number: 20030164302
    Abstract: The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.
    Type: Application
    Filed: April 4, 2003
    Publication date: September 4, 2003
    Inventors: Cyprian Emeka Uzoh, Homayoun Talieh, Bulent Basol
  • Patent number: 6607650
    Abstract: The object of the present invention is to provide a plating method capable of planarization process of high quality in comparison with the conventional plating method and also provide a plating device and a plating system adopting the plating method of the invention. In the plating method and device, an object 10 to be processed and an electrode plate 20 are dipped in a solution including objective metal ions and a forward current is supplied between the object and the electrode plate to educe a metal on the surface of the object. After forming a plating film on the object excessively, a backward current is supplied between the object 10 and the electrode 20 to uniformly remove at least part of superfluous plating film.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: August 19, 2003
    Assignee: Tokyo Electron Ltd.
    Inventors: Takayuki Niuya, Michihiro Ono, Hideto Goto, Kyungho Park, Yoshinori Marumo, Katsusuke Shimizu
  • Patent number: 6599412
    Abstract: Methods and apparatuses for in-situ cleaning of semiconductor electroplating electrodes to remove plating metal without requiring !the manual removal of the electrodes from the semiconductor plating equipment. The electrode is placed into the plating liquid and, an electrical current having reverse polarity is passed between the electrode and plating liquid. Plating deposits which have accumulated on the electrode are electrochemically dissolved and removed from the electrode.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: July 29, 2003
    Assignee: Semitool, Inc.
    Inventors: Lyndon W. Graham, Thomas L. Ritzdorf, Jeffrey I. Turner
  • Publication number: 20030127336
    Abstract: Various embodiments of the invention present techniques for forming structures (e.g. HARMS-type structures) via an electrochemical extrusion (ELEX™) process. Preferred embodiments perform the extrusion processes via depositions through anodeless conformable contact masks that are initially pressed against substrates that are then progressively pulled away or separated as the depositions thicken. A pattern of deposition may vary over the course of deposition by including more complex relative motion between the mask and the substrate elements. Such complex motion may include rotational components or translational motions having components that are not parallel to an axis of separation. More complex structures may be formed by combining the ELEX™ process with the selective deposition, blanket deposition, planarization, etching, and multi-layer operations of EFAB™.
    Type: Application
    Filed: October 15, 2002
    Publication date: July 10, 2003
    Applicant: MEMGen Corporation
    Inventors: Adam L. Cohen, Gang Zhang, Qui T. Le, Michael S. Lockard, Dennis R. Smalley
  • Patent number: 6589629
    Abstract: A technique for forming functionalized particles, where such particles are readily formed into periodic structures. A layer of particles is formed on a substrate, a first material is deposited over at least a portion of each of the particles, and then a functionalizing agent is attached to the first material. The functionalized particles are then capable of being formed into an ordered structure, by selection of appropriate complementary functionalizing agents on a substrate and/or on other particles and/or on other regions of the same particles.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: July 8, 2003
    Assignee: Lucent Technologies Inc.
    Inventors: Zhenan Bao, Edwin Arthur Chandross, Xiaochen Linda Chen, John A. Rogers, Marcus Weldon