Eroding Workpiece Of Nonuniform Internal Electrical Characteristics Patents (Class 205/656)
  • Patent number: 10920326
    Abstract: Provided are: an etchant composition for titanium or titanium alloy, the etchant composition being used for selectively etching a titanium layer or titanium-containing layer formed on an oxide semiconductor layer; and an etching method using said etchant composition. The etchant composition according to the present invention, which is used for etching a titanium layer or titanium-containing layer on an oxide semiconductor, comprises: a compound containing ammonium ions; hydrogen peroxide; and a basic compound, wherein the etchant composition has a pH of 7-11.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 16, 2021
    Assignee: KANTO KAGAKU KABUSHIKI KAISHA
    Inventors: Ryou Sasaki, Hideki Takahashi, Taiga Yokoyama
  • Patent number: 10712457
    Abstract: The invention relates to microfabrication technology for producing sensing cells, for use, for example, in molecular electronic transducer (MET) based seismometers devices. In some aspects, a method for fabricating a sensing element is provided. The method includes providing a first wafer including a first substrate, a second substrate, and a first insulating layer between therebetween, etching a first fluid throughhole through the first substrate, the first insulating layer, and the second substrate, and coating the first substrate and second substrate with a first and second conductive coating, respectively. The method also includes providing a second wafer including a third substrate, a fourth substrate, and a second insulating layer therebetween, etching a second fluid throughhole through the third substrate, the second insulating layer, and the fourth substrate, and coating the third substrate with a third conductive coating from top and the fourth substrate with a fourth conductive coating from back.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: July 14, 2020
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Hongyu Yu, Hai Huang
  • Patent number: 10354942
    Abstract: A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: July 16, 2019
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
  • Patent number: 9890465
    Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: February 13, 2018
    Assignee: TruTag Technologies, Inc.
    Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Subramanian Tamilmani, George D. Kamian, Jay Ashjaee, Takao Yonehara
  • Patent number: 9847277
    Abstract: A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: December 19, 2017
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
  • Patent number: 9470594
    Abstract: A differential capacitive pressure sensor of an embodiment of the present invention has first and second diaphragms positioned on opposing sides of a single substrate. Each diaphragm of the pressure transducer is configured to be exposed to a transient fluid, with the first and second pressure transducers being arranged with their respective deflection surfaces directed outwardly from each other. The differential capacitive pressure sensor may be configured to output representations of differential and common mode pressure of the transient fluids, where a representation of a common mode is cancelled in generating the representation of the differential pressure. The transient fluids may be the same fluid at different locations within a flow path. The diaphragms may be constructed from a ceramic material to be able to withstand exposure to corrosive or caustic fluids.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: October 18, 2016
    Assignee: Sensata Technologies, Inc.
    Inventors: William D. Cornwell, Mark L. Urban, Marcos A. Nassar
  • Patent number: 9362203
    Abstract: A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad.
    Type: Grant
    Filed: September 27, 2014
    Date of Patent: June 7, 2016
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
  • Patent number: 9254993
    Abstract: The invention relates to a method for connecting a precious metal surface to a polymer, wherein a layer made of 20% to 40% gold and 60% to 80% silver is deposited on a substrate and the silver is subsequently selectively removed in order to produce a nanoporous gold layer. A fluid polymer is applied to the gold layer and cured.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: February 9, 2016
    Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V.
    Inventor: Hermann Oppermann
  • Patent number: 9249523
    Abstract: Forming a porous layer on a silicon substrate is disclosed. Forming the porous layer can include placing a silicon substrate in a first solution and conducting a first current through the silicon substrate. It can further include conducting a second current through the silicon substrate resulting in a porous layer on the silicon substrate.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 2, 2016
    Assignee: SunPower Corporation
    Inventor: Seung Bum Rim
  • Patent number: 9139427
    Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: September 22, 2015
    Assignee: Infineon Technologies AG
    Inventors: Andreas Behrendt, Kai-Alexander Schreiber, Sokratis Sgouridis, Martin Zgaga, Bernhard Winkler
  • Publication number: 20150068918
    Abstract: A wafer contacting device may include: a receiving region configured to receive a wafer; and an elastically deformable carrier disposed in the receiving region and including an electrically conductive surface region.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Applicant: Infineon Technologies AG
    Inventors: Friedrich Kroener, Ingo Muri
  • Patent number: 8900424
    Abstract: An electrode for an electrochemical machining process is provided. The electrode includes an electrically conductive member defining at least one passage and an insulating coating partially covering a side surface of the electrically conductive member. The insulating coating does not cover at least one of first and second exposed sections of the electrically conductive member, where the first and second exposed sections are separated by approximately 180 degrees and extend substantially along a longitudinal axis of the electrically conductive member. The insulating coating also does not cover an exposed front end of the electrically conductive member. An electrochemical machining method is also provided, for forming a non-circular hole in a workpiece using the electrode.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: December 2, 2014
    Assignee: General Electric Company
    Inventors: Bin Wei, Kevin Leon Bruce
  • Patent number: 8778147
    Abstract: An electrochemical machining process for forming a non-circular hole from a substantially circular hole within a workpiece using an electrode. The electrode is made of an electrically conductive material and has insulated areas in which the electrically conductive material is coated with an insulating material, and exposed areas of metal or conductive material. The insulated areas and exposed areas extending in rows substantially along a longitudinal axis of the electrode. The electrode is first positioned in a substantially circular hole. An electric current is then applied to the electrode to electrochemically remove a predetermined amount of material from the substantially circular hole to form a non-circular hole. A variety of different non-circular shapes are achievable using the process.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: July 15, 2014
    Assignee: General Electric Company
    Inventors: Bin Wei, Ronald Scott Bunker
  • Publication number: 20130341205
    Abstract: A method for manufacturing an all solid-state lithium-ion rechargeable battery includes forming a first active material layer on a base, forming a solid electrolyte layer connected to the first active material layer, forming a second active material layer connected to the solid electrolyte layer, and repairing a short-circuit defect produced between the first active material layer and the second active material layer by supplying a repair current between the first active material layer and the second active material layer.
    Type: Application
    Filed: December 26, 2011
    Publication date: December 26, 2013
    Inventors: Mamoru Baba, Rongbin Ye, Masashi Kikuchi
  • Publication number: 20130011656
    Abstract: This invention relates to methods of generating NP gallium nitride (GaN) across large areas (>1 cm2) with controlled pore diameters, pore density, and porosity. Also disclosed are methods of generating novel optoelectronic devices based on porous GaN. Additionally a layer transfer scheme to separate and create free-standing crystalline GaN thin layers is disclosed that enables a new device manufacturing paradigm involving substrate recycling. Other disclosed embodiments of this invention relate to fabrication of GaN based nanocrystals and the use of NP GaN electrodes for electrolysis, water splitting, or photosynthetic process applications.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 10, 2013
    Applicant: YALE UNIVERSITY
    Inventors: Yu Zhang, Qian Sun, Jung Han
  • Publication number: 20100282613
    Abstract: Electrochemical etching tailors topography of a nanocrystalline or amorphous metal or alloy, which may be produced by any method including, by electrochemical deposition. Common etching methods can be used. Topography can be controlled by varying parameters that produce the item or the etching parameters or both. The nanocrystalline article has a surface comprising at least two elements, at least one of which is metal, and one of which is more electrochemically active than the others. The active element has a definite spatial distribution in the workpiece, which bears a predecessor spatial relationship to the specified topography. Etching removes a portion of the active element preferentially, to achieve the specified topography. Control is possible regarding: roughness, color, particularly along a spectrum from silver through grey to black, reflectivity and the presence, distribution and number density of pits and channels, as well as their depth, width, size.
    Type: Application
    Filed: November 15, 2007
    Publication date: November 11, 2010
    Applicant: Massachusetts Institute of Technology
    Inventors: Christopher A. Schuh, Shiyun Ruan
  • Patent number: 7628906
    Abstract: A method of manufacture for optical spectral filters with omnidirectional properties in the visible, near IR, mid IR and/or far IR (infrared) spectral ranges is based on the formation of large arrays of coherently modulated waveguides by electrochemical etching of a semiconductor wafer to form a pore array. Further processing of said porous semiconductor wafer optimizes the filtering properties of such a material. The method of filter manufacturing is large scale compatible and economically favorable. The resulting exemplary non-limiting illustrative filters are stable, do not degrade over time, do not exhibit material delamination problems and offer superior transmittance for use as bandpass, band blocking and narrow-bandpass filters. Such filters are useful for a wide variety of applications including but not limited to spectroscopy, optical communications, astronomy and sensing.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: December 8, 2009
    Assignee: Lake Shore Cryotronics, Inc.
    Inventors: Vladimir Kochergin, Philip Swinehart
  • Publication number: 20090107851
    Abstract: An electrolytic polishing method of a substrate having a barrier film and an interconnect metal layer on a surface to be processed under the presence of an electrolytic solution, including a barrier film electrolytic polishing process which removes the barrier film by applying a voltage between a cathode and an anode, with the surface to be processed serving as the cathode, and causing relative motion between the surface to be processed and a polishing pad which faces and makes contact with the surface to be processed.
    Type: Application
    Filed: October 9, 2008
    Publication date: April 30, 2009
    Inventors: Akira Kodera, Xinming Wang, Itsuki Kobata, Yasushi Toma
  • Patent number: 7494936
    Abstract: A method for electrochemical etching of a semiconductor material using positive potential dissolution (PPD) in solutions that do not contain hydrofluoric acid (HF-free solutions). The method includes immersing an as-cut semiconductor material in an etching solution, and positive biasing at atypically highly positive (anodic) potentials, thereby significantly increasing the value of the anodic current density (measured as A/cm2) of the semiconductor material. The application of positive biasing at atypically highly positive (anodic) potentials, is combined with specifically controlling and directing illumination on the semiconductor material surface contacted and wetted by the etching solution. This is done for a necessary and sufficient period of time to enable a positive synergistic effect on the rate and extent of etching of the semiconductor material therefrom.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: February 24, 2009
    Assignee: Technion Research & Development Foundation Ltd.
    Inventors: Yair Ein-Eli, David Starosvetsky, Joseph Yahalom
  • Publication number: 20090047783
    Abstract: A method of removing unwanted material from a substrate includes providing a system (600) having an etchant solution (610) with an electrode (620) therein and a current supply (630) connected to the electrode, placing the substrate in the solution and connecting it to the current supply, providing an electric current to the electrode, and altering a polarity of the electric current such that the substrate experiences an anodic polarity for a first time period and a cathodic polarity for a shorter time period. An alternative method includes providing a solution delivery system (1100) having a second etchant solution (1110) with an eductor jet (1140) therein and a recirculation pump connected to the eductor jet, placing the substrate in the second solution, and using the eductor jet to spray the substrate with the second solution. If desired, both methods may be used.
    Type: Application
    Filed: August 13, 2007
    Publication date: February 19, 2009
    Inventors: Omar J. Bchir, Houssam Jomaa, Islam A. Salama, Yonggang Li
  • Patent number: 7332068
    Abstract: A metal is provided on a polymeric component and the component is subjected to a removal process such as plasma or liquid etching in the presence of an electric field. The etchant selectively attacks the polymer at the boundary between the metal and the polymer, thereby forming gaps alongside the metal. A cover metal may be plated onto the metal in the gaps. The cover metal protects the principal metal during subsequent etching procedures.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: February 19, 2008
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Irina Poukhova, Masud Beroz
  • Patent number: 7294248
    Abstract: A method of forming an electron emitter includes the steps of: (i) forming a nanostructure-containing material; (ii) forming a mixture of nanostructure-containing material and a matrix material; (iii) depositing a layer of the mixture onto at least a portion of at least one surface of a substrate by electrophoretic deposition; (iv) sintering or melting the layer thereby forming a composite; and (v) electrochemically etching the composite to remove matrix material from a surface thereof, thereby exposing nanostructure-containing material.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: November 13, 2007
    Assignee: Xintek, Inc.
    Inventor: Bo Gao
  • Patent number: 7135120
    Abstract: The UV, deep UV and/or far UV (ultraviolet) filter transmission spectrum of an MPSi spectral filter is optimized by introducing at least one layer of substantially transparent dielectric material on the pore walls. Such a layer will modify strongly the spectral dependences of the leaky waveguide loss coefficients through constructive and/or destructive interference of the leaky waveguide mode inside the layer. Increased blocking of unwanted wavelengths is obtained by applying a metal layer to one or both of the principal surfaces of the filter normal to the pore directions. The resulting filters are stable, do not degrade over time and exposure to UV irradiation, and offer superior transmittance for use as bandpass filters. Such filters are useful for a wide variety of applications including but not limited to spectroscopy and biomedical analysis systems.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: November 14, 2006
    Assignee: Lake Shore Cryotronics, Inc.
    Inventors: Vladimir Kochergin, Philip Swinehart
  • Patent number: 7045052
    Abstract: A method of manufacture for optical spectral filters with omnidirectional properties in the visible, near IR, mid IR and/or far IR (infrared) spectral ranges is based on the formation of large arrays of coherently modulated waveguides by electrochemical etching of a semiconductor wafer to form a pore array. Further processing of said porous semiconductor wafer optimizes the filtering properties of such a material. The method of filter manufacturing is large scale compatible and economically favorable. The resulting exemplary non-limiting illustrative filters are stable, do not degrade over time, do not exhibit material delamination problems and offer superior transmittance for use as bandpass, band blocking and narrow-bandpass filters. Such filters are useful for a wide variety of applications including but not limited to spectroscopy, optical communications, astronomy and sensing.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: May 16, 2006
    Assignee: Lake Shore Cryotronics, Inc.
    Inventors: Vladimir Kochergin, Philip Swinehart
  • Patent number: 6805972
    Abstract: The present invention is directed to nanoporous metal membranes and methods of making nanoporous metal membranes from metal leaf. At least a portion of the metal leaf is freely supported by a de-alloying medium for a time effective to de-alloy the metal leaf. After the porous membrane is formed, the membrane may be re-adhered to a substrate and removed from the de-alloying medium. The de-alloying process may be thermally and electrically influenced.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: October 19, 2004
    Assignee: Johns Hopkins University
    Inventors: Jonah Erlebacher, Yi Ding
  • Patent number: 6803637
    Abstract: A micromechanical component having a substrate made from a substrate material having a first doping type, a micromechanical functional structure provided in the substrate and a cover layer to at least partially cover the micromechanical functional structure. The micromechanical functional structure has zones made from the substrate material having a second doping type, the zones being at least partially surrounded by a cavity, and the cover layer has a porous layer made from the substrate material.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: October 12, 2004
    Assignee: Robert Bosch GmbH
    Inventors: Hubert Benzel, Heribert Weber, Hans Artmann, Frank Schaefer
  • Patent number: 6790340
    Abstract: An electrochemical etching system has an etching bath for holding an n-type silicon substrate with a first surface of the substrate in contact with hydrofluoric acid, an electrode positioned in the hydrofluoric acid, a power source having a positive pole connected to the silicon substrate and a negative pole connected to the electrode, and an illumination unit having a light source for illumination of a second surface of the silicon substrate. The illumination unit illuminates the second surface of the silicon substrate with an illumination intensity of 10 m W/cm2 or more. A ratio of a maximum illumination to a minimum illumination of the second surface of the silicon substrate is 1.69:1 or less. With the etching system, pores and/or trenches of a certain size and shape can be formed in an entire area of the silicon substrate having a diameter of more than three inches.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: September 14, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinichi Izuo, Hiroshi Ohji, Kazuhiko Tsutsumi, Patrick James French
  • Patent number: 6743406
    Abstract: A family of discrete and uniformly sized silicon nanoparticles, including 1 (blue emitting), 1.67 (green emitting), 2.15 (yellow emitting), 2.9 (red emitting) and 3.7 nm (infrared emitting) nanoparticles, and a method that produces the family. The nanoparticles produced by the method of the invention are highly uniform in size. A very small percentage of significantly larger particles are produced, and such larger particles are easily filtered out. The method for producing the silicon nanoparticles of the invention utilizes a gradual advancing electrochemical etch of bulk silicon, e.g., a silicon wafer. The etch is conducted with use of an appropriate intermediate or low etch current density. An optimal current density for producing the family is ˜10 milli Ampere per square centimeter (10 mA/cm2). Higher current density favors 1 nm particles, and lower the larger particles.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: June 1, 2004
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Munir H. Nayfeh, Gennadey Belomoin, Satish Rao, Joel Therrien, Sahraoui Chaieb
  • Patent number: 6726815
    Abstract: An electrochemical etching cell (1) is proposed for etching an etching body (15) made at least superficially of an etching material. The etching cell (1) has at least one chamber filled with an electrolyte, and is provided with a first electrode (13), which at least superficially has a first electrode material, and with a second electrode (13′) which at least superficially has a second electrode material. Furthermore, the etching body (15) is in contact, at least region-wise, with the electrolyte. In this context, the first electrode material and the second electrode material are selected such that, after the etching, the etching body (15) is not contaminated and/or is not impaired in its properties by the electrode materials. In particular, the electrode materials are the same materials as the etching material. Also proposed is a method for etching an etching body (15) using this etching cell (1), the first and/or the second electrode (13, 13′) being used as a sacrificial electrode.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: April 27, 2004
    Assignee: Robert Bosch GmbH
    Inventors: Hans Artmann, Wilhelm Frey, Franz Laermer
  • Patent number: 6706166
    Abstract: A method for improving an electrodeposited metal film uniformity and preventing metal deposition and peeling of deposited metal from an electrode during an electrodeposition and electropolishing process including providing a first anode electrode assembly and a semiconductor wafer plating surface disposed in an electrolyte bath including a plating metal for deposition onto the semiconductor wafer plating surface; providing at least one additional anode electrode assembly including the plating metal disposed peripheral to the first anode electrode assembly for selectively applying the cathodic electrical potential during an electropolishing process; and, periodically alternating between an electrodeposition process and electropolishing process with respect to the semiconductor wafer plating surface such that the plating metal is preferentially plated onto the at least one additional electrode assembly.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: March 16, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Shih-Wei Chou, Ming-Hsing Tsai
  • Publication number: 20040011666
    Abstract: A method for selectively removing a layer of electrolytically dissoluble metal from a substrate comprising providing a substrate bearing' on a major surface thereof a layer of electrolytically dissoluble metal, said metal layer serving; as a dissoluble electrode; providing at least a first counterelectrode and a second counterelectrode; positioning said counterelectrodes opposite said metal layer and spaced from said metal layer; in a first electrolytic step, interposing an electrolyte between said metal and said first counterelectrode and in electrical contact with said metal layer and said electrode and passing an electric current between said first counterelectrode and said metal layer, wherein said first counterelectrode is maintained cathodic to said metal layer, for a period of time until said metal layer has been removed from a first central region of said surface of said substrate opposite said first counterelectrode; in a second electrolytic step, interposing an electrolyte between said metal and sai
    Type: Application
    Filed: June 11, 2003
    Publication date: January 22, 2004
    Inventors: E. Jennings Taylor, Heather Dyar, Patrick MacCarthy
  • Publication number: 20030221973
    Abstract: A method and apparatus for the electrochemical machining of grooves for a hydrodynamic bearing is provided. Grooves and a relief cut are simultaneously electrochemically etched into a surface of a workpiece.
    Type: Application
    Filed: January 10, 2003
    Publication date: December 4, 2003
    Inventors: Gunter Heine, Klaus Dieter Kloeppel, Dustin Alan Cochran
  • Publication number: 20030205477
    Abstract: An electrode assembly arrangement for improving an electrodeposition process and method for using the same the electrode assembly arrangement including a first electrode assembly and a second electrode assembly positioned to carry a metal containing electrolyte from the first electrode assembly to the second electrode assembly for deposition of the metal upon applying an electrical potential therebetween; at least one additional electrode assembly including a means for selectively applying an electrical potential thereto the at least one additional electrode assembly positioned to attract an electrolyte flow upon applying an electrical potential between the at least one additional electrode assembly and the second electrode assembly.
    Type: Application
    Filed: May 6, 2002
    Publication date: November 6, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Chou, Ming-Hsing Tsai
  • Patent number: 6602397
    Abstract: A method for the production of filters in which a blank of n- or p-doped etchable semiconductor material is connected as an anode or a cathode according to doping. The method includes contacting a first side of the blank with an etching solution in which a counterelectrode is arranged to electrochemically etch the first side, and supplying activation energy to generate minority charge carriers to the blank during the etching process. The activation energy supplied per unit time is reduced with increasing etching progress.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: August 5, 2003
    Assignee: NFT Nanofiltertechnik Gesellschaft mit beschrankter Haftung
    Inventor: Wilfried Hofmann
  • Patent number: 6585947
    Abstract: A method for producing the silicon nanoparticle of the invention is a gradual advancing electrochemical etch of bulk silicon. Separation of nanoparticles from the surface of the silicon may also be conducted. Once separated, various methods may be employed to form nanoparticles into colloids, crystals, films and other desirable forms. The particles may also be coated or doped.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: July 1, 2003
    Assignee: The Board of Trustess of the University of Illinois
    Inventors: Munir H. Nayfeh, Joel Therrien, Zain H. Yamani
  • Publication number: 20030062269
    Abstract: The present invention discloses an apparatus having a platen; a polishing pad disposed over the platen; a slurry dispenser disposed over the polishing pad; a cathode connected electrically to the polishing pad; a wafer carrier disposed over the polishing pad;
    Type: Application
    Filed: September 28, 2001
    Publication date: April 3, 2003
    Inventor: Sujit Sharan
  • Patent number: 6521118
    Abstract: There is provided a process for etching a semiconductor material, comprising the steps of: providing an electrochemical cell containing an etching electrolyte, the etching electrolyte being selected from the group of acidic electrolyte solutions, alkaline solutions, neutral solutions, and molten electrolytes; immersing the semiconductor material in the etching electrolyte, whereby at least one surface of the semiconductor material contacts the etching electrolyte; thereafter negatively biasing the semiconductor material; and while continuing to negatively bias the semiconductor material, illuminating at least part of the at least one surface of the semiconductor material which contacts the etching electrolyte with light selected from the group of ultraviolet, visible, and infrared light. There is also provided an apparatus for effecting the process of the invention, as well as semiconductor materials so etched.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: February 18, 2003
    Assignee: Technion Research and Development Foundation
    Inventors: David Starosvetsky, Mark Kovler, Joseph Yahalom, Yael Nemirovsky
  • Publication number: 20020139690
    Abstract: A method for producing water containing ozone by electrolysis, using an apparatus comprising,
    Type: Application
    Filed: October 17, 2001
    Publication date: October 3, 2002
    Inventors: Takafumi Kanaya, Noriaki Okubo
  • Patent number: 6440295
    Abstract: An electropolishing apparatus for polishing a metal layer formed on a wafer (31) includes an electrolyte (34), a polishing receptacle (100), a wafer chuck (29), a fluid inlet (5, 7, 9), and at least one cathode (1, 2, 3). The wafer chuck (29) holds and positions the wafer (31) within the polishing receptacle (100). The electrolyte (34) is delivered through the fluid inlet (5, 7, 9) into the polishing receptacle (100). The cathode (1, 2, 3) then applies an electropolishing current to the electrolyte to electropolish the wafer (31). In accordance with one aspect of the present invention, discrete portions of the wafer (31) can be electropolished to enhance the uniformity of the electropolished wafer.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: August 27, 2002
    Assignee: ACM Research, Inc.
    Inventor: Hui Wang
  • Publication number: 20020108861
    Abstract: An electrochemical planarization apparatus for planarizing a metallized surface on a workpiece includes a polishing pad and a platen. The platen is formed of conductive material, is disposed proximate to the polishing pad and is configured to have a negative charge during at least a portion of a planarization process. At least one electrical conductor is positioned within the platen. The electrical conductor has a first end connected to a power source. A workpiece carrier is configured to carry a workpiece and press the workpiece against the polishing pad. The power source applies a positive charge to the workpiece via the electrical conductor so that an electric potential difference between the metallized surface of the workpiece and the platen is created to remove at least a portion of the metallized surface from the workpiece.
    Type: Application
    Filed: February 12, 2001
    Publication date: August 15, 2002
    Inventors: Ismail Emesh, Saket Chadda, Nikolay Korovin, Brian L. Mueller
  • Patent number: 6413408
    Abstract: An interference filter having a layer with an area consisting of a porous material extending from the surface of the layer to the interior, the dimensions of the porous layer area in a direction normal to the layer surface have different values to provide for varying reflection or, respectively, transmission characteristics.
    Type: Grant
    Filed: June 19, 1999
    Date of Patent: July 2, 2002
    Assignee: Forschungszentrum Jülieh GmbH
    Inventors: Michael Berger, Michael Krüger, Markus Thönissen, Rüdiger Arens-Fischer, Hans Lüth, Walter Lang, Wolfgang Theiss, Stefan Hilbrich
  • Publication number: 20020074239
    Abstract: In an interference filter having a layer with an area consisting of a porous material extending from the surface of the layer to the interior, the dimensions of the porous layer area in a direction normal to the layer surface have different values to provide for varying reflection or, respectively, transmission characteristics.
    Type: Application
    Filed: June 19, 1999
    Publication date: June 20, 2002
    Inventors: MICHAEL BERGER, MICHAEL KRUGER, MARKUS THONISSEN, RUDIGER ARENS-FISCHER, HANS LUTH, WALTER LANG, WOLFGANG THEISS, STEFAN HILBRICH
  • Publication number: 20020074238
    Abstract: The present invention pertains to apparatus and methods for planarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by increasing the fluid agitation in raised regions with respect to recessed regions. That is, the agitation of the electropolishing bath fluid is agitated or exchanged as a function of elevation on the metal film profile. The higher the elevation, the greater the movement or exchange rate of bath fluid. In preferred methods of the invention, this agitation is achieved through the use of a microporous electropolishing pad that moves over (either near or in contact with) the surface of the wafer during the electropolishing process. Thus, methods of the invention are electropolishing methods, which in some cases include mechanical polishing elements.
    Type: Application
    Filed: September 28, 2001
    Publication date: June 20, 2002
    Inventors: Steven T. Mayer, Robert J. Contolini, Eliot K. Broadbent, John S. Drewery
  • Patent number: 6398940
    Abstract: A novel method to fabricate nanoscale pits on Au(111) surfaces in contact with aqueous solution is claimed. The method uses in situ electrochemical scanning tunnelling microscopy with independent electrochemical substrate and tip potential control and very small bias voltages. This is significantly different from other documented methods, which mostly apply high and short voltage pulses. The most important advantages of the present method are that the dimensions and positions of the pits can be controlled with high precision in aqueous environment so that nanopatterns of the pits can be designed, and that the operations are simple and require no instrumental accessories. Parameters, which control the pit formation and size, have been systematically characterized and show that the primary controlling parameter is the bias voltage. A mechanism based on local surface reconstruction induced by electronic contact between tip and substrate is in keeping with the overall patterns for pit formation.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: June 4, 2002
    Assignee: Danmarks Tekniske Universitet
    Inventors: Quijin Chi, Jingdong Zhang, Jens Enevold Thaulov Andersen, Jens Ulstrup, Esben Peter Friis
  • Patent number: 6376285
    Abstract: An epitaxial layer of silicon is grown on a layer of partially-oxidized porous silicon, then covered by a capping layer which provides structural support and prevents oxidation of the epitaxial layer. A high-temperature anneal allows the partially oxidized silicon layer to separate into distinct layers of silicon and SiO2, producing a buried oxide layer. This method provides a low cost means of producing silicon-on-insulator (SOI) wafers.
    Type: Grant
    Filed: May 20, 1999
    Date of Patent: April 23, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Keith A. Joyner, Leland S. Swanson
  • Patent number: 6340425
    Abstract: In the manufacturing of the cold cathode device which has a porous silicon portion as an emitter portion, the silicon layer is given an electric potential, while the gate electrode is given an electric potential lower than that of the silicon layer. And thereby, the predetermined portion of the silicon layer is subjected to anodic etching to be rendered into the porous silicon portion. With such anodic etching, the cold cathode device with the porous silicon portion is obtained.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: January 22, 2002
    Assignee: NEC Corporation
    Inventor: Fuminori Ito
  • Patent number: 6328876
    Abstract: A method for producing a filter includes the steps of providing a blank of etchable semiconductor material having a first side and a second side and affixing a holding element to the blank. The holding element is chemically resistant to an etching solution. A current source is connected to the blank and at least one of the first and second sides of the blank is illuminated with light. The holding element and the blank are immersed in the etching solution until the first side of the blank is wetted so that the first side is etched electrochemically. The holding element is affixed to the blank such that contact areas between the holding element and the blank remain free of the etching solution.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: December 11, 2001
    Assignee: NFT Nanofiltertechnik Gesellschaft mit beschankter Haftung
    Inventors: Wilfried Hofmann, Tschangiz Scheybani
  • Patent number: 6193762
    Abstract: An attachment surface for an implantable device has a random irregular pattern formed through a repetitive masking and chemical milling process. Additionally, an attachment surface for an implantable device has a random irregular pattern formed through a repetitive masking and electrochemical milling process. The electrochemical milling process is particularly well suited for use with substrate materials which have high chemical inertness which makes them resistant to chemical etching. Surface material is removed from the implant surface without stress on the adjoining material and the process provides fully dimensional fillet radii at the base of the surface irregularities. This irregular surface is adapted to receive the ingrowth of bone material and to provide a strong anchor for that bone material. The unitary nature of the substrate and surface features provides a strong anchoring surface with is resistant to cracking or breaking.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: February 27, 2001
    Assignees: Cycam, Inc., Tech Met, Inc.
    Inventors: Donald J. Wagner, Gary Reed
  • Patent number: 6180526
    Abstract: A method for improving the conformity of the conductive layer in a contact hole, thus allowing for the formation of a plug in the resulting contact hole. The aforementioned method includes the following steps. First, immerse the conductive layer of the semiconductor wafer into an electrolyte. The first portion of the conductive layer at the opening of the contact hole contact with the electrolyte, the conductive layer in the contact hole is not in contact with the electrolyte due to the surface tension of the electrolyte. Second, electrically couple the electrolyte to the anode of the source power. Finally, electrically couple the conductive layer to the cathode of the power source until the first portion of the conductive layer at the opening of the contact hole is removed.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: January 30, 2001
    Assignee: Industrial Technology Research Institute
    Inventor: Chung-Liang Chang
  • Patent number: 6139758
    Abstract: A method of manufacturing a micromachined thermal flowmeter is provided. The major manufacturing steps comprise forming an n-type region(s) in a p-type silicon wafer, forming heating and temperature sensing devices in the n-type region(s), converting the n-type region(s) into porous silicon by anodization in a HF solution, bonding the silicon wafer onto a glass plate using a polyimide layer as an adhesive layer, removing the porous silicon in a diluted base solution, and coating the heating and temperature sensing devices with a corrosion-resistant and abrasion-resistant material.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: October 31, 2000
    Assignee: Enlite Laboratories, Inc.
    Inventor: Xiangzheng Tu