Abstract: A method of manufacturing electronic module is provided. The method can perform selective partial molding by forming the tapes in a predetermined area on the circuit substrate, setting electronic components out the predetermined area on the circuit substrate, forming the molding member encapsulating the whole circuit substrate and removing the tapes along of the molding member thereon. Following, forming an EMI shielding layer on the molding member and setting optoelectronics in the predetermined area on the circuit substrate could protect the electronic components from electromagnetic disturbance and avoid the optoelectronics being encapsulated.

Abstract: A method for protecting an electronic device comprising an organic device body. The method involves the use of a hybrid layer deposited by chemical vapor deposition. The hybrid layer comprises a mixture of a polymeric material and a non-polymeric material, wherein the weight ratio of polymeric to non-polymeric material is in the range of 95:5 to 5:95, and wherein the polymeric material and the non-polymeric material are created from the same source of precursor material. Also disclosed are techniques for impeding the lateral diffusion of environmental contaminants.

Abstract: A method for forming patterns in a semiconductor device includes providing a substrate and a patterning-target layer formed over the substrate; forming a first feature in a first hard mask layer formed over the patterning-target layer; and forming a second feature in a second hard mask layer formed over the patterning-target layer. The first hard mask layer has a different etching selectivity from the second hard mask layer. The method further includes selectively removing a portion of the first feature within a first trench to form a reshaped first feature. In an embodiment, the first trench exposes a portion of the second feature, and the selectively removing of the first portion of the first feature does not etch the portion of the second feature.

Abstract: Anode active materials, anodes, and batteries are provided. In one embodiment, an anode active material includes particles consisting essentially of a material selected from the group consisting of silicon and an alloy of silicon. An average degree of circularity of the particles is 90% or less.

Abstract: A method of manufacturing a display panel, including providing a plurality of display substrates spaced apart from each other by a predetermined area disposed therebetween when viewed in a plan view, each of the display substrates including a display area, on which an image is displayed, and each of the display substrates being flexible; attaching a first film onto the display substrates to overlap with the display substrates; attaching a second film onto the first film; and substantially and simultaneously cutting the first and second films along a cutting line defined in an area overlapping with the predetermined area.

Abstract: In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the <111> direction of the silicon. A nanowire is grown directly on at least one of the sidewalls of the silicon and is formed from a material selected from Groups III-V. Only one end of the nanowire directly contacts the silicon.

Abstract: Alternating touchscreen conductors in each layer of a touchscreen display are connected to separate touchscreen controllers. Each controller completely and separately resolves a location anywhere on the display so that a failure of either controller, or the failure of conductors connected to either controller, do not degrade touchscreen usability. Conductors in separate layers, connected to separate controllers may be isolated via insulators to prevent undesirable shorts. Conductors are shaped to minimize the area covered by insulators and maximize the area of useful conductor overlap.

Abstract: A ceramic-capacitor includes a first electrically-conductive-layer, a second electrically-conductive-layer arranged proximate to the first electrically-conductive-layer, and a dielectric-layer interposed between the first electrically-conductive-layer and the second electrically-conductive-layer. The dielectric-layer is formed of a lead-lanthanum-zirconium-titanate material (PLZT), wherein the PLZT is characterized by a dielectric-constant greater than 125, when measured at 25 degrees Celsius and zero Volts bias, and an excitation frequency of ten-thousand Hertz (10 kHz). A method for increasing a dielectric constant of the lead-lanthanum-zirconium-titanate material (PLZT) includes the steps of depositing PLZT to form a dielectric-layer of a ceramic-capacitor, and heating the ceramic-capacitor to a temperature not greater than 300° C.

Abstract: The invention provides a process for forming crack-free dielectric films on a substrate. The process comprises the application of a dielectric precursor layer of a thickness from about 0.3 ?m to about 1.0 ?m to a substrate. The deposition is followed by low temperature heat pretreatment, prepyrolysis, pyrolysis and crystallization step for each layer. The deposition, heat pretreatment, prepyrolysis, pyrolysis and crystallization are repeated until the dielectric film forms an overall thickness of from about 1.5 ?m to about 20.0 ?m and providing a final crystallization treatment to form a thick dielectric film. The process provides a thick crack-free dielectric film on a substrate, the dielectric forming a dense thick crack-free dielectric having an overall dielectric thickness of from about 1.5 ?m to about 20.0 ?m.

Abstract: A method for fabricating an electrochemical sensing test piece comprises steps: forming an electrode layer on a substrate; etching the electrode layer to reduce the area of the electrode layer to be smaller than the area of the substrate, wherein the electrode layer has a test zone and a reading zone neighboring the test zone; forming an insulation member surrounding the test zone and covering the perimeter of the test zone; forming an enzyme layer on the test zone; and forming an insulation layer on the enzyme layer and the periphery of the reading zone and fabricating the insulation layer to have an opening revealing a portion of the enzyme layer. The insulation member fixes the effective reaction area of the tested material and increases measurement accuracy.

Abstract: Techniques for use of wafer bonding techniques for sealing of microfluidic chips are provided. In one aspect, a wafer bonding sealing method includes the steps of: forming a first oxide layer coating surfaces of a first wafer, the first wafer having at least one fluidic chip; forming a second oxide layer on a second wafer; and bonding the first wafer to the second wafer via an oxide-to-oxide bond between the first oxide layer and the second oxide layer to form a bonded wafer pair, wherein the second oxide layer seals the at least one fluidic chip on the first wafer. The second wafer can be at least partially removed after performing the bonding, and fluidic ports may be formed in the second oxide layer. A fluidic chip device is also provided.

Abstract: Provided herein is a method for manufacturing a conductive transparent substrate, the method including forming a plurality of main electrodes on the substrate such that the main electrodes are distanced from one another; and forming a connecting electrode that electrically connects two or more main electrodes such that the plurality of main electrodes are grouped into a plurality of group electrodes that are electrically disconnected from one another, thereby producing a conductive transparent substrate with excellent transmittance in a process of high yield.

Abstract: The present invention relates to a capacitive fingerprint sensing device for sensing a fingerprint pattern. The sensing device comprises a protective dielectric top layer having an outer surface forming a sensing surface to be touched by the finger; a two-dimensional array of electrically conductive sensing structures arranged underneath the top layer; readout circuitry coupled to each of the electrically conductive sensing structures to receive a sensing signal indicative of a distance between the finger and the sensing structure; and an electroacoustic transducer arranged underneath the top layer and configured to generate an acoustic wave, and to transmit the acoustic wave through the protective dielectric top layer towards the sensing surface to induce an ultrasonic vibration potential in a ridge of finger placed in contact with the sensing surface.

Abstract: A method of forming a circuit board includes forming a conductive pattern on a substrate; forming a first negative resist on the substrate after formation of the conductive pattern; partially exposing the first negative resist on the surface of the conductive pattern to form a first via exposure portion; forming a second negative resist on the substrate after formation of the first via exposure portion; partially exposing the second negative resist on the first via exposure portion to form a second via exposure portion larger than the first via exposure portion; developing the first negative resist and the second negative resist after formation of the second via exposure portion to form a via opening reaching the conductive pattern; and filling the via opening with a conductive material.

Abstract: A wiring substrate includes a wiring layer on a projection of an insulating layer. The wiring layer includes a first metal layer on an end face of the projection with a peripheral portion of the end face exposed, a second metal layer that is on the first metal layer and wider than the end face, and a third metal layer. The second metal layer includes first and second opposite surfaces with the second surface on the first metal layer with a peripheral portion thereof exposed. The third metal layer covers side surfaces of the first metal layer, and the first surface, the peripheral portion of the second surface, and side surfaces of the second metal layer, and fills in a region where the end face and the peripheral portion of the second surface face each other. The materials of the second and third metal layers are different.

Abstract: A solder alloy is providing, the solder alloy including zinc, aluminum, magnesium and gallium, wherein the aluminum constitutes by weight 8% to 20% of the alloy, the magnesium constitutes by weight 0.5% to 20% of the alloy and the gallium constitutes by weight 0.5% to 20% of the alloy, the rest of the alloy including zinc.

Abstract: An etching chamber is equipped with an actively-cooled element preferentially adsorbs volatile compounds that are evolved from a polymeric layer of a wafer during etching, which compounds will act as contaminants if re-deposited on the wafer, for example on exposed metal contact portions where they may interfere with subsequent deposition of metal contact layers. In desirable embodiments, a getter sublimation pump is also provided in the etching chamber as a source of getter material. Methods of etching in such a chamber are also disclosed.

Abstract: Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.

Abstract: A wiring board includes a base layer, a plurality of connection terminals and a surface layer. The base layer is electrically insulative. The plurality of connection terminals are conductive and formed on the base layer. The surface layer is electrically insulative, and fills gaps between the plurality of connection terminals on the base layer. The connection terminals include a base portion made of a conductive first metal and a coating portion made of a conductive second metal that is different from the first metal. The coating portion penetrates the surface layer, and coats the base portion to the base layer.

Abstract: An electrode which can have an improved performance such as higher discharge capacity and in which deterioration due to peeling of an active material layer or the like is difficult to occur are provided. The electrode includes an active material layer including a first protrusion, a second protrusion and a continuous active material film, a metal oxide layer, and a continuous mixed layer. The first protrusion, the second protrusion and the continuous active material film includes silicon. The metal oxide layer includes oxygen and a metal element which is capable of forming silicide by reacting with silicon. The continuous mixed layer includes silicon and the metal element.

Abstract: A circuit board including a core layer having a first surface and a second surface opposite to the first surface; a first build-up layer and a second build-up layer formed on the first surface and the second surface of the core layer, respectively, and including a conductive pattern and a conductive via; and an outer layer formed on the surface of the first build-up layer and the second build-up layer, wherein at least one build-up layer of the first build-up layer and the second build-up layer comprises a photosensitive insulating layer in which a cavity is disposed and a thermal dissipation unit disposed in the cavity.

Abstract: A die is manufactured using complementary metal-oxide semiconductor (CMOS) techniques to create transistors, electrical pathways, and microelectromechanical system (MEMS) structures. The MEMS structures include springs, plates, mechanical stops, and structural supports, which can be combined to form complex MEMS structures including microphones, pressure sensors, accelerometers, resonators, gyroscopes, and the like.

Abstract: A method can be used for producing a microelectromechanical transducer. A plurality of microelectromechanical transducers are produced on a single wafer. Each transducer includes a diaphragm. The wafer is divided into at least a first and a second region. The mechanical tensions of a random sample of diaphragms of the first region are established and the values are compared with a predetermined desired value. The mechanical tensions of a random sample of diaphragms of the second region are established and the values are compared with the predetermined desired value. The tensions of the diaphragms in the first region are adjusted to the predetermined desired value, and the tensions of the diaphragms in the second region are adjusted to the predetermined desired value.

Abstract: A method includes cutting a semiconductor wafer on a substrate wafer using at least one laser. By setting the laser to a set of parameters that define a laser beam, the laser beam can avoid ablation of the substrate wafer. The laser beam is also set equal to, or within, an ablation threshold of the semiconductor wafer for selectively ablating the semiconductor wafer. The set of parameters includes wavelength, pulse width and pulse frequency.

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.

Abstract: A method of processing a substrate that displays out-gassing when placed in a vacuum comprises placing the substrate in a vacuum and performing an out-gassing treatment by heating the substrate to a temperature T1 and removing gaseous contamination emitted from the substrate until the out-gassing rate is determined by the diffusion of the substrate's contamination and thus essentially a steady state has been established. Afterwards, the temperature is lowered to a temperature T2 at which the diffusion rate of the substrate's contamination is lower than at T1. The substrate is further processed at said temperature T2 until the substrate has been covered with a film comprising a metal.

Abstract: A system and method for removing metal from a substrate in a controlled manner is disclosed. The system includes a chamber, with one or more gas inlets to allow the flow of gasses into the chamber, at least one exhaust pump, to exhaust gasses from the chamber, and a heater, capable of modifying the temperature of the chamber. In some embodiments, one or more gasses are introduced into the chamber at a first temperature. The atoms in these gasses chemically react with the metal on the surface of the substrate to form a removable compound. The gasses are then exhausted from the chamber, leaving the removable compound on the surface of the substrate. The temperature of the chamber is then elevated to a second temperature, greater than the sublimation temperature of the removable compound. This increased temperature allows the removable compound to become gaseous and be exhausted from the chamber.

Abstract: An exemplary method for making a light blocking plate includes the steps of providing a flat plate-like light pervious member; forming a plurality of spaced ceramic power layers on the light pervious member; forming a light blocking layer over the light pervious member and side faces of the ceramic power layers; forming an electromagnetic shielding layer over the light blocking layer; removing top portions of the ceramic power layers with remaining portions of the ceramic power layers thus exposed; and removing the remaining portions of the ceramic power layers.

Abstract: The present disclosure relates to a prepreg formed by drying a fabric substrate impregnated with a resin composition by means of heating until the resin composition is in a semi-cured state. The resin composition contains (A) at least one of an epoxy resin having naphthalene skeleton and a phenolic curing agent; and (B) a polymer having structures represented by the following formulae (I) and (II), no unsaturated bond between carbon atoms, an epoxy value ranging from 0.2 to 0.8 ep/kg, and an weight-average molecular weight ranging from 200,000 to 850,000: wherein X:Y=0:1 to 0.35:0.65, R1 represents H or CH3, and R2 represents H or an alkyl group.

Abstract: The present disclosure provides a touch panel, including: a cover lens, an optical compensation layer and a sensing electrode layer disposed between the cover lens and the optical compensation layer, wherein an etching region and a non-etching region are defined in the sensing electrode layer; an optical match is formed by the optical compensation layer with the sensing electrode layer, wherein the optical compensation layer receives incident light through the cover lens and the sensing electrode to reconcile the hue of the reflected light correspondingly formed from the etching region and the non-etching region. The present disclosure also provides a method for fabricating a touch panel.

Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a selection element, a lower electrode pattern provided on the selection element to include a horizontal portion and a vertical portion; and a phase-changeable pattern on the lower electrode pattern. The vertical portion may extend from the horizontal portion toward the phase-changeable pattern and have a top surface, whose area is smaller than that of a bottom surface of the phase-changeable pattern.

Abstract: A surface treated copper foil which is well bonded to a resin and achieves excellent visibility when observed through the resin, and a laminate using the same are provided.

Abstract: A method for manufacturing a semiconductor device is provided. A substrate with an insulation formed thereon is provided, wherein the insulation has plural trenches, and the adjacent trenches are spaced apart from each other. A barrier layer is formed on an upper surface of the insulation and in sidewalls of the trenches, and the barrier layer comprises overhung portions corresponding to the trenches. A seed layer is formed on the barrier layer. Then, an upper portion of the seed layer formed on an upper surface of the barrier layer is removed. An upper portion of the barrier layer is removed for exposing the upper surface of the insulation. Afterwards, the conductors are deposited along the seed layer for filling up the trenches, wherein the top surfaces of the conductors are substantially aligned with the upper surface of the insulation.

Abstract: The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Abstract: A method for fabricating a transistor including the following steps is provided. First, a gate electrode is formed on a substrate, and a gate insulating layer is formed on the substrate in sequence, wherein the gate insulating layer covers the substrate and the gate electrode. Next, a patterned channel layer and a hard-mask layer are formed on the gate insulating layer, wherein the patterned channel layer and the hard-mask layer are located above the gate electrode, and the hard-mask layer is disposed on the patterned channel layer. Afterwards, a source and a drain are formed on the gate insulating layer by a wet etchant. The part of the hard-mask layer that is not covered by the source and the drain is removed by the wet etchant until the patterned channel layer is exposed, so as to form a plurality of patterned hard-mask layers.

Abstract: An optical electronic device and method that forms cavities through an interposer wafer after bonding the interposer wafer to a window wafer. The cavities are etched into the bonded interposer/window wafer pair using the anti-reflective coating of the window wafer as an etch stop. After formation of the cavities, the bonded interposer/window wafer pair is bonded peripherally of die areas to the MEMS device wafer, with die area micromechanical elements sealed within respectively corresponding ones of the cavities.

Abstract: A rectenna according to the present invention includes a circular-polarized patch antenna having dual slots fed by a microstrip and configured to receive and output a radio frequency (RF) signal, and a rectifying circuit configured to convert for output the RF signal, received by the circular-polarized patch antenna, into a direct current (DC) signal and transfer the DC signal from the antenna to a load, wherein the rectifying circuit comprises at least one radial stub.

Abstract: A sintered article in which a solid body is at least partially embedded includes an opening. The solid body extends across the opening so that the solid body can deform within the opening. The opening in the solid body prevents distortion of the sintered body from a planar configuration during sintering, even when the green body that is sintered is relatively thin.

Abstract: Embodiments of the present invention provide a preparation method of a patterned film, a display substrate and a display device, avoiding falling off of a film layer occurring in the process of peeling off a photoresist layer. The preparation method of the patterned film comprises: forming a preset film layer on a surface of a preset substrate; covering the preset film layer with an isolation layer; forming a photoresist layer on a surface of the isolation layer and forming a pattern of the isolation layer with a patterning process; then removing the preset film layer which is not covered by the pattern of the isolation layer, peeling off the photoresist layer and removing the remaining, isolation layer to form a pattern of the preset film layer.

Abstract: An active matrix organic light-emitting diode array substrate, a manufacturing method thereof and a display device including the same are disclosed to improve the aperture ratio of pixel of the array substrate and the display quality of the display device. The array substrate includes: a substrate; and a plurality of pixel units located on the substrate and arranged in array manner, each of the pixel units comprising a thin film transistor, a first transparent electrode, a second transparent electrode and a gate insulation layer provided between the first transparent electrode and the second transparent electrode. The first transparent electrode is provided on the substrate and is electrically connected to a gate of the thin film transistor; and the second transparent electrode is electrically connected to a drain of the thin film transistor, and the second transparent electrode is positioned opposite to the first transparent electrode to form a storage capacitor of the pixel unit therebetween.

Abstract: A method for digitally printing on containers by producing a printed multi-colored image on a print layer disposed on a middle layer, the middle layer being one of an intermediate layer and a base layer. The method includes applying the middle layer on an outer surface of a substrate formed by a container wall. An adhesion characteristic between the middle layer and the print layer differs from an adhesion characteristic between the middle layer and the substrate, wherein the adhesion characteristic is selected from the group consisting of adhesion strength and adhesion rate, and wherein the different adhesion characteristics are set by at least one of choice of materials used for the layers and crosslinking of the intermediate layer and the print layer.

Abstract: Embodiments of the present technology may include a method of etching a substrate. The method may include striking a plasma discharge in a plasma region. The method may also include flowing a fluorine-containing precursor into the plasma region to form a plasma effluent. The plasma effluent may flow into a mixing region. The method may further include introducing a hydrogen-and-oxygen-containing compound into the mixing region without first passing the hydrogen-and-oxygen-containing compound into the plasma region. Additionally, the method may include reacting the hydrogen-and-oxygen-containing compound with the plasma effluent in the mixing region to form reaction products. The reaction products may flow through a plurality of openings in a partition to a substrate processing region. The method may also include etching the substrate with the reaction products in the substrate processing region.

Abstract: Embodiments of the present invention describe a method for fabricating a memory device comprising an enlarged space between neighboring bottom electrodes comprising depositing a poly-silicon layer on a substrate depositing a carbon layer above the poly-silicon layer, patterning a photo-resist layer on the carbon layer, depositing a first spacer layer on the photo-resist layer and performing a modified photolithography process on the photo resist layer after etching back the spacer layer creating sidewalls.

Abstract: Techniques described herein generally relate to the fabrication of ultra-capacitor. In one or more embodiments of the present disclosure, methods for fabricating an ultra-capacitor are described that may include preparing a substrate surface of a silicon wafer. The methods may further include etching one or more nano-structures on the substrate surface of the silicon wafer with a galvanic displacement process, and constructing electrodes for the ultra-capacitor from the silicon wafer with the one or more nano-structures.

Abstract: In one aspect, methods of making a carbon coating are described herein. In some implementations, a method of making a carbon coating comprises applying a first adhesive material to a substrate surface to provide an adhesive surface; rolling a carbon source over the adhesive surface to provide a carbon layer on the adhesive surface; and rolling an adhesive roller over the carbon layer to remove some but not all of the carbon of the carbon layer to provide the carbon coating.

Abstract: A stacked optoelectronic packaged device includes a bottom die having a top surface including bottom electrical traces and a light source die coupled to ?1 bottom electrical traces. A first cavity die is on the bottom die. An optics die is on the first cavity die and a second cavity die on the optics die. A mounting substrate is on the second cavity die including top electrical traces. A photodetector die is optically coupled to receive light from the light source. The bottom and top electrical traces are both positioned substantially symmetrically on sides of a mirror plane so that when conducting equal and opposite currents a first magnetic field emanating from the first side and a second magnetic field emanating from the second side cancel one another to provide a reduction in magnetic flux density by more than 50% at one or more die locations on the optics die.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first feature in a first hard mask layer formed over the patterning-target layer; forming a second feature in a second hard mask layer formed over the patterning-target layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the first feature in the first hard mask layer within a first trench to formed a reshaped first feature; selectively removing a portion of the second feature in the second hard mask layer within a second trench to form a reshaped second feature; and transferring the reshaped first feature and the reshaped second feature to the patterning-target layer.

Abstract: An electrode structure includes a first diffusion barrier layer, an aluminum reflective layer formed over the first diffusion barrier layer. The aluminum reflective layer has a thickness from about 500 angstroms (?) to less than 2,000 ?, a second diffusion barrier layer formed over the aluminum reflective layer, and an electrode layer overlying the second diffusion barrier layer. The electrode structure is applicable in a light emitting diode device.

Abstract: A structure having an optical slit therein. The structure includes a substrate having an opening therethrough and a metal layer disposed on the substrate, such metal layer having a photolithographically formed slit therein, such slit being narrower than the opening and being disposed over the opening, portions of the metal layer disposed adjacent the slit being suspended over the opening and other portions of the metal layer being supported by the substrate.