Forming Or Treating Of Groove Or Through Hole Patents (Class 216/17)
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Publication number: 20140197131Abstract: A device comprising a substrate having a surface that comprises a conductive base layer. The device also comprises fluid-support-structures on the conductive base layer. Each of the fluid-support-structures has at least one dimension of about 1 millimeter or less. Each of the fluid-support-structures is coated with an electrical insulator. The device is configured to oscillate a fluid locatable between tops of the fluid-support-structures and the conductive base layer when a voltage is applied between the conductive base layer and the fluid.Type: ApplicationFiled: March 14, 2014Publication date: July 17, 2014Applicant: Alcatel LucentInventors: Joanna Aizenberg, Marc Scott Hodes, Paul Robert Kolodner, Thomas Nikita Krupenkin, Joseph Ashley Taylor
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Patent number: 8778197Abstract: The present invention relates to graphene windows and methods for making same. One method comprises selecting a high purity metal foil, growing a layer of graphene on a first face of the metal foil, patterning the second face of the graphene-modified foil with a polymer, wherein the second face of the graphene-modified foil has an exposed region and etching the second face of the graphene-modified foil in the exposed region until exposing the first layer of graphene.Type: GrantFiled: December 21, 2011Date of Patent: July 15, 2014Assignee: Clean Energy Labs, LLCInventors: William Neil Everett, William Martin Lackowski, Joseph F. Pinkerton
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Publication number: 20140190932Abstract: A mechanism is provided for fabricating nanochannels for a nanodevice. Insulating film is deposited on a substrate. A nanowire is patterned on the film. Insulating material is deposited on the nanowire and film. A first circular hole is formed in the insulating material as an inlet, over a first tip of the nanowire to expose the first tip. A second circular hole is formed as an outlet, over a second tip of the nanowire opposite the first tip to expose the second tip. A nanochannel connects the first and second holes by etching away the nanowire via an etchant in the first and the second holes. A first reservoir is attached over the first hole in connection with the nanochannel at a previous location of the first tip. A second reservoir is attached over the second hole in connection with the nanochannel at a previous location of the second tip.Type: ApplicationFiled: January 10, 2013Publication date: July 10, 2014Applicant: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Binquan Luan, Gustavo A. Stolovitzky, Chao Wang, Deqiang Wang
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Publication number: 20140190728Abstract: The invention provides a method for manufacturing a circuit board comprising the steps of: (a) forming a through hole in a substrate; (b) providing a photo resist to cover a predetermined area adjacent to the through hole on a first surface and a second surface opposite to the first surface of the substrate; and (c) performing an etching process to make the through hole has a shape of dumbbell.Type: ApplicationFiled: March 14, 2013Publication date: July 10, 2014Applicant: ECOCERA OPTRONICS CO., LTD.Inventors: Cheng-Feng Chou, Hung-Pin Lee, Tzu-Yuan Lin
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Publication number: 20140190933Abstract: A method of manufacturing a magnetoresistive-based device includes a metal hard mask that is inert to a top electrode etch chemistry and that has low sputter yield during a magnetic stack sputter. The metal hard mask is patterned by the photo resist and the photo mask is then stripped and the top electrode (overlying magnetic materials of the magnetoresistive-based device) is patterned by the metal hard mask.Type: ApplicationFiled: March 14, 2013Publication date: July 10, 2014Applicant: EVERSPIN TECHNOLOGIES, INC.Inventor: Everspin Technologies, Inc.
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Patent number: 8771528Abstract: A through-hole forming method includes steps of forming a first impurity region (102a) around a region where a through-hole is to be formed in the first surface of a silicon substrate (101), the first impurity region (102) being higher in impurity concentration than the silicon substrate (101), forming a second impurity region (102b) at a position adjacent to the first impurity region (102a) in the depth direction of the silicon substrate (101), the second impurity region (102b) being higher in impurity concentration than the first impurity region (102a), forming an etch stop layer (103) on the first surface, forming an etch mask layer (104) having an opening on the second surface of the silicon substrate (101) opposite to the first surface, and etching the silicon substrate (101) until at least the etch stop layer (103) is exposed via the opening.Type: GrantFiled: February 28, 2013Date of Patent: July 8, 2014Assignee: Canon Kabushiki KaishaInventors: Keiichi Sasaki, Yukihiro Hayakawa
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Publication number: 20140186590Abstract: Disclosed herein are a touch panel integrated with a cover glass and a manufacturing method thereof. The manufacturing method of a touch panel integrated with a cover glass includes: providing a sheet shaped glass substrate; forming grooves in cut regions of the glass substrate; forming a chemical tempered layer on a surface of the glass substrate and groove portions through chemical tempering; and cutting the glass substrate along the groove.Type: ApplicationFiled: October 10, 2013Publication date: July 3, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventor: Jin-Mun RYU
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Publication number: 20140186989Abstract: Provided are: a conductive base for forming a wiring pattern of a collector sheet for solar cells, which has good rust inhibiting properties and solderability without using an organic rust inhibitor that may harm a solar cell element; and a method for producing a collector sheet for solar cells, said method using the conductive base. A conductive base for forming a wiring pattern of a collector sheet for solar cells, which is a conductive base (30) wherein a zinc layer (320) composed of zinc is formed on the surface of a copper foil (310), is used. The conductive base for forming a wiring pattern of a collector sheet for solar cells is characterized in that the zinc layer (320) does not contain chromium and the amount of zinc therein is more than 20 mg/m2 but 40 mg/m2 or less.Type: ApplicationFiled: June 14, 2012Publication date: July 3, 2014Inventors: Takayuki Komai, Satoshi Emoto
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Publication number: 20140184027Abstract: The present disclosure provides a method of singulating a plurality of miniature ultrasound transducers from a wafer. The method includes receiving a wafer on which a plurality of miniature ultrasound transducers is formed. The miniature ultrasound transducers each include a transducer membrane containing a piezoelectric material. The method includes etching, from a front side of the wafer, a plurality of trenches into the wafer. Each trench at least partially encircles a respective one of the miniature ultrasound transducers in a top view. Each trench includes an approximately rounded segment. The method includes thinning the wafer from a back side opposite the front side. The thinning the wafer is performed such that the trenches are open to the back side. The method includes performing a dicing process to the wafer to separate the miniature ultrasound transducers from one another. The dicing process is performed without making crossing cuts in the wafer.Type: ApplicationFiled: December 16, 2013Publication date: July 3, 2014Applicant: VOLCANO CORPORATIONInventors: Cheryl Rice, Dongjuan Chris Xi
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Patent number: 8764996Abstract: A method of patterning a first material on a polymeric substrate is described. The method includes providing a polymeric film substrate having a major surface with a relief pattern including a recessed region and an adjacent raised region, depositing a first material onto the major surface of the polymeric film substrate to form a coated polymeric film substrate, forming a layer of a functionalizing material selectively on the raised region of the coated polymeric film substrate to form a functionalized raised region and an unfunctionalized recessed region, and etching the first material from the polymeric substrate selectively from the unfunctionalized recessed region.Type: GrantFiled: October 18, 2006Date of Patent: July 1, 2014Assignee: 3M Innovative Properties CompanyInventors: Matthew H. Frey, Khanh P. Nguyen
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Patent number: 8768114Abstract: An opto-electric hybrid board which is capable of suppressing the increase in light propagation losses and which is excellent in flexibility, and a method of manufacturing the same are provided. The opto-electric hybrid board includes an electric circuit board, an optical waveguide, and a metal layer. The electric circuit board includes an insulative layer having front and back surfaces, and electrical interconnect lines formed on the front surface of the insulative layer. The optical waveguide is formed on the back surface of the insulative layer of the electric circuit board. The metal layer is formed between the optical waveguide and the back surface of the insulative layer of the electric circuit board. The metal layer is patterned to have a plurality of strips. Cores of the optical waveguide are disposed in a position corresponding to a site where the metal layer is removed by the patterning.Type: GrantFiled: February 25, 2013Date of Patent: July 1, 2014Assignee: Nitto Denko CorporationInventors: Yuichi Tsujita, Yasuto Ishimura, Hiroyuki Hanazono, Naoyuki Tanaka, Yasufumi Yamamoto, Shotaro Masuda, Mayu Ozaki
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Patent number: 8756804Abstract: Disclosed is a printed circuit board, including a base member, an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened, a circuit layer formed on the insulating layer, and a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member. A method of manufacturing the printed circuit board is also provided.Type: GrantFiled: August 19, 2011Date of Patent: June 24, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Hyung Jin Jeon, Young Do Kweon, Seung Wook Park, Seon Hee Moon
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Patent number: 8747682Abstract: According to one embodiment, a pattern formation method is disclosed. The method includes forming a plurality of regions on a foundation and the plurality of the regions correspond to different pattern sizes. The method includes separating each of a plurality of block copolymers from another one of the plurality of the block copolymers and segregating the each of the plurality of the block copolymers into a corresponding one of the regions. The method includes performing a phase separation of the each of the block copolymers of each of the regions. The method includes selectively removing a designated phase of each of the phase-separated block copolymers to form a pattern of the each of the block copolymers and the pattern has a different pattern size for the each of the regions.Type: GrantFiled: August 3, 2010Date of Patent: June 10, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kentaro Matsunaga, Tomoya Oori, Eishi Shiobara, Yukiko Sato, Yoshihisa Kawamura
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Publication number: 20140151326Abstract: The present invention provides a light-transmitting metal electrode including a substrate and a metal electrode layer having plural openings. The metal electrode layer also has such a continuous metal part that any pair of point-positions in the part is continuously connected without breaks. The openings in the metal electrode layer are periodically arranged to form plural microdomains. The plural microdomains are so placed that the in-plane arranging directions thereof are oriented independently of each other. The thickness of the metal electrode layer is in the range of 10 to 200 nm.Type: ApplicationFiled: February 6, 2014Publication date: June 5, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Eishi Tsutsumi, Tsutomu Nakanishi, Akira Fujimoto, Koji Asakawa
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Patent number: 8742468Abstract: Systems, methods and apparatus are provided through which in some embodiments a mass spectrometer micro-leak includes a number of channels fabricated by semiconductor processing tools and that includes a number of inlet holes that provide access to the channels.Type: GrantFiled: September 23, 2010Date of Patent: June 3, 2014Assignee: The United States of America as represented by the Administrator of the National Aeronautics Space AdministrationInventors: Dan N. Harpold, Hasso B. Niemann, Brian G. Jamieson, Bernard A. Lynch
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Publication number: 20140147073Abstract: An electro-optic modulator includes a substrate and a Y-shaped waveguide. The substrate has a top surface. The Y-shaped waveguide is formed in the top surface and includes a non-modulated branch and a modulated branch. The substrate defines two grooves in the top surface, separating the non-modulated branch and the modulated branch.Type: ApplicationFiled: January 9, 2013Publication date: May 29, 2014Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: HSIN-SHUN HUANG
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Publication number: 20140144690Abstract: The invention concerns the forming of a microelectronic device comprising a substrate containing at least one conductive pad, the said pad being provided with a bottom surface resting on the substrate and an upper surface opposite said bottom surface, the said upper surface of said pad having a stack applied thereto formed of a conductive layer and a protective dielectric layer comprising an opening called first opening facing said pad and exposing the said conductive layer, at least one insulating block (120a, 120b) being arranged on a peripheral region of said upper surface of said pad, the said insulating block (120a, 120b) having a cross-section forming a closed contour and comprising an opening called second opening, a conductive pillar (130a, 130b) being located in the centre of said contour in the said second opening.Type: ApplicationFiled: November 26, 2013Publication date: May 29, 2014Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALTInventor: Gabriel Pares
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Patent number: 8734659Abstract: A process for etching a silicon-containing substrate to form structures is provided. In the process, a metal is deposited and patterned onto a silicon-containing substrate (commonly one with a resistivity above 1-10 ohm-cm) in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. The metallized substrate is submerged into an etchant aqueous solution comprising about 4 to about 49 weight percent HF and an oxidizing agent such as about 0.5 to about 30 weight percent H2O2, thus producing a metallized substrate with one or more trenches. A second silicon etch is optionally employed to remove nanowires inside the one or more trenches.Type: GrantFiled: October 9, 2009Date of Patent: May 27, 2014Assignee: Bandgap Engineering Inc.Inventors: Brent A. Buchine, Faris Modawar, Marcie R. Black
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Publication number: 20140131307Abstract: An embodiment of the invention generally relates to a method of converting a commercial off-the-shelf electrical lead to a rugged off-the-shelf electrical lead by laser machining a portion of the electrical lead. The method includes ablating material from the electrical lead of the commercial off-the-shelf component to reduce the moment of inertia or increase the flexibility of the electrical lead.Type: ApplicationFiled: July 8, 2013Publication date: May 15, 2014Inventors: Deepak Keshav Pai, Melvin Eric Graf
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Publication number: 20140125193Abstract: A sensor assembly including one or more capacitive micromachined ultrasonic transducer (CMUT) microarray modules which are provided with a number of individual transducers. The microarray modules are arranged to simulate or orient individual transducers in a hyperbolic paraboloid geometry. The transducers/sensor are arranged in a rectangular or square matrix and are activatable individually, selectively or collectively to emit and received reflected beam signals at a frequency of between about 100 to 170 kHz.Type: ApplicationFiled: March 14, 2013Publication date: May 8, 2014Applicant: UNIVERSITY OF WINDSORInventor: Sazzadur CHOWDHURY
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Patent number: 8715514Abstract: Provided are a micro-electromechanical systems (MEMS) microphone and a method of manufacturing the same. A manufacturing process is simplified compared to a conventional art using both upper and lower substrate processes. Since defects which may occur during manufacturing are reduced due to the simplified manufacturing process, the manufacturing throughput is improved, and since durability of the MEMS microphone is improved, system stability against the external environment is improved.Type: GrantFiled: March 29, 2012Date of Patent: May 6, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Jae Woo Lee, Kang Ho Park, Jong Dae Kim
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Patent number: 8709266Abstract: A method of manufacturing a substrate for a liquid discharge head having a supply port passing through a silicon substrate provided with an energy-generating element generating the energy used to discharge a liquid and allowing liquid to be supplied to the energy-generating element, includes preparing a silicon substrate in which a first etching mask having a first opening is provided on a first face, and a second etching mask having a second opening is provided on a second face that is the rear face of the first face; forming a first recess towards the second face from the first face within the first opening, and forming a second recess towards the first face from the second face within in the second opening; and performing crystalline anisotropic etching using the first and second etching masks as masks from both of the first and second faces, to form the supply port.Type: GrantFiled: March 10, 2010Date of Patent: April 29, 2014Assignee: Canon Kabushiki KaishaInventors: Satoshi Kokubo, Masahiko Kubota
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Publication number: 20140111729Abstract: The present invention provides a COF base tape. The COF base tape includes: a connected lead being configured to connect with a connected terminal of a liquid crystal glass; an alignment mark being set on the two sides of the connected lead being configured to align with a mark of the connected terminal, an area of the alignment mark thereof being light transparency. The present invention also provides a method for manufacturing the COF base tape and liquid crystal display module. The embodiment of the invention of a COF base tape and manufacturing method thereof and liquid crystal display module including the same enhances the strength of the COF base tape edge and raises the accurate alignment and operationally of the COF base tap connected with liquid glass. The present invention can save the material and reduce the cost of the art.Type: ApplicationFiled: October 31, 2012Publication date: April 24, 2014Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd.Inventors: Chengwen Que, Dehua Li
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Publication number: 20140113386Abstract: Embodiments of the disclosure are directed to a device for molecule sensing. In some embodiments, the device includes a first electrode separated from a second electrode by a dielectric layer. The first electrode comprises a large area electrode and the second electrode comprises a small area electrode. At least one opening (e.g., trench) cut or otherwise created into the dielectric layer exposes a tunnel junction therebetween whereby target molecules in solution can bind across the tunnel junction.Type: ApplicationFiled: October 10, 2013Publication date: April 24, 2014Applicant: ARIZONA BOARD OF REGENTS, acting for and on behalf of ARIZONA STATE UNIVERSITYInventors: Brett Gyarfas, Stuart Lindsay, Pei Pang
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Publication number: 20140106119Abstract: There is provided a pattern forming method for forming hole patterns in a substrate, comprising pattern forming steps each including, in order, the steps (1) to (6): (1) forming a resist film on the substrate by using a chemical amplification resist composition containing (A) a resin capable of increasing the polarity by the action of an acid to decrease the solubility for an organic solvent-containing developer and (B) a compound capable of generating an acid upon irradiation with an actinic ray or radiation; (2) exposing the resist film to form a first line-and-space latent image; (3) exposing the resist film to form a second line-and-space latent image; (4) developing the resist film by using an organic solvent-containing developer to form a hole pattern group in the resist film; (5) applying an etching treatment to the substrate with the resist film; and (6) removing the resist film.Type: ApplicationFiled: December 16, 2013Publication date: April 17, 2014Applicant: FUJIFILM CorporationInventor: Ryosuke UEBA
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Patent number: 8696917Abstract: Methods for fabricating analyte sensor components using IC- or MEMs-based fabrication techniques and sensors prepared therefrom. Fabrication of the analyte sensor component comprises providing an inorganic substrate having deposited thereon a release layer, a first flexible dielectric layer and a second flexible dielectric layer insulating there between electrodes, contact pads and traces connecting the electrodes and the contact pads of a plurality of sensors. Openings are provided in one of the dielectric layers over one or more of the electrodes to receive an analyte sensing membrane for the detection of an analyte of interest and for electrical connection with external electronics. The plurality of fabricated sensor components are lifted off the inorganic substrate.Type: GrantFiled: February 3, 2010Date of Patent: April 15, 2014Assignee: Edwards Lifesciences CorporationInventors: James R. Petisce, David Zhou, Mena Valiket
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Publication number: 20140076843Abstract: A method of fabricating an In-Plane Switching (IPS) screen electrode is disclosed. In the method, a first ITO layer is etched, and the etched first ITO layer is annealed. Subsequently, a second ITO layer is etched, and the etched first ITO layer and the etched second ITO layer are concurrently annealed. With this method, the etched first ITO layer is annealed after the first ITO layer is etched, subsequent etching of the second ITO layer will have no influence upon the annealed first ITO layer, thus making it possible to ensure the line widths of the two ITO layers and a spacing between the respective ITO layers to thereby effectively avoid the problem of a short circuit due to a too small spacing between the respective ITO layers.Type: ApplicationFiled: October 31, 2013Publication date: March 20, 2014Applicant: Shanghai AVIC Optoelectronics Co., Ltd.Inventor: Yanfeng LIANG
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Patent number: 8668835Abstract: A multi-step etch process wherein elliptical via openings and trench openings are formed in a dielectric layer includes supporting a multi-layer film stack on a temperature controlled electrostatic chuck in a plasma etch reactor. The multi-layer film stack has a dielectric layer and a patterned metal hard mask layer above the dielectric layer. An etchant gas is supplied to the plasma etch reactor. The etchant gas is energized into a plasma state, and via openings in a photo resist are transferred into a planarization layer and then into elliptical portions of the trench openings in a patterned hard mask layer while maintaining the chuck at a temperature of about 30 to 50° C. The elliptical openings are extended into a lower layer of the hard mask and into an underlying dielectric layer while maintaining the chuck at a temperature of 20° C. or below.Type: GrantFiled: January 23, 2013Date of Patent: March 11, 2014Assignee: Lam Research CorporationInventors: Ananth Indrakanti, Bhaskar Nagabhirava
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Patent number: 8668834Abstract: A method of protecting a mold having at least one substantially planar surface provided with a plurality of mold cavities includes inserting a plurality of mandrels into respective ones of the plurality of mold cavities, depositing a layer of mold protection material onto the at least one substantially planar surface and the plurality of mandrels, and removing the plurality of mandrels from the mold substrate.Type: GrantFiled: April 23, 2012Date of Patent: March 11, 2014Assignee: International Business Machines CorporationsInventors: Bradley P. Jones, Sarah H. Knickerbocker, Richard P. Volant
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Patent number: 8667675Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.Type: GrantFiled: August 12, 2008Date of Patent: March 11, 2014Assignee: Sanmina Sci CorporationInventor: George Dudnikov, Jr.
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Patent number: 8668833Abstract: A method of forming a discrete nanostructured element at one or more predetermined locations on a substrate is presented. The method includes forming a mask member over the substrate. A window is formed in the mask member at each of one or more locations at which it is required to form the nanostructured element thereby to expose a portion of a surface of the substrate. A portion of the substrate exposed by the window at the one or more locations is removed to form one or more recesses in the substrate. The method further includes forming a layer of a nanostructure medium over a surface of the recess and annealing the structure thereby to form the nanostructured element in each of the one or more recesses. The nanostructured element includes a portion of the nanostructure medium and has an external dimension along at least two substantially orthogonal directions of less than substantially 100 nm.Type: GrantFiled: May 21, 2008Date of Patent: March 11, 2014Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., National University of SingaporeInventors: Han Guan Chew, Fei Zheng, Wee Kiong Choi, Tze Haw Liew
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Publication number: 20140054261Abstract: A method of fabricating a micro-device having micro-features on glass is presented. The method includes the steps of preparing a first glass substrate, fabricating a metallic pattern on the first glass substrate, preparing a second glass substrate and providing one or more apertures on the second glass substrate, heating the first glass substrate and the second glass substrate with a controlled temperature raise, bonding the first glass substrate and the second glass substrate by applying pressure to form a bonded substrate, wherein the metallic pattern is embedded within the bonded substrate, cooling the bonded substrate with a controlled temperature drop and thereafter maintaining the bonded substrate at a temperature suitable for etching, etching the metallic pattern within the bonded substrate, wherein an etchant has access to the metallic pattern via the apertures, forming a void within the bonded substrate, wherein the void comprises micro-features.Type: ApplicationFiled: September 29, 2013Publication date: February 27, 2014Inventor: Viswanadam Gautham
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Patent number: 8652337Abstract: A mechanism is provided for fabricating nanochannels for a nanodevice. Insulating film is deposited on a substrate. A nanowire is patterned on the film. Insulating material is deposited on the nanowire and film. A first circular hole is formed in the insulating material as an inlet, over a first tip of the nanowire to expose the first tip. A second circular hole is formed as an outlet, over a second tip of the nanowire opposite the first tip to expose the second tip. A nanochannel connects the first and second holes by etching away the nanowire via an etchant in the first and the second holes. A first reservoir is attached over the first hole in connection with the nanochannel at a previous location of the first tip. A second reservoir is attached over the second hole in connection with the nanochannel at a previous location of the second tip.Type: GrantFiled: August 20, 2013Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Binquan Luan, Gustavo A. Stolovitzky, Chao Wang, Deqiang Wang
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Patent number: 8647517Abstract: A producing method of a suspension board with circuit includes simultaneously forming a conductive pattern formed on an insulating layer formed on a metal supporting board and having a terminal portion for connecting to an electronic component, and a mark formed on the metal supporting board, or on the insulating layer and having an opening for forming a reference hole for mounting the electronic component, and forming the reference hole by etching the metal supporting board disposed in the opening of the mark, or the insulating layer and the metal supporting board each disposed in the opening of the mark.Type: GrantFiled: July 8, 2008Date of Patent: February 11, 2014Assignee: Nitto Denko CorporationInventors: Takahiko Yokai, Yasunari Ooyabu, Toshiki Naito
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Publication number: 20140033833Abstract: A device for measuring forces and a method of making the same is disclosed. The device comprises a boss structure within a diaphragm cavity, wherein the boss structure has substantially parallel sidewalls. One or more sensors are installed proximate to the diaphragm to sense flexure in the diaphragm, which is controlled by the boss structure.Type: ApplicationFiled: August 6, 2012Publication date: February 6, 2014Applicant: General Electric CompanyInventors: Sisira Kankanam Gamage, Naresh Venkata Mantravadi, Calin Victor Miclaus
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Publication number: 20140036345Abstract: The current disclosure shows how to make a fast switching array of mirrors for projection displays. Because the mirror does not have a via in the middle connecting to the underlying spring support, there is an improved contrast ratio that results from not having light scatter off the legs or vias like existing technologies. Because there are no supporting contacts, the mirror can be made smaller making smaller pixels that can be used to make higher density displays. In addition, because there is not restoring force from any supporting spring support, the mirror stays in place facing one or other direction due to adhesion. This means there is no need to use a voltage to hold the mirror in position. This means that less power is required to run the display.Type: ApplicationFiled: July 15, 2013Publication date: February 6, 2014Applicant: CAVENDISH KINETICS INC.Inventors: Charles Gordon SMITH, Richard L. KNIPE
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Patent number: 8641913Abstract: A method includes applying a final etch-resistant material to an in-process substrate so that the final etch-resistant material at least partially covers first microcontact portions integral with the substrate and projecting upwardly from a surface of the substrate, and etching the surface of the substrate so as to leave second microcontact portions below the first microcontact portions and integral therewith, the final etch-resistant material at least partially protecting the first microcontact portions from etching during the further etching step. A microelectronic unit includes a substrate, and a plurality of microcontacts projecting in a vertical direction from the substrate, each microcontact including a base region adjacent the substrate and a tip region remote from the substrate, each microcontact having a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.Type: GrantFiled: March 13, 2007Date of Patent: February 4, 2014Assignee: Tessera, Inc.Inventors: Belgacem Haba, Yoichi Kubota, Teck-Gyu Kang, Jae M. Park
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Patent number: 8641914Abstract: Methods for fabricating arrays of nanoscaled alternating lamellae or cylinders in a polymer matrix having improved long range order utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.Type: GrantFiled: May 17, 2012Date of Patent: February 4, 2014Assignee: Micron Technology, Inc.Inventor: Jennifer Kahl Regner
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Publication number: 20140021163Abstract: The present invention relates to graphene windows and methods for making same. One method comprises selecting a high purity metal foil, growing a layer of graphene on a first face of the metal foil, patterning the second face of the graphene-modified foil with a polymer, wherein the second face of the graphene-modified foil has an exposed region and etching the second face of the graphene-modified foil in the exposed region until exposing the first layer of graphene.Type: ApplicationFiled: December 21, 2011Publication date: January 23, 2014Applicant: CleanEnergy Labs, LLCInventors: William Neil Everett, Joseph F. Pinkerton, William Martin Lackowski
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Publication number: 20140021164Abstract: A method for manufacturing a multilayer rigid flexible printed circuit board that includes a flexible region including a flexible film having a circuit pattern formed on one or both surfaces thereof and a laser blocking layer formed on the circuit pattern; and a rigid region formed adjacent to the flexible region and including a plurality of pattern layers on one or both surfaces of extended portions extended to both sides of the flexible film of the flexible region.Type: ApplicationFiled: September 19, 2013Publication date: January 23, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Yang Je LEE, Dek Gin YANG, Dong Gi AN, Jae Ho SHIN
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Publication number: 20140021165Abstract: The present invention relates to graphene windows and methods for making same. The present invention further relates to devices that include such graphene windows.Type: ApplicationFiled: September 27, 2013Publication date: January 23, 2014Inventors: WILLIAM NEIL EVERETT, JOSEPH F. PINKERTON, WILLIAM MARTIN LACKOWSKI
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Publication number: 20140001149Abstract: For a cross slit structure that contains a nanopore, a layer is produced including a first spacer that penetrates through the layer. A subsequent layer over, and in direct contact with, the layer is also produced. The subsequent layer includes a second spacer penetrating through the subsequent layer. The first spacer and the second spacer are selectively etched away, creating a first slit and a second slit. Respective projections of these slits are crossing one another at an angle. At such a crossing an opening is formed which provides for fluid connectivity through the two layers.Type: ApplicationFiled: June 28, 2012Publication date: January 2, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jingwei Bai, Stefan Harrer, Stanislav Polonsky, Stephen M. Rossnagel
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Patent number: 8617960Abstract: A capacitive microphone transducer integrated into an integrated circuit includes a fixed plate and a membrane formed in or above an interconnect region of the integrated circuit. A process of forming an integrated circuit containing a capacitive microphone transducer includes etching access trenches through the fixed plate to a region defined for the back cavity, filling the access trenches with a sacrificial material, and removing a portion of the sacrificial material from a back side of the integrated circuit.Type: GrantFiled: December 16, 2010Date of Patent: December 31, 2013Assignee: Texas Instruments IncorporatedInventors: Marie Denison, Brian E. Goodlin, Wei-Yan Shih, Lance W. Barron
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Patent number: 8617988Abstract: A method of etching through-substrate vias comprising depositing a layer of embossable material on a first side and a second side of a thin-film stack, the thin-film stack including a base substrate, embossing the embossable material deposited on the first side and the second side of the thin-film stack with a pattern, hardening the embossable material, and etching the first and second sides of the thin-film stack, the etching of the second side of the thin-film stack forming vias through the base substrate.Type: GrantFiled: June 6, 2011Date of Patent: December 31, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventor: Devin Alexander Mourey
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Publication number: 20130335804Abstract: A method of manufacturing an electrowetting display device includes a preliminary partition wall pattern formed on a lower substrate on which a pixel electrode of an oxide series and an insulation layer are formed. The preliminary partition wall pattern is disposed along a boundary of the pixel electrode. A water-repellent layer including a self-assembled monolayer having a hydrophobic property is formed on the lower substrate. A portion of the preliminary partition wall pattern and the water-repellent layer formed on the preliminary partition wall pattern are removed to form a partition wall pattern on the insulation layer and to form a water-repellent pattern on the pixel electrode and the insulation layer between partition walls of the partition wall patterns. A fluid layer is formed on the lower substrate on which the water-repellent pattern is formed. The lower substrate and an upper substrate are combined with each other.Type: ApplicationFiled: November 23, 2012Publication date: December 19, 2013Applicant: SAMSUNG DISPLAY CO., LTD.Inventors: Woo-Yong SUNG, A-Ram Lee, Tae-Gyun Kim, Tae-Woon Cha, Sang-Gun Choi
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Patent number: 8609221Abstract: Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.Type: GrantFiled: July 12, 2010Date of Patent: December 17, 2013Assignee: Micron Technology, Inc.Inventors: Dan B. Millward, Donald Westmoreland, Gurtej Sandhu
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Publication number: 20130319972Abstract: Polymer materials make useful materials as electrode array bodies for neural stimulation. They are particularly useful for retinal stimulation to create artificial vision. Regardless of which polymer is used, the basic construction method is the same. A layer of polymer is laid down. A layer of metal is applied to the polymer and patterned to create electrodes and leads for those electrodes. A second layer of polymer is applied over the metal layer and patterned to leave openings for the electrodes, or openings are created later by means such as laser ablation. Hence the array and its supply cable are formed of a single body.Type: ApplicationFiled: August 8, 2013Publication date: December 5, 2013Inventors: Robert J. Greenberg, Jerry Ok, Jordan Matthew Neysmith, Brian V. Mech, Neil Hamilton Talbot
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Publication number: 20130323470Abstract: A conductive structure for a panel is formed on a plate and includes a first metal layer, a nitride layer, and a second metal layer. The first metal layer is located on the plate and has a first side surface and a lower surface connected to the first side surface, while the lower surface makes contact with the plate. The first metal layer contains molybdenum. The nitride layer is located on the first metal layer and has a second side surface. The nitride layer contains molybdenum. The second metal layer is located on the nitride layer and has a third side surface. The second side surface is adjacent to the first side surface and the third side surface, to form an inclined surface. An included angle between the inclined surface and the lower surface is between 20 degrees and 75 degrees.Type: ApplicationFiled: May 10, 2013Publication date: December 5, 2013Applicant: INNOLUX CORPORATIONInventors: HUEI-YING CHEN, CHIA-CHI HO
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Publication number: 20130319736Abstract: A multilayer electronic support structure comprising at least one pair of adjacent feature layers extending in an X-Y plane that are separated by a via layer; said via layer comprising a dielectric material that is sandwiched between the two adjacent feature layers and at least one one non-cylindrical via post that couples said pair of adjacent feature layers through the dielectric material in a Z direction perpendicular to the X-Y plane; wherein said at least one non-cylindrical via post is characterized by having a long dimension in the X-Y plane that is at least 3 times as long as a short dimension in the X-Y plane.Type: ApplicationFiled: May 29, 2012Publication date: December 5, 2013Inventor: DROR HURWITZ
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Publication number: 20130319748Abstract: A wired circuit board includes an insulating layer to be formed with an opening extending therethrough in a thickness direction of the wired circuit board, a conductive layer formed on one surface of the insulating layer in the thickness direction and including a one-side terminal portion, an other-side terminal portion formed on the other surface of the insulating layer in the thickness direction, disposed so as to overlap the opening and the one-side terminal portion when projected in the thickness direction, and used to be connected to an electronic element via a conductive adhesive, and a conductive portion filling the opening to provide electrical conduction between the one-side terminal portion and the other-side terminal portion.Type: ApplicationFiled: May 8, 2013Publication date: December 5, 2013Applicant: NITTO DENKO CORPORATIONInventors: Jun ISHII, Saori KANEZAKI