Abstract: Methods, systems and apparatuses are disclosed for making and post-processing a 3-D printed object for laminate-forming tooling, and components made using post-processed 3-D printed laminate-forming tooling.

Abstract: The ampholytic surfactants show the nature of anionic surfactants in an alkaline region and the nature of cationic surfactants in an acidic region. As described below, the pretreatment solution of the present invention may preferably indicate alkalinity of pH 8.5 or higher, and therefore, it exhibits the nature of cationic surfactants by the use of ampholytic surfactants. As the ampholytic surfactants, those disclosed in JP 2011-228517 A can be used.

Abstract: An advanced metal conductor structure is described. An integrated circuit device including a substrate having a patterned dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed over the set of features in the patterned dielectric. A metal layer fills a first portion of the set of features and is disposed over the adhesion promoting layer. A ruthenium layer is disposed over the metal layer. A cobalt layer is disposed over the ruthenium layer fills a second portion of the set of features. The cobalt layer is formed using a physical vapor deposition process.

Abstract: Some novel features pertain to an inductor structure that includes a first inductor winding, a second inductor winding and a filler. The first inductor winding includes an electrically conductive material. The second inductor winding includes an electrically conductive material. The filler is laterally located between the first inductor winding and the second inductor winding. The filler is configured to provide structural coupling of the first and second inductor windings. In some implementations, the first inductor winding is laterally co-planar to the second inductor winding. In some implementations, the first inductor winding has a first spiral shape and the second inductor winding has a second spiral shape. In some implementations, the first inductor winding and the second inductor winding have an elongated circular shape. In some implementations, the filler is an epoxy.

Abstract: This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.

Abstract: A method to create a media display device viewing area in a mirror platform includes isolating the media display device viewing area from the rest of a glass layer of the mirror platform. The glass layer has a backing layer and an optional paint layer. A solvent is applied to remove optional protective paint, if present, from a backing layer within the media display device viewing area. The protective paint, if present, is scraped from the media display device viewing area. An etching solution is applied to the media display device viewing area to remove the backing layer. The media display device viewing area is rinsed.

Abstract: Display substrates and display devices with reduced electrical resistance are disclosed. One inventive aspect includes a switching device, a first wiring and a second wiring. The switching device includes a first semiconductor layer, first and second gate insulation layers, a source electrode and a drain electrode. The source and drain electrodes are formed to electrically connect, through the first and second gate insulation layers, to the first semiconductor layer. The second wiring is formed on the second gate insulation layer and electrically connected to the first wiring.

Abstract: A sensor device for integration in an electrical circuit, including a support layer (12?), which is formed with a release layer; at least one flexible insulating layer (14?, 32), which is made using a printing method; and at least one flexible electrical conductor structure (20?, 34), which is applied with a printing method onto the insulating layer (14). The insulating layer (14?, 32) and the conductor structure (20?, 34) form a flexible unit, which is removable without damage from the support layer (12?).

Abstract: This invention provides an electronic device with improved reliability. The electronic device has a wiring board with a back-surface ground pattern formed at the back surface of the board. The back-surface ground pattern is provided with a notch overlapping a region of an upper wiring layer at which a board member is exposed and which is encircled by a wide pattern, the notch permitting the release of water vapor from the region.

Abstract: The stack manufacturing apparatus includes a first supporting body supply unit which is configured to intermittently unroll a roll sheet-shaped first supporting body and includes one of a pair of tension applying devices capable of applying tension to the unrolled first supporting body; a first adhesive layer formation unit configured to form a first adhesive layer over the first supporting body while the first supporting body supply unit suspends unrolling of the first supporting body; a first bonding unit configured to bond the first supporting body and a sheet-shaped member using the first adhesive layer; and a control unit which is configured to hold an end portion of the first supporting body and includes the other of the pair of tension applying devices.

Abstract: Semiconductor structures include a patterned interlayer dielectric overlaying a semiconductor substrate. The interlayer dielectric includes a first dielectric layer and at least one additional dielectric layer disposed on the first dielectric layer, wherein the patterned interlayer dielectric comprises at least one opening extending through the interlayer dielectric to the semiconductor substrate. Chemically enriched regions including ions of Si, P, B, N, O and combinations thereof are disposed in surfaces of the first dielectric layer and the at least one dielectric layer defined by the at least one opening. Also described are methods of for forming an interconnect structure in a semiconductor structure.

Abstract: A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect level. The semiconductor interconnect structure has a segment of dielectric capping material that is in contact with the bottom of the first portion, which separates, in part, the upper interconnect level from a lower interconnect level. The second portion is in electrical contact with the first portion.

Abstract: A multilayer electrical device, such as a printed circuit board, having a tooth structure including a metal layer set in a dielectric. The device includes a base; a conductive layer adjacent to the base; a dielectric material adjacent to conductive layer; a tooth structure including a metal layer set in the dielectric material to join the dielectric material to the metal layer; and wherein the metal layer forms a portion of circuitry in a circuit board having multiple layers of circuitry.

Abstract: In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed.

Abstract: Methods of forming a microelectronic structure are described. Those methods comprise forming a stress compensation layer on a substrate, forming at least one opening within the stress compensation layer, and forming an interconnect paste within the at least one opening.

Abstract: Embodiments of the invention relates to adding test access to a back-drilled vertical access interconnect (VIA) of a printed circuit board (PCB). A VIA is either formed or provided as an opening through layers of the PCB. The VIA is countersunk from one of the two openings to the PCB prior to plating to form a surface that can be used as a test target. The countersunk VIA is subject to plating so that the interior walls and surfaces of the VIA are covered with a conductive material. The plating is removed along the walls of the countersunk section of the VIA, so that the plating remains on the shoulders and the non-countersunk section of the VIA with the shoulder in communication with a trace internal to the PCB. The back-drilled VIA with the plating configuration provides an internal conducting surface for contact while mitigating interference associated with a VIA stub.

Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

Abstract: A copper layer structure includes a first copper layer, a second copper layer and a carbon-rich copper layer. The second copper layer is disposed over the first copper layer. The carbon-rich copper layer is sandwiched between the first copper layer and the second copper layer. A carbon concentration of the carbon-rich copper layer is greater than a carbon concentration of the first copper layer and a carbon concentration of the second copper layer.

Abstract: An advanced metal conductor structure is described. An integrated circuit device including a substrate having a patterned dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed over the set of features in the patterned dielectric. A metal layer fills a first portion of the set of features and is disposed over the adhesion promoting layer. A ruthenium layer is disposed over the metal layer. A cobalt layer is disposed over the ruthenium layer fills a second portion of the set of features. The cobalt layer is formed using a physical vapor deposition process.

Abstract: The present disclosure relates, according to some embodiments, to the fabrication of a flexible circuit board, which includes forming a base layer comprising polyimide, forming a polyimide layer on the base layer, the polyimide layer having a first surface and a second surface opposite to each other, the first surface being peelably adhered in contact with the base layer, forming a metal layer on the second surface of the polyimide layer, and peeling the base layer from the polyimide layer with the metal layer remaining on the second surface of the polyimide layer.

Abstract: Disclosed are pre-wetting apparatus designs and methods. In some embodiments, a pre-wetting apparatus includes a degasser, a process chamber, and a controller. The process chamber includes a wafer holder configured to hold a wafer substrate, a vacuum port configured to allow formation of a subatmospheric pressure in the process chamber, and a fluid inlet coupled to the degasser and configured to deliver a degassed pre-wetting fluid onto the wafer substrate at a velocity of at least about 7 meters per second whereby particles on the wafer substrate are dislodged and at a flow rate whereby dislodged particles are removed from the wafer substrate. The controller includes program instructions for forming a wetting layer on the wafer substrate in the process chamber by contacting the wafer substrate with the degassed pre-wetting fluid admitted through the fluid inlet at a flow rate of at least about 0.4 liters per minute.

Abstract: A method for fabricating printed electronics includes printing a trace of an electrical component on a first substrate to form a first layer. The method further includes printing a trace of an electrical component on at least one additional substrate to form at least one additional layer. The first layer is stacked with the at least one additional layer to create an assembled electrical device. At least one of the layers is modified after printing.

Abstract: A semiconductor apparatus with an optoelectronic device and a further device is disclosed. Embodiments of the invention provide a semiconductor apparatus with an optoelectronic device and a further device, wherein the optoelectronic device and the further device are interconnected to one another in parallel when the semiconductor apparatus is in operation, wherein the optoelectronic device is connected to a first contact and a second contact, the first contact and the second contact being configured to externally contact the semiconductor apparatus, and wherein the further device is connected with at least one further contact of the semiconductor apparatus.

Abstract: Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a method for processing a semiconductor substrate includes forming an aperture in a semiconductor substrate and through a dielectric on the semiconductor substrate. The aperture has a first end open at the dielectric and a second end opposite the first end. The method can also include forming a plurality of depressions in the dielectric, and simultaneously depositing a conductive material into the aperture and at least some of the depressions.

Abstract: A method for manufacturing metal interconnects. The method includes following steps. A substrate including a dielectric layer formed thereon is provided, and a plurality of trenches are formed in the dielectric layer. Next, a seed layer is formed in the trenches and on the dielectric layer and followed by masking regions of the seed layer to define a plurality of masked regions and a plurality of exposed regions for the seed layer. Subsequently, a surface treatment is performed to the exposed regions of the seed layer to form a plurality of rough surfaces on the exposed regions of the seed layer. Then, a metal layer is formed on the substrate, and the trenches are filled up with the metal layer.

Abstract: A semi-finished product for the production of a printed circuit board having a plurality of alternately arranged insulating layers and conductive layers and at least one hard gold-plated edge connector is characterized by the hard gold-plated edge connector being arranged on an inner conductive layer of the semi-finished product and being fully covered by at least one group of an insulating layer and a conductive layer.

Abstract: A surgical locator circuit identifies a surgical target such as a kidney stone by disposing an emitter such as a magnetic source behind or adjacent the surgical target, and employing the circuit to identify an axis to the emitter, thus defining an axis or path to the surgical target. An array of sensors arranged in an equidistant, coplanar arrangement each senses a signal indicative of a distance to the emitter. A magneto resistor sensor generates a variable resistance is responsive to the distance to a magnetic coil emitting a magnetic field. An equal signal from each of the coplanar sensors indicates positioning on an axis passing through a point central to the sensors and orthogonal to the plane. A fixed element and signal conditioner augments and normalizes the signal received from each of the sensors to accommodate subtle differences in magneto resistive response among the plurality of sensors.

Abstract: A method for irradiating semiconductor material is provided which includes selecting a region of a semiconductor layer surface, irradiating the region with an excimer laser which has a beam spot size, and adjusting the beam spot size to match the selected region size. Further, an apparatus for irradiating semiconductor material is provided. The apparatus includes an excimer laser for irradiating a selected region of a semiconductor layer surface, the laser has a laser beam spot size, and a system for adjusting the laser beam spot size to match the selected region size.

Abstract: Provided is an optical waveguide photosensitive resin composition containing a photocurable resin and a photopolymerization initiator, in which the photopolymerization initiator is a specific photoacid generator represented by the general formula (1). Accordingly, when a core layer is formed by using the optical waveguide photosensitive resin composition as a material for forming an optical waveguide, especially a core layer-forming material, excellent high transparency (low loss effect) is obtained. In the formula (1), R1 and R2 each represent hydrogen or an alkyl group having 1 to 15 carbon atoms, and may be identical to or different from each other.

Abstract: The disclosed embodiments relate to methods and apparatus for immersing a substrate in electrolyte in an electroplating cell under sub-atmospheric conditions to reduce or eliminate the formation/trapping of bubbles as the substrate is immersed. Various electrolyte recirculation loops are disclosed to provide electrolyte to the plating cell. The recirculation loops may include pumps, degassers, sensors, valves, etc. The disclosed embodiments allow a substrate to be immersed quickly, greatly reducing the issues related to bubble formation and uneven plating times during electroplating.

Abstract: Provided are semiconductor devices and methods of fabricating the same. The device may include a substrate including a first surface and a second surface opposing each other, a through-silicon-via (TSV) electrode provided in a via hole that may be formed to penetrate the substrate, and an integrated circuit provided adjacent to the through electrode on the first surface. The through electrode includes a metal layer filling a portion of the via hole and an alloy layer filling a remaining portion of the via hole. The alloy layer contains at least two metallic elements, one of which may be the same as that contained in the metal layer, and the other of which may be different from that contained in the metal layer.

Abstract: A method of forming a semiconductor device is provided. Metallic interconnects are formed in a dielectric layer of the semiconductor device. A hard mask is used to avoid usual problems faced by manufacturers, such as possibility of bridging different conductive elements and via patterning problems when there are overlays between vias and trenches. The hard mask is etched multiple times to extend via landing windows, while keeping distance between the conductive elements to avoid the bridging problem.

Abstract: A printed wiring board includes an inner conductive-circuit layer, an insulation layer structure including a first insulation layer laminated on inner conductive-circuit layer and a second insulation layer laminated on the first insulation layer, and an outermost conductive-circuit layer laminated on the insulation layer structure and including connection portions such that the connection portions are positioned to mount a component on the insulation layer structure. The second insulation layer is interposed between the first insulation layer and the outermost conductive-circuit layer and has a thickness which is smaller than a thickness of the first insulation layer such that an outer surface of the second insulation layer on an outermost conductive-circuit-layer side is flatter than an inner surface of the second insulation layer on a first insulation-layer side.

Abstract: Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate including a plurality of build-up layers, such as bumpless build-up layer (BBUL). In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.

Abstract: A method for forming a printed circuit board includes providing a substrate including a first device region, a second device region and a dicing channel region between the first device region and the second device region. A first circuit is formed on the substrate. An insulating layer is formed on the first circuit and the substrate. At least one build-up circuit is formed on the insulating layer. A photoresist layer is formed on the at least one build-up circuit. An image transferring process is performed to pattern the photoresist layer to form a dam structure in the dicing channel region. A solder mask layer is formed on the at least one build-up circuit. The dam structure is removed to form a trench in the solder mask layer.

Abstract: Integrated circuit devices and method of forming them. The devices include a dielectric barrier layer formed over a copper-containing metal interconnect structure. The dielectric barrier layer inhibits electro-migration of Cu. The dielectric barrier layer includes a metal-containing layer that forms an interface with the interconnect structure. Incorporating metal within the interfacial layer improves adhesion of the dielectric barrier layer to copper lines and the like and provides superior electro-migration resistance over the operating lifetime of the devices.

Abstract: A method of manufacturing a transistor comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material; forming at least one layer of resist material over said regions to form a covering of resist material over said regions; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of conductive material, said first portion separating a second portion of the conductive region from a third portion of the conductive region; removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region; removing said first portion to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion to the third portion of the conductive region; forming a layer of

Abstract: A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric layer. A metal trench is formed with a metal width in the first dielectric layer. A via hole is formed with a via width in the second dielectric layer.

Abstract: A semiconductor apparatus with an optoelectronic device and a further device is disclosed. Embodiments of the invention provide a semiconductor apparatus with an optoelectronic device and a further device, wherein the optoelectronic device and the further device are interconnected to one another in parallel when the semiconductor apparatus is in operation, wherein the optoelectronic device is connected to a first contact and a second contact, the first contact and the second contact being configured to externally contact the semiconductor apparatus, and wherein the further device is connected with at least one further contact of the semiconductor apparatus.

Abstract: A multilayer electrical device, such as a printed circuit board, having a tooth structure including a metal layer set in a dielectric. The device includes a base; a conductive layer adjacent to the base; a dielectric material adjacent to conductive layer; a tooth structure including a metal layer set in the dielectric material to join the dielectric material to the metal layer; and wherein the metal layer forms a portion of circuitry.

Abstract: A ceramic substrate is provided that includes a ceramic substrate main body including a principal surface, a connecting terminal portion disposed on the principal surface of the ceramic substrate main body that is capable of being connected to another component via solder, the connecting terminal portion including a copper layer and a coating metal layer covering a surface of the copper layer; a contact layer of titanium or chromium disposed between the ceramic substrate main body and the connecting terminal portion; and an intermediate layer disposed between the copper layer of the connecting terminal portion and the contact layer, the intermediate layer including one of a titanium-tungsten alloy, a nickel-chromium alloy, tungsten, palladium, and molybdenum. The contact layer and the intermediate layer are set back from a side surface of the copper layer in a substrate plane direction.

Abstract: A computer-implemented structure for optimizing a route for power supply and heat dissipation in a multilayer chip. The method includes: setting a heat conductive thermal value for the multilayer chip by way of density, preparing a substrate that contains silicon where a wiring layer is formed facing the upper surface side of the multilayer chip, setting the power from the wiring layer of the substrate that uses silicon, manipulating the value of the power supply, and manipulating the heat conductive thermal value based on density. Both apparatuses include an organic substrate, a multilayer chip, a substrate containing silicon, a wiring layer, and a heat dissipater, wherein the components are configured to perform the steps of the above method. The method of configuring an apparatus ensures that all the multilayer chips are stored in the concave part of the organic substrate.

Abstract: A dynamic pattern generator (DPG) device and method of making a DPG device are disclosed. The DPG device is used in semiconductor processing tools that require multiple electron-beams, such as direct-write lithography. The device is a self-aligned DPG device that enormously reduces the required tolerances for aligning the various electrode layers, as compared to other design configurations including the non-self-aligned approach and also greatly simplifies the process complexity and cost. A process sequence for both integrated and non-integrated versions of the self-aligned DPG device is described. Additionally, an advanced self-aligned DPG device that eliminates the need for a charge dissipating coating or layer to be used on the device is described. Finally, a fabrication process for the implementation of both integrated and non-integrated versions of the advanced self-aligned DPG device is described.

Abstract: System-in-Packages (SiPs) and methods for producing SiPs are provided. In one embodiment, the above-described SiP fabrication method includes the step or process of forming a through-hole in a core package, the core package containing an electrically-conducive routing feature exposed at a sidewall surface of the through-hole. A leaded component is positioned adjacent the core package such that an elongated lead of the leaded component extends into the through-hole. An electrically-conductive material, such as solder, is then applied into the through hole to electrically couple the elongated lead of the leaded component to the electrically-conductive routing feature of the core package.

Abstract: A multilayer electronic support structure comprising a plurality of layers extending in an X-Y plane consisting of a dielectric material surrounding metal via posts that conduct in a Z direction perpendicular to the X-Y plane, wherein a stacked via structure crossing at least two via layers of the plurality of layers comprises at least two via posts in neighboring via layers wherein the at least two stacked via posts in neighboring layers have different dimensions in the X-Y plane, such that the stacked via structure tapers.

Abstract: A circuit board includes a circuit board plate, a conductive ring, a solder mask and at least one insulating pad. The circuit board plate includes a surface and a conductive through hole passing through the surface and the circuit board plate, wherein the conductive through hole have a conductive layer disposed on a wall thereof. The conductive ring on the surface surrounds an opening of the conductive through hole on the surface and electrically connects to the conductive layer. The solder mask is disposed on the surface. The conductive ring is exposed outside of the solder mask. The insulating pad has a thickness. The first surface of the insulating pad is adapted to contact the solder mask or the surface and sited at periphery of the conductive ring. The second surface of the insulating pad is adapted for spacing a distance between a solder coating tool and the solder mask.

Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

Abstract: A method of producing a printed circuit board includes: forming a metal layer on a support plate; forming a mask layer on the metal layer; forming a pattern plating having a stem as plating up to a level of the mask layer, and a cap as a portion of plating exceeding the mask layer and having an outgrowth lying over the surface of the mask layer; laminating an insulating base on a conductive circuit board constituted by the support plate, the metal layer and the pattern plating to form a circuit board intermediate in which the pattern plating is buried in the base; removing the support plate and the metal layer to form an exposed surface; and mechanically polishing the exposed surface until the stem of the pattern plating is removed, to increase the width of the conductive pattern on the exposed surface.

Abstract: A photomask is manufactured by providing a photomask blank comprising a transparent substrate, a phase shift film, and a light-shielding film, the phase shift film and the light-shielding film including silicon base material layers, a N+O content in the silicon base material layer of the phase shift film differing from that of the light-shielding film, and chlorine dry etching the blank with oxygen-containing chlorine gas in a selected O/Cl ratio for selectively etching away the silicon base material layer of the light-shielding film.

Abstract: An interposer structure including a semiconductor substrate, a plurality of shallow trenches, a plurality of deep trenches and a plurality of metal damascene structures is provided. The semiconductor substrate has a first surface and a second surface opposite to each other. The shallow trenches are formed on the first surface in both of a first area and a second area of the semiconductor substrate and correspondingly a plurality of respective openings are formed on the first surface. The deep trenches extend from at least one of the shallow trenches toward the second surface in the second area and correspondingly a plurality of respective openings are formed on the second surface. The metal damascene structures are filled in both of the shallow trenches and the deep trenches. A manufacturing method for the aforementioned interposer structure is also provided.