Abstract: The present invention relates to a method for fabricating blackened conductive patterns, which includes (i) forming a resist layer on a non-conductive substrate; (ii) forming fine pattern grooves in the resist layer using a laser beam; (iii) forming a mixture layer containing a conductive material and a blackening material in the fine pattern grooves; and (iv) removing the resist layer remained on the non-conductive substrate.

Abstract: To manufacture a thin film compound solar cell which can improve the adhesive property of electrodes even when being provided with a base material, and which prevents the base material from being separated. A cell main body configured by laminating a plurality of compound semiconductor layers is formed on a substrate. A rear surface electrode 7 is formed on the cell main body, and a rear surface film 8 as the base material is formed on the rear surface electrode 7. A reinforcing material 9 is attached on the rear surface film 8. The substrate is separated from the cell main body, and the cell main body is mesa-etched. A surface electrode 13 is formed on a contact layer 3 after the etching. The reinforcing material 9 is separated, and the surface electrode 13 is annealed. The formed thin film compound solar cell is separated into a plurality of solar cell elements.

Abstract: The gravimetric and volumetric efficiency of lithium ion batteries may be increased if higher capacity materials like tin and silicon are substituted for carbon as the lithium-accepting host in the negative electrode of the battery. But both tin and silicon, when fully charged with lithium, undergo expansions of up to 300% and generate appreciable internal stresses. These internal stresses, which will develop on each discharge-charge cycle, may lead to a progressive reduction in battery capacity, also known as battery fade. The effects of the internal stresses may be significantly reduced by partially embedding tin or silicon nanowires in the current collector. Additional benefit may be obtained if a 5 to 50% portion of the nanowire length at its embedded end are coated or masked with a composition which impedes lithium diffusion. Methods for embedding and masking the nanowires are described.

Abstract: A contact structure and assembly and a method for manufacturing the same for a microelectronics device includes first and second electrically conductive contacts being helically shaped. A carrier element is attached to and positioned between the first and second contacts. The first and second contacts are in electrical communication with each other, and the first and second contacts are in a mirror image relationship with each other. A pair of insulating substrates each include electrically conductive members. A contact point on each of the first and second contacts is attached and electrically communicating to respective electrically conductive members such that the first and second electrically conductive contacts between the pair of insulating substrates form an electrically conductive package. A metal layer on the carrier element provides electrical conductivity through a first opening defined by the carrier element between the first and second portions of the helix shaped contact.

Abstract: A printed circuit board and a method of manufacturing the same. In one embodiment, a printed circuit board includes: a core made of a glass material; an insulator surrounding the core; and a via connecting internal circuit layers through the core and the insulator.

Abstract: A method and system for integrated circuit fabrication is disclosed. In an example, the method includes determining a first process parameter of a wafer and a second process parameter of the wafer, the first process parameter and the second process parameter corresponding to different wafer characteristics; determining a variation of a device parameter of the wafer based on the first process parameter and the second process parameter; constructing a model for the device parameter as a function of the first process parameter and the second process parameter based on the determined variation of the device parameter of the wafer; and performing a fabrication process based on the model.

Abstract: An exemplary embodiment of the present invention discloses a method of manufacturing a touch panel, the method including, forming a plurality of sensing cells in a first region of a substrate, forming an insulating interlayer on the plurality of sensing cells, removing at least a portion of the insulating interlayer to form contact holes exposing the plurality of sensing cells, and forming a connection pattern and a transparent conductive pattern on the insulating interlayer simultaneously, wherein the connection pattern is electrically connected to adjacent sensing cells, and the transparent conductive pattern is disposed in a second region of the substrate outside of the first region.

Abstract: A pressure sensitive element is provided. In one embodiment the pressure sensitive element comprises: a diaphragm with a gage side and a back side and a rim surrounding the diaphragm; a pair of inner islands on the gage side of the diaphragm wherein the pair of inner islands are spaced to form a first gap between the pair of inner islands; a first freed gage spanning the first gap; at least one bridge to provide an electrical communication path between the rim and the first freed gage; an outer island on the gage side of the diaphragm wherein the outer island and the rim are spaced to form a second gap; and a second freed gage spanning the second gap.

Abstract: A method of forming a conductive via in a substrate includes forming a via hole covered by a dielectric layer followed by an annealing process. The dielectric layer can getter the mobile ions from the substrate. After removing the dielectric layer, a conductive material is formed in the via hole, forming a conductive via in the substrate.

Abstract: This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces.

Abstract: A manufacturing method of a package carrier includes the following steps. Two base metal layers are bonded together. Two supporting layers are laminated onto the base metal layers respectively. Two release metal films are disposed on the supporting layers respectively. Each release metal film includes a first metal film and a second metal film separable from each other. Two first patterned metal layers are formed on the release metal films respectively. Each first patterned metal layer includes a pad pattern. Two dielectric layers are formed on the release metal films respectively and cover the corresponding first patterned metal layers. Each dielectric layer has a conductive via connecting to the corresponding pad pattern. Two second patterned metal layers are formed on the dielectric layers respectively. Each second patterned metal layer at least covers the conductive via. The base metal layers are separated from each other to form two independent package carriers.

Abstract: A method of manufacturing a printed circuit board having a bump is disclosed. The method includes preparing a first carrier having a first circuit formed thereon, compressing the first carrier to one surface of an insulation layer such that the first circuit is buried, stacking an etching resist on the first carrier in accordance with where the bump is to be formed and forming the bump by etching the first carrier. In accordance with an embodiment of the present invention, the difference in height between a bump and its adjacent bump in a printed circuit board can be reduced, and thus electrical connection between an electronic component and the printed circuit board can be better implemented.

Abstract: A multilayer wiring board has a high degree of freedom of wiring design and can realize high-density wiring, and a method to simply manufacture the multilayer wiring board. A core substrate with two or more wiring layers provided thereon through an electrical insulating layer. The core substrate has a plurality of throughholes filled with an electroconductive material, and the front side and back side of the core substrate have been electrically conducted to each other by the electroconductive material. The throughholes have an opening diameter in the range of 10 to 100 ?m. An insulation layer and an electroconductive material diffusion barrier layer are also provided, and the electroconductive material is filled into the throughholes through the insulation layer. A first wiring layer provided through an electrical insulating layer on the core substrate is connected to the electroconductive material filled into the throughhole through via.

Abstract: A circuit substrate includes a circuit stack, a patterned conductive layer, a dielectric layer, and a plurality of thickening conductive layers. The circuit stack has a surface. The patterned conductive layer is located on the surface of the circuit stack and has a plurality of traces. Each of the traces has a bonding segment. The dielectric layer is located on the surface of the circuit stack and covers the patterned conductive layer. Besides, the dielectric layer has a plurality of bonding openings Each of the bonding openings exposes the corresponding bonding segment. Each of the thickening conductive layers is located on the corresponding bonding segment. A semiconductor package structure having the above circuit substrate and a process for fabricating a circuit substrate are also provided.

Abstract: Provided is a method for manufacturing a probe card which inspects electrical characteristics of a plurality of semiconductor devices in batch. The method includes: a step of forming a plurality of probes, which are to be brought into contact with external terminals of the semiconductor devices, on one side of a board which forms the base body of the probe card; a step of forming on the board, by photolithography and etching, a plurality of through-holes which reach the probes from the other side of the board; a step of forming, in the through-holes, through electrodes to be conductively connected with the probes, respectively; and a step of forming wiring, which is conductively connected with the through electrodes, on the other side of the board.

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

Abstract: A method of manufacturing at least a portion of a printed circuit board. The method includes: applying a lamination adhesive on a first plural-layer substrate that includes a plurality of circuit layers with at least one first metal pad on a first side of the first plural-layer substrate; applying a protective film on the lamination adhesive; forming at least one via into the lamination adhesive to expose the at least one metal pad on the first side of the first plural-layer substrate; filling at least one conductive paste into the at least one via formed in the lamination adhesive; removing the protective film to expose the lamination adhesive on the first plural-layer substrate; and attaching the first plural-layer substrate with a second plural-layer substrate that includes a plurality of circuit layers with at least one second metal pad on a second side of the second plural-layer substrate.

Abstract: A printed circuit board and a preparation method thereof. The preparation method includes: making a first through hole in a core board including a metal layer; filling copper into the first through hole; forming a circuit pattern of the metal layer of the core board through an alkaline etching process; successively laminating a dielectric layer and a first copper foil on one side of the core board; making a second through hole opposite to and communicated with the first through hole, in the first copper foil; filling copper into the second through hole; and forming a circuit pattern of the first copper foil. The method for preparing the printed circuit board provided in the present invention can effectively reduce the preparation cost of the printed circuit board, greatly increase the yield of a product and further improve the universality of application.

Abstract: A particular device includes a coil and a discontinuous magnetic core. The discontinuous magnetic core includes a first elongated portion, a second elongated portion, and at least two curved portions, where the portions are coplanar and physically separated from each other. The discontinuous magnetic core is arranged to form a discontinuous loop. The discontinuous magnetic core is deposited as a first layer above a dielectric substrate. A first portion of the coil extends above a first surface of the magnetic core. A second portion of the coil extends below a second surface of the magnetic core. The second portion of the coil is electrically coupled to the first portion of the coil. The second surface of the magnetic core is opposite the first surface of the magnetic core.

Abstract: A method of manufacturing a display device includes forming a first signal line and a second signal line on a first substrate, forming a first insulating layer, forming a first electrode layer on the first insulating layer, forming a first electrode piece and a first lens electrode from the first electrode layer based on a first mask, forming a second insulating layer on the first electrode piece and the first lens electrode, defining a first contact hole exposing the first signal line based on a second mask, and defining a second contact hole exposing the second signal line on the second mask, forming a second electrode layer on the second insulating layer, forming a lower electrode from the second electrode layer based on the first mask, forming a third electrode layer on the second insulating layer, and forming an upper electrode and a second lens electrode.

Abstract: Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. In some embodiments the graphene and non-graphene regions may be nested within one another. In some embodiments an electrically insulative material may be over an upper surface of the laminate structure, and an opening may extend through the insulative material to a portion of the laminate structure. Electrically conductive material may be within the opening and in electrical contact with at least one of the non-graphene regions of the laminate structure. Some embodiments include methods of forming electrical interconnects in which non-graphene material and graphene are alternately formed within a trench to form nested non-graphene and graphene regions.

Abstract: The presently claimed invention is to provide a package for compact RF signal system, and a method to form the package thereof in order to miniaturize the size of package, improve signal integrity, and reduce manufacturing cost. The package comprises a hybrid substrate with a sandwiched structure, in which the hybrid substrate comprises an upper layer and a lower layer with different dielectric properties being separated by an interposer for improving electrical isolation and mechanical stiffness. Metal layers are formed on the sidewalls of the opening to surround an active component, such that the metal sidewalls together with two ground plates in the upper and lower layers constitute a self-shielding enclosure inside the package to protect the active component.

Abstract: A bio-fluid sensor is formed by depositing polyimide on a glass substrate. Gold and platinum are deposited on the polyimide and patterned to form fluid sensing electrodes, signal traces, and a temperature sensor. The fluid sensor is then fixed to a flexible tape and peeled off of the glass substrate.

Abstract: A method for fabricating a coaxial structure having an electrical conductor surrounded by an optically conductive dielectric is disclosed. The method may include creating an optical trench in an electrical conductor and depositing an optical material into the optical trench to cover an inner surface of the trench. The method may also include removing a portion of the deposited optical material from the optical trench to form an embedded trench in the deposited optical material, and building up electrically conductive material from within the embedded trench to create an inner electrical conductor. The method may also include depositing optical material around an exposed portion of the inner electrical conductor to create an optical channel encapsulating the inner electrical conductor, and depositing electrically conductive material over a top surface of the optical channel and over a top surface of the first electrical conductor to create the coaxial structure.

Abstract: An array substrate, comprising: a substrate; a metal pattern formed on the substrate; an insulation layer formed on the metal pattern and formed with a via therein; and a transparent conductive pattern formed on the insulation layer and electrically connected to the metal pattern through the via, wherein the via has a cross section exhibiting an irregular geometry shape having a curved side edge.

Abstract: It is described an integrated gas sensor device comprising a silicon substrate and an oxide layer on the silicon substrate, as well as a working electrode, a counter electrode and a reference electrode, on the oxide layer, the working electrode and the counter electrode having respective active area exposed to an environmental air through at least a plurality of first openings and a plurality of second openings in the oxide layer in correspondence of the working electrode and of the counter electrode, further comprising an electrolyte layer portion and a hydrogel layer portion on the electrolyte layer portion, the electrolyte and hydrogel layer portions having a same size, suitable to cover at least the working, counter and reference electrodes, the hydrogel layer portion acting as a “quasi solid state” water reservoir.

Abstract: An optical interposer that includes a glass substrate having one or more optical vias extending through the glass substrate. A first optical polymer may be bonded to the substrate and to interior surfaces of the one or more optical vias. Implementations include one or more optical via cores comprising a second optical polymer that has a greater refractive index than the first optical polymer. The one or more optical via cores may be at least partially surrounded by the first optical polymer. Embodiments include encapsulated optical waveguides in communication with the optical vias and/or via cores. Example implementations include layers of electrical insulation, electrical traces, and electrical vias. A method of manufacture includes forming the optical vias by laser ablation. Certain embodiments may include chemically etching the inside of the vias to improve surface roughness.

Abstract: The invention provides a vertical conductive unit. The vertical conductive unit comprises an insulating layer comprising a connecting via, a first conductor, a second conductor, and a third conductor. The insulating layer comprises photosensitive polyimide, and the glass transition temperature of the photosensitive polyimide is lower than about 200° C. The invention also provides a method for manufacturing the vertical conductive unit.

Abstract: A traveling wave device includes a slow wave circuit supported by a dielectric membrane. The dielectric membrane can have a thickness substantially smaller than a wavelength of operation of the traveling wave device.

Abstract: A method for the production of a transparent conductor deposit on a substrate, the method comprising: providing a substrate formed from a first material; depositing a film of a second material on the substrate; causing the film to crack so as to provide a plurality of recesses; depositing a conductive material in the recesses; and removing the film from the substrate so as to yield a transparent conductive deposit on the substrate.

Abstract: An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon.

Abstract: An electronic device includes a structure. The structure includes a first set of through glass vias (TGVs) and a second set of TGVs. The first set of TGVs includes a first via and the second set of TGVs includes a second via. The first via has a different cross-sectional shape than the second via.

Abstract: A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; a first encapsulant in the first openings; a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.

Abstract: A touch screen sensing module, includes a substrate, a first conductive layer and a second conductive layer which are laminated over each other, an insulating adhesive layer is provided between the first conductive layer and the second conductive layer; the first conductive layer includes multiple parallel first conductive strips on the substrate and material of the first conductive strips is transparent semiconductor oxide; the second conductive layer includes multiple parallel second conductive strips provided in the insulating adhesive layer; each of the second conductive strips is a conductive grid formed by intersected fine conductive wires, the first conductive strips and the second conductive strips are insulatedly spaced apart in a thickness direction of the substrate. The touch screen sensing module has only one substrate layer, the thickness is reduced, material is saved and cost is low. A manufacturing method thereof and a display device are further provided.

Abstract: A method of thin printed circuit board wet process consistency on the same carrier, and more particularly to a printed circuit board in the developing, copper plating, stripping, etching and other wet processes uses the same frame as a carrier from the beginning to the end of the wet process, such that the thin printed circuit board is conducted a continuous and automatic wet process to avoid disassembly, storage and transportation between each process. Moreover, when using the flame, the thin printed circuit board is smooth and flattening in the wet process for avoiding “water effect,” the effective area is not exposed to any mechanical members for preventing scratches, and there are point contacts between the thin printed circuit board and the frame for preventing chemical residue. Accordingly, the present invention can not only enhance the yield of the thin printed circuit board but also shorten the production time.

Abstract: A substrate assembly including a photosensitive etching glass substrate; and a first substrate and a second substrate for interposing both main surfaces of the photosensitive etching glass substrate between them. One of the main surfaces of the photosensitive etching glass substrate is thermally bonded to the first substrate, and the other main surface of the photosensitive etching glass substrate is bonded to the second substrate. When a thermal expansion coefficient of the photosensitive etching glass substrate is defined as C0, and a thermal expansion coefficient of the first substrate is defined as C1, and a thermal expansion coefficient of the second substrate is defined as C2, C1/C2 satisfies a relation of 0.7 or more and 1.3 or less, and at least one of a relation of C0/C1 satisfying less than 0.7 or larger than 1.3, and a relation of C0/C2 satisfying less than 0.7 or larger than 1.3 is satisfied.

Abstract: A structure of via hole of electrical circuit board includes an adhesive layer and a conductor layer that are formed after wiring is formed on a carrier board. At least one through hole extends in a vertical direction through the carrier board, the wiring, the adhesive layer, and the conductor layer and forms a hole wall surface. The conductor layer shows a height difference with respect to an exposed zone of the circuit trace in the vertical direction. A conductive cover section covers the conductor layer and the hole wall surface of the through hole. The carrier board is a single-sided board, a double-sided board, a multi-layered board, or a combination thereof, and the single-sided board, the double-sided board, and multi-layered board can be flexible boards, rigid boards, or composite boards combining flexible and rigid boards.

Abstract: A touch display unit, includes: a base substrate having a first surface to which a user's touch is applied, and a second surface having a concavo-convex pattern of a plurality of grooves; an electrode layer formed on the second surface, having sensing regions for generating an electric signal by sensing the user's touch, and having open regions corresponding to part of the plurality of grooves; and a display panel formed below the electrode layer, and providing light to the base substrate.

Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.

Abstract: Imprinting tools and processes for making such tools, circuitry that includes narrow, high aspect ratio traces having reduced parasitic capacitance to adjacent circuit features and processes for making such circuitry using the imprinting tools are described.

Abstract: There is provided a liquid ejecting head including: a flow path formation substrate on which a pressure generation chamber communicating with nozzle openings for discharging liquid is provided; and a piezoelectric element which is provided on the flow path formation substrate and includes a piezoelectric layer, an electrode, and a wiring layer connected to the electrode, in which the wiring layer includes an adhesion layer which is provided on the electrode side and contains at least titanium and tungsten, and a conductive layer containing copper which is provided on a side of the adhesion layer opposite the electrode.

Abstract: A dynamic pattern generator (DPG) device and method of making a DPG device are disclosed. The DPG device is used in semiconductor processing tools that require multiple electron-beams, such as direct-write lithography. The device is a self-aligned DPG device that enormously reduces the required tolerances for aligning the various electrode layers, as compared to other design configurations including the non-self-aligned approach and also greatly simplifies the process complexity and cost. A process sequence for both integrated and non-integrated versions of the self-aligned DPG device is described. Additionally, an advanced self-aligned DPG device that eliminates the need for a charge dissipating coating or layer to be used on the device is described. Finally, a fabrication process for the implementation of both integrated and non-integrated versions of the advanced self-aligned DPG device is described.

Abstract: A method for manufacturing a package substrate is provided, including etching a substrate to form trenches each having a buffer portion, and forming a circuit in each of the trenches. The trenches are formed by etching instead of excimer laser to increase the aspect ratio of the trench, thereby solving the problem that the metallic layer is not thick enough and achieving a high yield of the circuit and a good process capability index.

Abstract: Provided is a device packaging structure including: an interposer substrate including a substrate, and a plurality of through-hole interconnections formed inside a plurality of through-holes passing through the substrate from a first main surface toward a second main surface, the first main surface being one main surface of the substrate, the second main surface being the other main surface thereof; a first device which includes a plurality of electrodes and is arranged so that these electrodes face the first main surface; and a second device which includes a plurality of electrodes of which an arrangement is different from an arrangement of each of the electrodes of the first device, and is arranged so that these electrodes face the second main surface.

Abstract: A substrate includes an iron-nickel alloy core or a cobalt-nickel ferrous alloy core, a chromium conversion coating on at least a portion of the core, and an insulating coating on the chromium conversion coating. A method of making a substrate includes: providing an iron-nickel alloy core or a cobalt-nickel ferrous alloy core, applying a chromium conversion coating on at least a portion of the core, and applying an insulating coating on the chromium conversion coating.

Abstract: A Capacitive Micromachined Ultrasonic Transducer (CMUT) device includes at least one CMUT cell including a first substrate having a top side including a patterned dielectric layer thereon including a thick and a thin dielectric region. A membrane layer is bonded on the thick dielectric region and over the thin dielectric region to provide a movable membrane over a micro-electro-mechanical system (MEMS) cavity. A through-substrate via (TSV) includes a dielectric liner which extends from a bottom side of the first substrate to a top surface of the membrane layer. A top side metal layer includes a first portion over the TSV, over the movable membrane, and coupling the TSV to the movable membrane. A patterned metal layer is on the bottom side surface of the first substrate including a first patterned layer portion contacting the bottom side of the first substrate lateral to the TSV.

Abstract: A substrate manufacturing method includes an inner layer circuit forming step for partially removing metal films from an insulating base material (2), on both surfaces of which the metal films are stuck, and forming an inner layer circuit (3); and an insulating layer forming step for applying first insulating resin (4) to each of both the surfaces of the insulating base material (2) with an inkjet system and forming an insulating layer (5). In the insulating layer forming step, a via hole (6) from which the inner layer circuit (3) is partially exposed is formed simultaneously with the application of the first insulating resin (4). Consequently, a step of separately forming a via hole with a laser or the like is unnecessary, expenses are relatively low, and it is possible to simplify a manufacturing process.

Abstract: A miniaturised electrochemical sensor for detection of a component in a gas is provided. The sensor comprises a reference electrode, a counter electrode and a structure comprising a plurality of passages delineated by walls extending along the passages. A working electrode covers the walls of the structure and a layer of an ionomer covers at least part of the working electrode along the walls of the structure. The layer of ionomer is in ion conducting contact with the electrodes. The disclosure further relates to a method of fabricating a miniaturised electrochemical sensor and to a device for measuring content of NO in exhaled breath comprising such a miniaturised electrochemical sensor.

Abstract: A mother substrate for a liquid crystal display device includes: a substrate; a plurality of unit array patterns on the substrate, each of the plurality of unit array patterns including a gate line, a data line crossing the gate line, a thin film transistor connected to the gate line and the data line and a pixel electrode connected to the thin film transistor; a first electrostatic discharge pattern surrounding the plurality of unit array patterns; a second electrostatic discharge pattern connected to the gate line and crossing the first electrostatic discharge pattern; and a third electrostatic discharge pattern connected to the data line and crossing the first electrostatic discharge pattern, the third electrostatic discharge pattern contacting the second electrostatic discharge pattern.

Abstract: Embodiments described herein provide a method of manufacturing integrated circuit (IC) devices. The method includes coupling a first surface of a first intermediate substrate to a first surface of a second intermediate substrate, forming a first plurality of patterned metal layers on a second surface of the first intermediate substrate to form a first substrate and a second plurality of patterned metal layers on a second surface of the second intermediate substrate to form a second substrate, and separating the first and second substrates. Each of the first substrate and the second substrate is configured to facilitate electrical interconnection between a respective IC die and a respective printed circuit board (PCB).