Etching Of Semiconductor Material To Produce An Article Having A Nonelectrical Function Patents (Class 216/2)
  • Patent number: 9154886
    Abstract: A capacitive transducer and manufacturing method thereof is provided. A multifunction device including a plurality of the capacitive transducers is also provided, where the capacitive transducers are disposed on a substrate and include at least one microphone and at least one pressure sensor or ultrasonic device.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: October 6, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Jien-Ming Chen, Chin-Wen Huang, Chin-Hung Wang, Hsin-Li Lee
  • Patent number: 9142586
    Abstract: A semiconductor image sensor device includes first and second semiconductor substrates. A pixel array and a control circuit are formed in a first surface of the first substrate. An interconnect layer is formed over the first surface of the first substrate and electrically connects the control circuit to the pixel array. A top conducting layer is formed over the interconnect layer to have electrical connectivity with at least one of the control circuit or the pixel array via the interconnect layer. A surface of a second substrate is bonded to the top conducting layer. A conductive through-silicon-via (TSV) passes through the second substrate, and has electrical connectivity with the top conducting layer. A terminal is formed on an opposite surface of the second substrate, and electrically connected to the TSV.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: September 22, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-De Wang, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Jeng-Shyan Lin
  • Patent number: 9136303
    Abstract: A method of protecting a CMOS device within an integrated photonic semiconductor structure is provided. The method may include depositing a conformal layer of germanium over the CMOS device and an adjacent area to the CMOS device, depositing a conformal layer of dielectric hardmask over the germanium, and forming, using a mask level, a patterned layer of photoresist for covering the CMOS device and a photonic device formation region within the adjacent area. Openings are etched into areas of the deposited layer of silicon nitride not covered by the patterned photoresist, such that the areas are adjacent to the photonic device formation region. The germanium material is then etched from the conformal layer of germanium at a location underlying the etched openings for forming the photonic device at the photonic device formation region. The conformal layer of germanium deposited over the CMOS device protects the CMOS device.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: September 15, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, Marwan H. Khater, Edward W. Kiewra, Carol Reinholm, Steven M. Shank
  • Patent number: 9110237
    Abstract: A method of manufacturing an optical waveguide is provided which enables a recognition device such as a CCD camera to easily recognize an alignment mark for positioning a mold for over cladding layer formation. The method includes the steps of: forming protruding cores and a protruding alignment mark on an upper surface of an under cladding layer on a substrate by a photolithographic method; and forming the over cladding layer by use of the mold positioned using the alignment mark as a guide. For the formation of the alignment mark, a photomask is used which has an opening pattern for alignment mark formation including an opening, and a light transmission amount reduction region provided around the opening and having an aperture ratio within a range greater than 10% and less than 80%. The alignment mark is formed to have a peripheral side surface in the form of an inclined surface.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: August 18, 2015
    Assignee: NITTO DENKO CORPORATION
    Inventors: Naoki Shibata, Ryusuke Naito, Toru Mizutani
  • Patent number: 9103336
    Abstract: A micropump device including a first wafer and a second wafer attached to the first wafer. The first and second wafers are configured to define a chamber therebetween having a predetermined volume. A third wafer is attached to the second wafer to define an inlet section and an outlet section in fluid communication with the chamber. At least one of the second and third wafers are formed to define a moveable diaphragm configured to change the predetermined volume of the chamber for pumping a fluid between the inlet section and the outlet section.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: August 11, 2015
    Assignee: Wayne State University
    Inventors: Jianke Kang, Gregory W. Auner
  • Patent number: 9069005
    Abstract: A capacitance-to-frequency converter is configured to convert a difference between first and second capacitances produced of a teeter-totter capacitive transducer as a result of a rotational force being applied to the teeter-totter capacitive transducer to a first signal having a first frequency that is a function of the rotational force, and to convert a sum of the first and second capacitances produced as a result of an acceleration force to a second signal having a second frequency that is a function of the acceleration force. The capacitance-to-frequency converter includes a first oscillator having a first oscillator frequency that changes in response to a change in the first capacitance; a second oscillator having a second oscillator frequency that changes in response to a change in the second capacitance; and a mixer having first and second mixer inputs connected outputs of the first and second oscillators.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: June 30, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Richard C. Ruby
  • Patent number: 9054059
    Abstract: The present invention relates to a flexible organic electroluminescent device, and the invention disclosed herein includes a switching thin film transistor and a drive thin film transistor formed at the each pixel region on a substrate; a first electrode connected to a drain electrode of the drive thin film transistor, and formed at the each pixel region; a bank formed on the display area and non-display area of the substrate; a spacer formed on a bank in the non-display area, and disposed in the vertical direction in parallel to a lateral surface of the display area; an organic light emitting layer separately formed for each pixel region; a second electrode formed on an entire surface of the organic light emitting layer; an organic layer formed on an entire surface of the substrate; a barrier film located to face the substrate.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: June 9, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: MiSo Kim, DoHyung Kim, SeHwan Na, ChiMin Choi
  • Patent number: 9049797
    Abstract: An active component array includes a target substrate having one or more contacts formed on a side of the target substrate, and one or more printable active components distributed over the target substrate. Each active component includes an active layer having a top side and an opposing bottom side and one or more active element(s) formed on or in the top side of the active layer. The active element(s) are electrically connected to the contact(s), and the bottom side is adhered to the target substrate. Related fabrication methods are also discussed.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: June 2, 2015
    Assignee: Semprius, Inc.
    Inventors: Etienne Menard, Christopher Bower, Matthew Meitl, Philip Garrou
  • Patent number: 9040431
    Abstract: A method for processing a silicon wafer is provided. The method includes allowing an etchant to flow along a surface of the silicon wafer to form a line in which a plurality of apertures are arranged in a flow direction of the etchant from an upstream side to a downstream side. The apertures arranged in the line include a first aperture formed on the most upstream side and a second aperture formed downstream of the first aperture in the flow direction of the etchant. The first aperture and the second aperture are subjected to different processes after being formed.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: May 26, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hirohisa Fujita, Shuji Koyama, Keiji Matsumoto, Kenta Furusawa
  • Publication number: 20150139885
    Abstract: A polishing liquid comprising an abrasive grain, an additive, and water, wherein the abrasive grain includes a hydroxide of a tetravalent metal element, and produces absorbance of 1.00 or more and less than 1.50 for light having a wavelength of 400 nm in an aqueous dispersion having a content of the abrasive grain adjusted to 1.0 mass %.
    Type: Application
    Filed: March 26, 2013
    Publication date: May 21, 2015
    Applicant: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Tomohiro Iwano, Hisataka Minami, Toshiaki Akutsu, Koji Fujisaki
  • Patent number: 9031684
    Abstract: A method and system for integrated circuit fabrication is disclosed. In an example, the method includes determining a first process parameter of a wafer and a second process parameter of the wafer, the first process parameter and the second process parameter corresponding to different wafer characteristics; determining a variation of a device parameter of the wafer based on the first process parameter and the second process parameter; constructing a model for the device parameter as a function of the first process parameter and the second process parameter based on the determined variation of the device parameter of the wafer; and performing a fabrication process based on the model.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Han Cheng, Chin-Hsiang Lin, Chi-Ming Yang, Chun-Lin Chang, Chih-Hong Hwang
  • Publication number: 20150115307
    Abstract: [Technical Problem] A sapphire substrate and a method for manufacturing the same are provided, which enables growth of a nitride semiconductor having excellent crystallinity and can achieve a nitride semiconductor light emitting element having excellent light extraction efficiency. [Solution to Problem] A sapphire substrate provided with a plurality of projections on a principal surface on which a nitride semiconductor is grown to form a nitride semiconductor light emitting element, wherein the projection is substantially pyramidal-shaped having a pointed top and constituted by a plurality of side surfaces, wherein the side surface has an inclined angle of between 53° and 59° from a bottom surface of the projection, and wherein the side surface is crystal-growth-suppressed surface on which growth of nitride semiconductor is suppressed relative to the substrate surface located between the adjacent projections.
    Type: Application
    Filed: January 9, 2015
    Publication date: April 30, 2015
    Inventors: Naoya SAKO, Takashi Ohara, Yoshiki Inoue, Yuki Shibutani, Yoshihito Kawauchi, Kazuyuki Takeichi, Yasunori Nagahama
  • Patent number: 9017561
    Abstract: A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: April 28, 2015
    Assignee: NXP, B.V.
    Inventors: Gerhard Koops, Jozef Thomas Martinus van Beek
  • Patent number: 9011706
    Abstract: A foraminous microstructure or film that has photonic or plasmonic properties is made by forming a structure or film composed of at least two constituent materials so that the compositional ratio of the constituent materials varies in a depth direction of the structure, and then removing one of the materials from the structure.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: April 21, 2015
    Assignee: City University of Hong Kong
    Inventors: Yang Yang Li, Zhengtao Xu, Chun Kwan Tsang
  • Publication number: 20150090661
    Abstract: The present technology provides microfabricated filtration devices, methods of making such devices, and uses for microfabricated filtration devices. The devices may allow diffusion to occur between two fluids with improved transport resistance characteristics as compared to conventional filtration devices. The devices may include a compound structure that includes a porous membrane overlying a support structure. The support structure may define a cavity and a plurality of recesses formed in a way that can allow modified convective flow of a first fluid to provide improved diffusive transport between the first fluid and a second fluid through the membrane.
    Type: Application
    Filed: May 16, 2013
    Publication date: April 2, 2015
    Inventors: Rishi Kant, Shuvo Roy, Benjamin Chui, Kenneth G. Goldman
  • Patent number: 8992784
    Abstract: A method of fabricating a reinforced silicon micromechanical part includes: micro-machining the part, or a batch of parts in a silicon wafer; forming a silicon dioxide layer over the entire surface of the part, in one or plural operations, so as to obtain a thickness of silicon dioxide that is at least five times greater than the thickness of native silicon dioxide; and removing the silicon dioxide layer by etching.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: March 31, 2015
    Assignee: Montres Breguet SA
    Inventor: Nakis Karapatis
  • Patent number: 8986553
    Abstract: A method for manufacturing an optical semiconductor device includes the steps of preparing a substrate product including a semiconductor layer, a mesa structure, and a protective layer; forming a buried layer composed of a resin on the substrate product; forming a first opening in the buried layer on the mesa structure; forming a second opening in the buried layer on the semiconductor layer; exposing the mesa structure and the semiconductor layer by etching the protective layer; forming a first electrode in the first opening; and forming a second electrode in the second opening. The step of forming the second opening includes a first etching step including etching the buried layer using a first resist mask for forming a recess and a second etching step including etching the buried layer using a second resist mask having an opening pattern which has an opening width not smaller than that of the recess.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: March 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takamitsu Kitamura, Hideki Yagi
  • Publication number: 20150048046
    Abstract: A pattern-forming method in which processibility of a silicon-containing film in etching with a fluorine gas and resistance against etching with an oxygen gas can be together improved in a multilayer resist process to form a finer pattern. Provided is a pattern-forming method that includes the steps of (1) providing a silicon-containing film on the upper face side of a substrate to be processed using a polysiloxane composition; (2) forming a resist pattern on the silicon-containing film; (3) dry-etching the silicon-containing film using the resist pattern as a mask to form a silicon-containing pattern; and (4) dry-etching the substrate to be processed using the silicon-containing pattern as a mask to form a pattern, in which the polysiloxane composition includes (A) a polysiloxane containing a fluorine atom, and (B) a crosslinking accelerator.
    Type: Application
    Filed: September 28, 2012
    Publication date: February 19, 2015
    Applicant: JSR CORPORATION
    Inventor: JSR Corporation
  • Patent number: 8956544
    Abstract: A method for manufacturing a micromechanical structure, and a micromechanical structure. The micromechanical structure encompasses a first micromechanical functional layer, made of a first material, that comprises a buried conduit having a first end and a second end; a micromechanical sensor structure having a cap in a second micromechanical functional layer that is disposed above the first micromechanical functional layer; an edge region in the second micromechanical functional layer, such that the edge region surrounds the sensor structure and defines an inner side containing the sensor structure and an outer side facing away from the sensor structure; such that the first end is located on the outer side and the second end on the inner side.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: February 17, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Johannes Classen, Jochen Reinmuth, Sebastian Guenther, Pia Bustian-Todorov
  • Patent number: 8940586
    Abstract: The present disclosure relates to a bump processing method and/or resulting MEMS-CMOS structure, in which one or more anti-stiction bumps are formed within a substrate prior to the formation of a cavity in which the one or more anti-stiction bumps reside. By forming the one or more anti-stiction bumps prior to a cavity, the sidewall angle and the top critical dimension (i.e., surface area) of the one or more anti-stiction bumps are reduced. The reduction in sidewall angle and critical dimension reduces stiction between a substrate and a moveable part of a MEMS device. By reducing the size of the anti-stiction bumps through a processing sequence change, lithographic problems such as reduction of the lithographic processing window and bump photoresist collapse are avoided.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chris Kuo, Lee-Chuan Tseng
  • Publication number: 20150015948
    Abstract: A polarizing plate having an excellent optical property and a method of manufacturing the same are disclosed. The polarizing plate includes: a transparent substrate 11 transmitting light in a used bandwidth; an absorbing layer 12 having at least a metal-containing semiconductor layer containing a metal, the absorbing layer being arranged as a one-dimensional lattice shaped wire-grid structure having a pitch smaller than the wavelength of the light in the used bandwidth; a dielectric layer 13 arranged as a one-dimensional lattice shaped wire-grid structure having a pitch smaller than the wavelength of light in the used bandwidth; and a reflective layer 14 arranged as a one-dimensional lattice shaped wire-grid structure having a pitch smaller than the wavelength of light in the used bandwidth, wherein the absorbing layer 12, the dielectric layer 13 and the reflective layer 14 are layered on the transparent substrate 11 in this or reversed order.
    Type: Application
    Filed: June 27, 2014
    Publication date: January 15, 2015
    Inventors: Akio TAKADA, Eiji TAKAHASHI
  • Patent number: 8932479
    Abstract: Provided is a polishing liquid which is used for chemical mechanical polishing of a body to be polished having a layer containing polysilicon or a modified polysilicon, and using which the polishing rate of a layer containing a silicon-based material other than polysilicon is high and polishing of the layer containing polysilicon can be selectively suppressed. The polishing liquid includes components (A), (B), and (C), has a pH of from 1.5 to 7.0, and is capable of selectively polishing a second layer with respect to a first layer: (A) colloidal silica particles having a negative ? potential; (B) phosphoric acid or an organic phosphonic acid compound represented by the following Formula (1) or (2); and (C) an anionic surfactant having at least one group represented by the following Formulae (I) to (IV): R2—C(R3)3-a—(PO3H2)a??Formula (1): R4—N(R5)m—(CH2—PO3H2)n??Formula (2): —PO3X2??Formula (I): —OPO3X2??Formula (II): —COOX??Formula (III): —SO3X??Formula (IV).
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: January 13, 2015
    Assignee: FUJIFILM Corporation
    Inventor: Tetsuya Kamimura
  • Patent number: 8932473
    Abstract: The invention relates to a method for making a 3D nanostructure having a nanosubstructure, comprising the steps of: i) providing a mold comprising at least one sharp concave corner; ii) conformational depositing at least one structural material in the sharp concave corner; iii) isotropically removing structural material; iv) depositing at least one other structural material; v) removing earlier deposited structural material; vi) forming a nanosubstructure; and vii) removing the mold thereby providing the 3D nanostructure having the nanosubstructure.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: January 13, 2015
    Assignee: Universiteit Twente
    Inventors: Johan Willem Berenschot, Niels Roelof Tas
  • Publication number: 20150009586
    Abstract: Lightguides, devices incorporating lightguides, processes for making lightguides, and tools used to make lightguides are described. A lightguide includes light extractors arranged in a plurality of regions on a surface of the lightguide. The orientation of light extractors in each region is arranged to enhance uniformity and brightness across a surface of the lightguide and to provide enhanced defect hiding. The efficiency of the light extractors is controlled by the angle of a given light extractor face with respect to a light source illuminating the light guide.
    Type: Application
    Filed: September 23, 2014
    Publication date: January 8, 2015
    Inventors: Tzu-Chen Lee, David A. Ender, Guoping Mao, Jun-Ying Zhang, Jaime B. Willoughby
  • Patent number: 8911636
    Abstract: A method of fabricating a micro-device having micro-features on glass is presented. The method includes the steps of preparing a first glass substrate, fabricating a metallic pattern on the first glass substrate, preparing a second glass substrate and providing one or more apertures on the second glass substrate, heating the first glass substrate and the second glass substrate with a controlled temperature raise, bonding the first glass substrate and the second glass substrate by applying pressure to form a bonded substrate, wherein the metallic pattern is embedded within the bonded substrate, cooling the bonded substrate with a controlled temperature drop and thereafter maintaining the bonded substrate at a temperature suitable for etching, etching the metallic pattern within the bonded substrate, wherein an etchant has access to the metallic pattern via the apertures, forming a void within the bonded substrate, wherein the void comprises micro-features.
    Type: Grant
    Filed: September 29, 2013
    Date of Patent: December 16, 2014
    Inventor: Viswanadam Gautham
  • Patent number: 8904628
    Abstract: Disclosed herein is a method of manufacturing a noise removing filter, including preparing at least one conductive pattern, an insulating layer for covering the at least one conductive pattern, and a lower magnetic body including input/output stud terminals for electrically inputting and outputting electricity to and from the at least one conductive pattern; disposing a recognizable portion on upper surfaces of the input/output stud terminals; disposing an upper magnetic body on the recognizable portion and the insulating layer; polishing the upper magnetic body; and removing the recognizable portion such that a level of an upper surface of the upper magnetic body is higher than levels of the upper surfaces of the input/output stud terminals.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 9, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang Moon Lee, Sung Kwon Wi, Jeong Bok Kwak, Won Chul Sim, Young Seuck Yoo, Yong Suk Kim
  • Publication number: 20140352759
    Abstract: A photovoltaic power module including a reflector, and methods for manufacturing the reflector. The photovoltaic power module includes a plurality of photovoltaic cells arranged in an array, including a photon source facing surface having a plurality of active areas that convert photons to electrical energy and a plurality of inactive areas that do not convert photons to electrical energy. The reflector covers at least one inactive area of a photon source facing surface, for reflecting photons that would otherwise have fallen on the inactive area onto an active area. The output of the photovoltaic power module may therefore be increased.
    Type: Application
    Filed: August 21, 2012
    Publication date: December 4, 2014
    Applicant: SOLAR SYSTEMS PTY LTD
    Inventors: Brett Barnes, Joel Goodrich, Sam Carter
  • Patent number: 8883014
    Abstract: A monolithic fabrication method of parallel-plate electrowetting-on-dielectric (EWOD) chips for digital microfluidics of picoliter droplets is disclosed. Instead of assembling a second substrate to form a top plate, the top plate is generated in situ as a thin-film membrane that forms a monolithic cavity having a gap height on the order of micrometers with excellent accuracy and uniformity. The membrane is embedded with EWOD driving electrodes and confines droplets against the device substrate to perform digital microfluidic operations. Two main attributes of the monolithic architecture that distinguish it from tradition methods are: (i) it enables excellent control of droplet dimensions down to the micrometer scale, and (ii) it does not require the typical alignment and assembly steps of the two plates.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: November 11, 2014
    Assignee: The Regents of the University of California
    Inventors: Wyatt C. Nelson, Chang-Jin Kim
  • Patent number: 8883015
    Abstract: A method of producing projections on a patch including providing a mask on a substrate and etching the substrate using an etchant and a passivant to thereby control the etching process and form the projections, wherein the passivant does not include oxygen.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: November 11, 2014
    Assignee: The University of Queensland
    Inventors: Mark Anthony Fernance Kendall, Derek William Kenneth Jenkins
  • Patent number: 8883018
    Abstract: A method for fabricating a grating coupler having a bottom mirror in a semiconductor wafer including etching a trench from a top surface of a wafer and around a grating coupler formed in the wafer; etching a void underneath the grating coupler; etching a via into the void from the backside of the wafer; and depositing a mirror on the bottom of the grating coupler. Alternatively, additional oxide may be deposited on the bottom of the grating coupler prior to the deposition of the mirror such that a desirable oxide thickness on the bottom is achieved.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: November 11, 2014
    Assignee: Acacia Communications Inc.
    Inventor: Christopher Doerr
  • Patent number: 8877071
    Abstract: A method of making a mold includes forming spaced mold cavities in a mold body. The mold cavities include geometrically similar portions, but have respective depths below an initial reference surface that vary as a function of position along a particular direction. The mold cavities can be formed using anisotropic etching of preferred crystal directions in single crystal materials such as silicon. A portion of the mold material adjacent the initial reference surface is removed to expose a new reference surface at a tilt angle with respect to the initial reference surface. The modified mold cavities have their respective axes at a new desired tilt angle relative to the new reference surface.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: November 4, 2014
    Assignee: Metadigm LLC
    Inventor: Victor B. Kley
  • Patent number: 8877072
    Abstract: A method to fabricate a hierarchical graduated-branched structure that grows in a three-dimensional pattern down to fractal-branching, nano-size level is detailed. The fractal patterning is accomplished on a three-dimensional (i.e., non-planar) surface, by exposing the surface to a properly focused particle beam, which causes the spontaneous growth of graduated branches all over the surface. The structure can be fabricated with a single material and the fractal-patterning is done in a one step process. No addition of material is required for the formation of each branch. The fractal graduated branching structure can then be molded in order to produce replicas.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: November 4, 2014
    Inventors: Ranjana Sahai, Paolo Corradi
  • Patent number: 8858807
    Abstract: A process for making a microneedle array master comprises: (a) providing a photoreactive composition, the photoreactive composition comprising: (1) at least one reactive species that is capable of undergoing an acid- or radical-initiated chemical reaction, and (2) at least one multiphoton photoinitiator system; and (b) imagewise exposing at least a portion of the composition to light sufficient to cause simultaneous absorption of at least two photons, thereby inducing at least one acid- or radical-initiated chemical reaction where the composition is exposed to the light, the imagewise exposing being carried out in a pattern that is effective to define at least the surface of a plurality of microneedles. The microneedles may be solid and the outer surface of the microneedles may be characterized by at least one concave area. The master may be used to fabricate a tool for replication.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: October 14, 2014
    Assignee: 3M Innovative Properties Company
    Inventors: Robert J. DeVoe, Dennis E. Ferguson, Franklyn L. Frederickson, Mitchell A. F. Johnson, Mikhail L. Pekurovsky, Craig R. Sykora, Jeremy K. Larsen
  • Patent number: 8858811
    Abstract: A method for manufacturing a device comprising an elastic member on a substrate includes steps of: forming a sacrificial layer by forming a plurality of sacrificial sub-layers on the substrate; forming a plate member in or on the sacrificial layers connected to the substrate and substantially parallel to a top surface of the substrate; and removing the sacrificial sub-layers after forming the plate member by removing the sacrificial sub-layers in an order different from the reverse order of forming the sacrificial sub-layers.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: October 14, 2014
    Inventors: Yoshihiro Maeda, Fusao Ishii, Kazuhiro Watanabe, Hirotoshi Ichikawa
  • Patent number: 8852447
    Abstract: A method for simultaneously detecting and separating a target analyte such as a protein or other macromolecule that includes providing a porous silicon matrix on the silicon substrate, exposing the porous silicon matrix to an environment suspect of containing the target analyte, observing optical reflectivity of the porous silicon matrix; and correlating the changes in the silicon substrate to the target analyte.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 7, 2014
    Assignee: The Regents of the University of California
    Inventors: Michael J. Sailor, Gaurav Abbi, Boyce E. Collins, Keiki-Pua S. Dancil
  • Publication number: 20140291282
    Abstract: A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a substrate, the spreading layer having a monolayer. A stressor layer is formed on the spreading layer, and the stressor layer is configured to apply stress to a closest monolayer of the spreading layer. The closest monolayer is exfoliated by mechanically splitting the spreading layer wherein the closest monolayer remains on the stressor layer.
    Type: Application
    Filed: April 2, 2013
    Publication date: October 2, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Christos D. Dimitrakopoulos, Keith E. Fogel, James B. Hannon, Jeehwan Kim, Hongsik Park, Dirk Pfeiffer, Devendra K. Sadana
  • Patent number: 8846537
    Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Publication number: 20140264030
    Abstract: A chip-scale, air-clad semiconductor pedestal waveguide can be used as a mid-infrared (mid-IR) sensor capable of in situ monitoring of organic solvents and other analytes. The sensor uses evanescent coupling from a silicon or germanium waveguide, which is highly transparent in the mid-IR portion of the electromagnetic spectrum (e.g., between ?=1.3 ?m and ?=6.5 ?m for silicon and ?=1.3 ?m and ?=12.0 ?m for germanium), to probe the absorption spectrum of the fluid surrounding the waveguide. Launching a mid-IR beam into the waveguide exposed to a particular analyte causes attenuation of the evanescent wave's spectral components due to absorption by carbon, oxygen, hydrogen, and/or nitrogen bonds in the surrounding fluid. Detecting these changes at the waveguide's output provides an indication of the type and concentration of one or more compounds in the surrounding fluid.
    Type: Application
    Filed: November 11, 2013
    Publication date: September 18, 2014
    Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: PAO TAI LIN, YAN CAI, ANURADHA MURTHY AGARWAL, LIONEL C. KIMERLING
  • Publication number: 20140256028
    Abstract: According to one embodiment, a semiconductor micro-analysis chip for detecting fine particles in sample liquid includes a semiconductor substrate, a first flow channel that is formed in the semiconductor substrate and into which the sample liquid is introduced, and a plurality of columnar structures fully arranged in the first flow channel at regulation distance.
    Type: Application
    Filed: August 28, 2013
    Publication date: September 11, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kentaro KOBAYASHI, Hideto FURUYAMA
  • Patent number: 8828249
    Abstract: An optical deflector has: a movable plate having a reflecting surface and a side surface; and a support portion that supports the movable plate in such a manner that the movable plate is able to rotate around a predetermined axis, in which the side surface of the movable plate is recessed toward the axis.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: September 9, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Makiko Hino, Yasushi Mizoguchi
  • Patent number: 8828251
    Abstract: A method for finishing an exterior surface of an injection-molded product is provided, in which a metal layer is formed on the exterior surface of the injection-molded product, a photoresist layer is formed on the metal layer, a photomask is placed on the photoresist layer, light is projected onto the photomask, and remaining parts of the metal layer and the photoresist layer except for parts corresponding to a pattern formed on the photomask are removed by etching.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: September 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Bae Park, Pil-Woo Lee, Jong-Hwa Kim, Hak-Ju Kim, Jung-Won Cho
  • Patent number: 8828871
    Abstract: A pattern formation method, mask pattern formation method and a method for manufacturing semiconductor devices are provided in this disclosure, which are directed to the field of semiconductor processes. The pattern formation method comprises: providing a substrate; forming a polymer thin film containing a block copolymer on the substrate; forming a first pattern through imprinting the polymer thin film with a stamp; forming domains composed of different copolymer components through directed self assembly of the copolymer in the first pattern; selectively removing the domains composed of copolymer components to form a second pattern. In the embodiments of the present invention, finer pitch patterns can be obtained through combining the imprinting and DSA process without exposure, which as compared to the prior art methods has the advantage of simplicity. Furthermore, stamps used in imprinting may have relative larger pitches, facilitating and simplifying the manufacture and alignment of the stamps.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Junqing Zhou, Xiaoying Meng, Haiyang Zhang
  • Patent number: 8821747
    Abstract: A method for manufacturing a glass substrate for a magnetic disk comprises a surface grinding step of processing a mirror-surface plate glass, having a main surface in the form of a mirror surface, to a required flatness and surface roughness using fixed abrasive particles. The method comprises, before the surface grinding step using the fixed abrasive particles, a surface roughening step of roughening the surface of the mirror-surface plate glass by frosting.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: September 2, 2014
    Assignee: Hoya Corporation
    Inventors: Takanori Mizuno, Yosuke Suzuki
  • Patent number: 8821740
    Abstract: Provided is a nanowire manufacturing method, comprising forming a plurality of grid patterns on a substrate, forming a nanowire on the grid patterns, and separating the grid pattern and the nanowire. According to the present invention, the width and height of the nanowire can be adjusted by controlling the wet-etching process time period, and the nanowire can be manufactured at a room temperature at low cost, the nanowire can be mass-manufactured and the nanowire with regularity can be manufactured even in case of mass production.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: September 2, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Young Jae Lee, Kyoung Jong Yoo, Jun Lee, Jin Su Kim, Jae Wan Park
  • Publication number: 20140238952
    Abstract: A method for manufacturing a thin substrate includes the following steps: a first etching step in which the thickness of a glass substrate (110a) is reduced by etching one surface of the glass substrate (110a); a scribing step in which a scribe line (Ca) for splitting a glass substrate (110b), which is formed by reducing the thickness of the glass substrate (110a), is formed on a surface of the glass substrate (110b); and a second etching step in which the thickness of a glass substrate (110c), which is formed by forming the scribe line (Ca) on the glass substrate (110b), is reduced by etching a surface of the glass substrate (110c), and the glass substrate (110c) is split by way of the scribe line (Ca).
    Type: Application
    Filed: October 15, 2012
    Publication date: August 28, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Hiroki Makino, Gen Nagaoka, Takatoshi Kira
  • Publication number: 20140234198
    Abstract: Provided is an etching method including: (1) bringing a material containing at least one organic compound having an N—F bond into contact with the surface of a solid material; and (2) a step of heating the solid material; whereby etching can be performed safely and in a simple manner, at a higher etching rate, without the use of a high-environmental-load gas that causes global warming or highly reactive and toxic fluorine gas or hydrofluoric acid. The etching method may further include: (3) a step of exposing the solid material to light from the side of the material containing at least one organic compound having an N—F bond; and (4) a step of removing the material containing at least one organic compound having an N—F bond together with the residue remained between said material and the solid material.
    Type: Application
    Filed: August 10, 2012
    Publication date: August 21, 2014
    Applicants: DAIKIN INDUSTRIES, LTD., OSAKA UNIVERSITY
    Inventors: Mizuho Morita, Junichi Uchikoshi, Kentaro Tsukamoto, Takabumi Nagai, Kenji Adachi
  • Patent number: 8809135
    Abstract: A method for producing Microelectromechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) wafer includes providing an SOI wafer, performing a mesa etch to at least partially define the MEMS device, bonding the SOI wafer to an interposer by direct boding, removing the handle layer of the SOI wafer, removing the oxide layer of the SOI wafer, and further etching the device layer of the SOI wafer to define the MEMS device. A structure manufactured according to the above described processes includes an interposer comprising an SOI wafer and a MEMS device mounted on the interposer. The MEMS device comprises posts extending from a silicon plate. The MEMS device is directly mounted to the interposer by bonding the posts of the MEMS device to the device layer of the interposer.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: August 19, 2014
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventor: William D. Sawyer
  • Patent number: 8808553
    Abstract: A process for producing a liquid ejection head including a silicon substrate having a first surface and a second surface that is a surface on an opposite side to the first surface, an ejection energy generating element which is formed on a side of the first surface side and generates energy for ejecting a liquid, a cavity formed in the second surface and a liquid supply port which is formed in a bottom part of the cavity and communicates with the first surface, including, in the following order: (1) forming the cavity in the second surface of the silicon substrate by a first crystal anisotropic etching; (2) forming a chemical leading hollow in a slope of the cavity; (3) expanding the cavity by a second crystal anisotropic etching; and (4) forming the liquid supply port in a bottom face of the cavity by dry etching with the use of an ion.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: August 19, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Akio Goto
  • Publication number: 20140209562
    Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film.
    Type: Application
    Filed: March 31, 2014
    Publication date: July 31, 2014
    Applicant: Novellus Systems, Inc.
    Inventors: Adrien LaVoie, Shankar Swaminathan, Hu Kang, Ramesh Chandrasekharan, Tom Dorsh, Dennis M. Hausmann, Jon Henri, Thomas Jewell, Ming Li, Bryan Schlief, Antonio Xavier, Thomas W. Mountsier, Bart J. van Schravendijk, Easwar Srinivasan, Mandyam Sriram
  • Patent number: 8791021
    Abstract: Polycrystalline silicon germanium (SiGe) can offer excellent etch selectivity to silicon during cryogenic deep reactive ion etching in an SF6/O2 plasma. Etch selectivity of over 800:1 (Si:SiGe) may be achieved at etch temperatures from ?80 degrees Celsius to ?140 degrees Celsius. High aspect ratio structures with high resolution may be patterned into Si substrates using SiGe as a hard mask layer for construction of microelectromechanical systems (MEMS) devices and semiconductor devices.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: July 29, 2014
    Assignee: King Abdullah University of Science and Technology
    Inventors: Mohamed Serry, Andrew Rubin, Mohamed Refaat, Sherif Sedky, Mohammad Abdo