With Measuring, Testing, Or Inspecting Patents (Class 216/59)
  • Patent number: 8252193
    Abstract: A substrate plasma processing apparatus includes a chamber of which an interior is evacuated under a predetermined vacuum condition; an RF electrode which is disposed in the chamber and configured so as to hold a substrate to be processed on a main surface thereof; an opposing electrode which is disposed opposite to the RF electrode in the chamber; an RF voltage applying device for applying an RF voltage with a predetermined frequency to the RF electrode; and a pulsed voltage applying device for applying a pulsed voltage to the RF electrode so as to be superimposed with the RF voltage and which includes a controller for controlling a timing in application of the pulsed voltage and defining a pause period of the pulsed voltage.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: August 28, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Ui, Takashi Ichikawa, Naoki Tamaoki, Hisataka Hayashi, Akihiro Kojima
  • Patent number: 8232212
    Abstract: An apparatus for adaptive self-aligned dual patterning and method thereof. The method includes providing a substrate to a processing platform configured to perform an etch process and a deposition process and a metrology unit configured for in-vacuo critical dimension (CD) measurement. The in-vacuo CD measurement is utilized for feedforward adaptive control of the process sequence processing platform or for feedback and feedforward adaptive control of chamber process parameters. In one aspect, a first layer of a multi-layered masking stack is etched to form a template mask, an in-vacuo CD measurement of the template mask is made, and a spacer is formed, adjacent to the template mask, to a width that is dependent on the CD measurement of the template mask.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: July 31, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Matthew F. Davis, Thorsten B. Lill, Lei Lian
  • Patent number: 8231799
    Abstract: A plasma reactor for processing a workpiece such as a semiconductor wafer has a housing defining a process chamber, a workpiece support configured to support a workpiece within the chamber during processing and comprising a plasma bias power electrode. The reactor further includes plural gas sources containing different gas species, plural process gas inlets and an array of valves capable of coupling any of said plural gas sources to any of said plural process gas inlets. The reactor also includes a controller governing said array of valves and is programmed to change the flow rates of gases through said inlets over time. A ceiling plasma source power electrode of the reactor has plural gas injection zones coupled to the respective process gas inlets. In a preferred embodiment, the plural gas sources comprise supplies containing, respectively, fluorocarbon or fluorohydrocarbon species with respectively different ratios of carbon and fluorine chemistries.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: July 31, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Kallol Bera, Xiaoye Zhao, Kenny L. Doan, Ezra Robert Gold, Paul Lukas Brillhart, Bruno Geoffrion, Bryan Pu, Daniel J. Hoffman
  • Patent number: 8222156
    Abstract: Methods and arrangements for controlling the electron loss to the upper electrode, including techniques and apparatus for biasing the upper electrode more negatively to allow charged species to be trapped within the plasma chamber for a longer period of time, thereby increasing the plasma density may be increased. The induced RF signal on the upper electrode is rectified, thus biasing the upper electrode more negatively. The rectified RF signal may also be amplified, thus driving the upper electrode even more negatively, if desired.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: July 17, 2012
    Assignee: Lam Research Corporation
    Inventors: Rajindra Dhindsa, Hudson Eric, Alexei Marakhtanov, Andreas Fischer
  • Patent number: 8221638
    Abstract: Prior to wafer processing, pressure ratio control is executed on a divided flow rate adjustment means so as to adjust the flow rates of divided flows to achieve a target pressure ratio with regard to the pressures in the individual branch passages. As the processing gas from a processing gas supply means is diverted into first and second branch pipings under the pressure ratio control and the pressures in the branch passages then stabilize, the control on the divided flow rate adjustment means is switched to steady pressure control for adjusting the flow rates of the divided flows so as to hold the pressure in the first branch passage at the level achieved in the stable pressure condition. Only after the control is switched to the steady pressure control, an additional gas is delivered into the second branch passage via an additional gas supply means.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: July 17, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Kenetsu Mizusawa
  • Patent number: 8216485
    Abstract: A plasma etching method etches an organic film formed on a target substrate by using a plasma of a processing gas via a silicon-containing mask. The processing gas is a gaseous mixture of an oxygen-containing gas, a rare gas and a carbon fluoride gas. A computer-executable control program controls a plasma etching apparatus to perform the plasma etching method. A computer-readable storage medium stores therein a computer-executable control program.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: July 10, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Yoshimitsu Kon, Yoshinobu Hayakawa
  • Publication number: 20120152898
    Abstract: In a supercritical fluid method a supercritical fluid is supplied into a process chamber. The supercritical fluid is discharged from the process chamber as a supercritical fluid process proceeds. A concentration of a target material included in the supercritical fluid discharged from the process chamber is detected during the supercritical fluid process. An end point of the supercritical fluid process may be determined based on a detected concentration of the target material.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 21, 2012
    Inventors: YONG JHIN CHO, Kun-Tack LEE, Hyo-San LEE, Young-Hoo KIM, Jung-Won LEE, Sang-Won BAE, Jung-Min OH
  • Patent number: 8187483
    Abstract: The present invention provides a method for improving the critical dimension performance during a plasma etching process of a photolithographic substrate having a thin film. A passivation film is deposited onto the photolithographic substrate using a first set of process conditions. The deposited film is etched from the photolithographic substrate using a second set of process conditions. An exposed surface of the photolithographic substrate is etched using a third set of process conditions. During the plasma processing of the photolithographic substrate, the critical dimension performance of the photolithographic substrate is monitored to insure that the target uniformity and feature widths are obtained by adjusting the deposition and etch plasma processing of the photolithographic substrate.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: May 29, 2012
    Inventors: Jason Plumhoff, Sunil Srinivasan, David Johnson, Russell Westerman
  • Patent number: 8182708
    Abstract: The present invention is to provide a method by which the waviness generated in a glass substrate surface during pre-polishing are removed and the glass substrate is finished so as to have a highly flat surface. The present invention relates a method of finishing a pre-polished glass substrate surface, the glass substrate being made of quartz glass containing a dopant and comprising SiO2 as a main component, the finishing method comprising: measuring a concentration distribution of the dopant contained in the glass substrate; and measuring a surface shape of the glass substrate in the pre-polished state, wherein conditions for processing the glass substrate surface are set for each part of the glass substrate based on the measurement results of the concentration distribution of the dopant and the surface shape of the glass substrate.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: May 22, 2012
    Assignee: Asahi Glass Company, Limited
    Inventor: Koji Otsuka
  • Patent number: 8175736
    Abstract: A processing system and method for chemical oxide removal (COR) is presented, wherein the processing system comprises a first treatment chamber and a second treatment chamber, wherein the first and second treatment chambers are coupled to one another. The first treatment chamber comprises a chemical treatment chamber that provides a temperature controlled chamber, and an independently temperature controlled substrate holder for supporting a substrate for chemical treatment. The substrate is exposed to a gaseous chemistry, such as HF/NH3, under controlled conditions including surface temperature and gas pressure. The second treatment chamber comprises a heat treatment chamber that provides a temperature controlled chamber, thermally insulated from the chemical treatment chamber. The heat treatment chamber provides a substrate holder for controlling the temperature of the substrate to thermally process the chemically treated surfaces on the substrate.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: May 8, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Masayuki Tomoyasu, Merritt Funk, Kevin A. Pinto, Masaya Odagiri, Lemuel Chen, Asao Yamashita, Akira Iwami, Hiroyuki Takahashi
  • Publication number: 20120091097
    Abstract: The invention provide apparatus and methods for creating gate structures on a substrate in real-time using Vacuum Ultra-Violet (VUV) data and Electron Energy Distribution Function (EEDƒ) data and associated (VUV/EEDƒ)-related procedures in (VUV/EEDƒ) etch systems. The (VUV/EEDƒ)-related procedures can include multi-layer-multi-step processing sequences and (VUV/EEDƒ)-related models that can include Multi-Input/Multi-Output (MIMO) models.
    Type: Application
    Filed: October 18, 2011
    Publication date: April 19, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Lee CHEN, Jianping ZHAO
  • Patent number: 8158016
    Abstract: Methods of operating an electromagnet of an ion source for generating an ion beam with a controllable ion current density distribution. The methods may include generating plasma in a discharge space of the ion source, generating and shaping a magnetic field in the discharge space by applying a current to an electromagnet that is effective to define a plasma density distribution, extracting an ion beam from the plasma, measuring a distribution profile for the ion beam density, and comparing the actual distribution profile with a desired distribution profile for the ion beam density. Based upon the comparison, the current applied to the electromagnet may be adjusted either manually or automatically to modify the magnetic field in the discharge space and, thereby, alter the plasma density distribution.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: April 17, 2012
    Assignee: Veeco Instruments, Inc.
    Inventors: Alan V. Hayes, Rustam Yevtukhov, Viktor Kanarov, Boris L. Druz
  • Patent number: 8158017
    Abstract: A method of detecting substrate arcing in a semiconductor plasma processing apparatus is provided. A substrate is placed on a substrate support in a reaction chamber of a plasma processing apparatus. Process gas is introduced into the reaction chamber. A plasma is generated from the process gas and the substrate is processed with the plasma. Intensities of real-time spectrometry signals of selected gas species produced in the reaction chamber during plasma processing are monitored. The selected gas species are generated by a substrate arcing event. The arcing event is detected when the intensities are above a threshold value.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: April 17, 2012
    Assignee: Lam Research Corporation
    Inventor: Eric Hudson
  • Patent number: 8158015
    Abstract: The present disclosure provides a mask and a method of determining etching times for etching the mask. In one embodiment, values for a main etching time and an over-etching time are determined simultaneously based on a desired critical dimension (CD) parameter and a desired phase parameter for the mask.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: April 17, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ming Lin, Joy Huang
  • Patent number: 8158526
    Abstract: Apparatus and method for endpoint detection are provided for photomask etching. The apparatus provides a plasma etch chamber with a substrate support member. The substrate support member has at least two optical components disposed therein for use in endpoint detection. Enhanced process monitoring for photomask etching are achieved by the use of various optical measurement techniques for monitoring at different locations of the photomask.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: April 17, 2012
    Assignee: Applied Materials, Inc.
    Inventor: Michael Grimbergen
  • Patent number: 8147705
    Abstract: When an ion beam 4 is to be extracted from an ion source 2 by using a gas containing boron trifluoride as an ion source gas 50 for supplying the gas into a plasma chamber 20 for the ion source 2, a bias voltage VB of a plasma electrode 31 with respect to the plasma chamber 20 for the ion source 2 is set to be positive by a bias circuit 64.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: April 3, 2012
    Assignee: Nissin Ion Equipment Co., Ltd.
    Inventors: Yutaka Inouchi, Syojiro Dohi, Yasunori Ando, Yasuhiro Matsuda
  • Patent number: 8137574
    Abstract: The present invention is to provide a processing method for manufacturing a highly flat and highly smooth glass substrate with good productivity. A highly flat and highly smooth glass substrate is obtained with good productivity by processing of a glass substrate, which comprises a step of measuring the surface shape of the glass substrate prior to processing, a step of processing the surface of the substrate by changing a processing condition for each site (first processing step), and a step of finish-polishing the surface of the glass substrate that has been subjected to the first processing step (second processing step).
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: March 20, 2012
    Assignee: Asahi Glass Company, Limited
    Inventors: Koji Otsuka, Hiroshi Kojima, Masabumi Ito
  • Publication number: 20120061350
    Abstract: A time-dependent substrate temperature to be applied during a plasma process is determined. The time-dependent substrate temperature at any given time is determined based on control of a sticking coefficient of a plasma constituent at the given time. A time-dependent temperature differential between an upper plasma boundary and a substrate to be applied during the plasma process is also determined. The time-dependent temperature differential at any given time is determined based on control of a flux of the plasma constituent directed toward the substrate at the given time. The time-dependent substrate temperature and time-dependent temperature differential are stored in a digital format suitable for use by a temperature control device defined and connected to direct temperature control of the upper plasma boundary and the substrate. A system is also provided for implementing upper plasma boundary and substrate temperature control during the plasma process.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 15, 2012
    Applicant: Lam Research Corporation
    Inventor: Rajinder Dhindsa
  • Patent number: 8133402
    Abstract: A pattern forming method includes performing a first resist development during a first time period to a substrate obtained by coating a resist film having a predetermined thickness onto a predetermined film to be etched, measuring the film thickness of the resist film after the first resist development, writing a predetermined pattern corrected in dimension on the basis of an amount of reduction in thickness of the resist film on the resist film by using a charged particle beam, performing a second resist development during a second time period which is longer than the first time period to the substrate after writing the pattern, and etching the predetermined film to be etched by using the resist film after the second resist development as a mask.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: March 13, 2012
    Assignee: NuFlare Technology, Inc.
    Inventors: Takayuki Ohnishi, Hirohito Anze
  • Patent number: 8129283
    Abstract: The invention provides a plasma processing apparatus and a dry etching method for etching a multilayered film structure having steps with high accuracy. The plasma processing apparatus comprises a vacuum reactor 107, a lower electrode 113 placed within a processing chamber of the vacuum reactor and having a wafer 112 to be etched mounted on the upper surface thereof, bias supplying units 118 and 120 for supplying high frequency power for forming a bias potential to the lower electrode 113, a gas supply means 111 for feeding reactive gas into the processing chamber, an electric field supplying means 101 through 103 for supplying a magnetic field for generating plasma in the processing chamber, and a control unit 127 for controlling the distribution of ion energy in the plasma being incident on the wafer 112 via the high frequency power.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: March 6, 2012
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Masahito Mori, Naoyuki Kofuji, Naoshi Itabashi
  • Publication number: 20120031876
    Abstract: A plasma source includes multiple ring plasma chambers, multiple primary windings, multiple ferrites and a control system. Each one of the primary windings is wrapped around an exterior one of the ring plasma chambers. Each one of the plurality of the ring plasma chamber passes through a respective portion of the plurality of ferrites. The control system is coupled to each of the ring plasma chambers. A system and method for generating and using a plasma are also described.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 9, 2012
    Inventors: Ali Shajii, Richard Gottscho, Souheil Benzerrouk, Andrew Cowe, Siddharth P. Nagarkatti, William R. Entley
  • Patent number: 8105499
    Abstract: A mask fixture for etching an item includes: a top fixture disposed over the item, including a reservoir centered within the top fixture for containing an etchant; a bottom fixture underneath the item to be etched including a recessed surface area centered within the bottom fixture; and an etch-resistant window for holding the item to be etched, the etch-resistant window disposed entirely within the recessed surface area. In addition, a small via centered within and intersecting both the top and bottom fixtures acts as a path for a high intensity light beam.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: January 31, 2012
    Assignee: International Business Macines Corporation
    Inventor: Arthur Wood Ellis
  • Patent number: 8083961
    Abstract: A method and system for treating a substrate using a ballistic electron beam is described, whereby the radial uniformity of the electron beam flux is adjusted by modulating the source radio frequency (RF) power. For example, a plasma processing system is described having a first RF power coupled to a lower electrode, which may support the substrate, a second RF power coupled to an upper electrode that opposes the lower electrode, and a negative high voltage direct current (DC) power coupled to the upper electrode to form the ballistic electron beam. The amplitude of the second RF power is modulated to affect changes in the uniformity of the ballistic electron beam flux.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: December 27, 2011
    Assignees: Tokyo Electron Limited, Texas Instruments Incorporated
    Inventors: Lee Chen, Ping Jiang
  • Patent number: 8080168
    Abstract: A confinement assembly for a semiconductor processing chamber is provided. The confinement assembly includes a plurality of confinement rings disposed over each other. Each of the plurality of confinement rings are separated by a space and each of the plurality of confinement rings have a plurality of holes defined therein. A plunger extending through aligned holes of corresponding confinement rings is provided. The plunger is moveable in a plane substantially orthogonal to the confinement rings. A proportional adjustment support is affixed to the plunger. The proportional adjustment support is configured to support the confinement rings, such that as the plunger moves in the plane, the space separating each of the plurality of confinement rings is proportionally adjusted. In one embodiment the proportional adjustment support is a bellows sleeve. A semiconductor processing chamber and a method for confining a plasma in an etch chamber having a plurality of confinement rings are provided.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: December 20, 2011
    Assignee: Lam Research Corporation
    Inventor: Peter Cirigliano
  • Patent number: 8075698
    Abstract: A substrate processing unit comprises a processing vessel for receiving a substrate, a cleaning gas supply system for supplying cleaning gas to the processing vessel so as to clean the interior of the processing vessel, an exhauster for exhausting the processing vessel, an operating state detector for detecting the operating state of the exhauster, and an end point detector for detecting the end point of the cleaning on the basis of the detection result from the operating state detector.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: December 13, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Kannan, Tadahiro Ishizaka, Yasuhiko Kojima, Yasuhiro Oshima, Takashi Shigeoka
  • Patent number: 8073646
    Abstract: A plasma processing apparatus includes a radio frequency generator capable of adjusting a target output power level based on the set power level and the offset level to output radio frequency power; a chamber in which a plasma process is performed; and a power detection unit for measuring radio frequency power level fed to the matching unit. The plasma processing apparatus further includes a generator control unit for controlling the radio frequency power such that the radio frequency power level fed to the matching unit reaches the set power level by calculating the offset level based on the difference between the set power level and the power level measured by the power detection unit and transmitting the set power level and the offset level in digital form to the data input terminal of the radio frequency generator.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: December 6, 2011
    Assignee: Tokyo Electron Limited
    Inventor: Kenji Sato
  • Publication number: 20110294234
    Abstract: Methods and devices for etching a device precursor are provided. For example, a method includes: providing a substrate, determining a temperature associated with the substrate, and etching a metal oxide layer of the substrate, wherein the etching is controlled based on the determined temperature.
    Type: Application
    Filed: June 7, 2010
    Publication date: December 1, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Niels KUHR, Ursula SCHMIDT
  • Publication number: 20110292546
    Abstract: A patterned recording media is formed from a master template that includes a data area and a timing track area having a final timing track. In order to form the final timing track, a first timing track is etched into master template and tested for accuracy by comparing the angular position of the master template to the timing track. If errors are detected in the timing track, the errors are used to create additional timing tracks which are etched into the master template. This process of improving the timing track is repeated until a final timing track is formed that has errors below a predetermined level. The timing tracks formed prior to the final timing track are removed and the master template is used to make stampers which are used to make patterned media disks.
    Type: Application
    Filed: May 25, 2010
    Publication date: December 1, 2011
    Applicant: Seagate Technology LLC
    Inventors: Dave Marcus Tung, Sundeep Chauhan, David Kuo, Shih-Fu Lee
  • Patent number: 8052886
    Abstract: A fluorine-containing compound gas, e.g., SF6 gas, is converted into a plasma and a silicon portion of an object to be processed is etched by the plasma. At the same time, using a light source having a peak intensity of light in a wavelength range of light absorption of a reaction product, e.g., SiF4, for which, to be more precise, ranges from 9 ?m to 10 ?m, the light is irradiated onto a surface of an object to be processed from the light source. The SiF4 molecules absorb the light, become activated and gain kinetic energy to be used in gaining an easy escape from a hole. As a consequence, an amount (a partial pressure) of fluorine radicals (F*) used as an etchant is increased and an etching rate of a silicon is increased.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: November 8, 2011
    Assignee: Tokyo Electron Limited
    Inventor: Koji Maruyama
  • Publication number: 20110266256
    Abstract: Methods for processing substrates in twin chamber processing systems having first and second process chambers and shared processing resources are provided herein. In some embodiments, a method may include providing a substrate to the first process chamber of the twin chamber processing system, wherein the first process chamber has a first processing volume that is independent from a second processing volume of the second process chamber; providing one or more processing resources from the shared processing resources to only the first processing volume of the first process chamber; and performing a process on the substrate in the first process chamber.
    Type: Application
    Filed: October 29, 2010
    Publication date: November 3, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventors: James P. Cruse, Dermot Cantwell, Ming Xu, Charles Hardy, Benjamin Schwarz, Kenneth S. Collins, Andrew Nguyen, Zhifeng Sui, Evans Lee
  • Patent number: 8048806
    Abstract: In some implementations, a method is provided in a plasma processing chamber for stabilizing etch-rate distributions during a process transition from one process step to another process step. The method includes performing a pre-transition compensation of at least one other process parameter so as to avoid unstable plasma states by inhibiting formation of a parasitic plasma during the process transition. In some implementations, a method is provided for processing a workpiece in plasma processing chamber, which includes inhibiting deviations from an expected etch-rate distribution by avoiding unstable plasma states during a process transition from one process step to another process step.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: November 1, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Michael C. Kutney, Daniel J. Hoffman, Gerardo A. Delgadino, Ezra R. Gold, Ashok Sinha, Xiaoye Zhao, Douglas H. Burns, Shawming Ma
  • Patent number: 8048327
    Abstract: In a plasma processing apparatus for processing an object to be processed by generating plasma in a processing chamber: a first electrode is arranged in the processing chamber and a second electrode is arranged to face the first electrode in the processing chamber; a first and a second power systems include a first and a second power supplies for supplying a first and a second powers to the first and the second electrodes, respectively; and a control unit controls both or either one of the first and the second power systems so as to apply a preprocessing voltage to the second electrode for a time period before plasma processing is performed on the object.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: November 1, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Akira Koshiishi, Masatoshi Kitano
  • Patent number: 8038897
    Abstract: A method for inspecting semiconductor wafers patterned by a photomask includes loading a first wafer and scanning a first image of the first wafer, loading a second wafer and scanning a second image of the second wafer, comparing the first and second images, and classifying a difference detected between the first and second images as a potential defect on the photomask. The potential defect includes a haze defect on the photomask.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: October 18, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Cheng Hung, Tsai-Sheng Gau
  • Patent number: 8038896
    Abstract: Plasma processing of plural substrates is performed in a plasma processing apparatus, which is provided with a plasma processing chamber having an antenna electrode and a lower electrode for placing and retaining the plural substrates in turn within the plasma processing chamber, a gas feeder for feeding processing gas into the processing chamber, a vacuum pump for discharging gas from the processing chamber via a vacuum valve, and a solenoid coil for forming a magnetic field within the processing chamber. At least one of the plural substrates is placed on the lower electrode, and the processing gas is fed into the processing chamber. RF power is fed to the antenna electrode via a matching network to produce a plasma within the processing chamber in which a magnetic field has been formed by the solenoid coil. This placing of at least one substrate and this feeding of the processing gas are then repeated until the plasma processing of all of the plural substrates is completed.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: October 18, 2011
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Eiji Ikegami, Shoji Ikuhara, Takeshi Shimada, Kenichi Kuwabara, Takao Arase, Tsuyoshi Matsumoto
  • Patent number: 8038892
    Abstract: The removal of partial areas of a coating (11, 12) on at least one surface (37, 38) of a glass pane (2) takes place by means of a plasma jet (14, 15) which emerges from a plasma nozzle (5, 6). The plasma nozzle (5, 6) is part of a plasma unit and two such plasma units are provided. Both of the plasma nozzles (5, 6) are oriented towards each other and form a pair of nozzles. A glass pane (2) is machined between both of the nozzles (5, 6). A distance sensor (23, 24) is arranged on both of the nozzles (5, 6), and said nozzles (5, 6) are positioned at the correct distance in relation to the surface (37, 38) of the glass pane (2).
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: October 18, 2011
    Assignee: Vetrotech Saint-Gobain (International) AG
    Inventors: Christian Müller, Norbert Schwankhaus, Friedrich Triebs, Udo Gelderie
  • Publication number: 20110239429
    Abstract: An embodiment of the present inventions provides a method for preconditioning a semiconductor fabrication component using a plasma etching process and an optional enhanced ultrasonic and/or megasonic preconditioning step in order to eliminate the need for a burn-in period typically associated with said components, as well as extend the useful life of the component during its wear-out phase.
    Type: Application
    Filed: June 2, 2009
    Publication date: October 6, 2011
    Applicant: POCO GRAPHITE, INC.
    Inventor: Wayne Hambek
  • Patent number: 8021563
    Abstract: A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the layer of material. The resist mask does not cover the trench. The layer of material is isotropically etched. An etch depth may be determined from a characteristic of etching of the material underneath the mask. Such a method may be used for forming SGT structures. The wafer may comprise a layer of material disposed on at least a portion of a surface of semiconductor wafer; a resist mask comprising an angle-shaped test portion disposed over a portion of the layer of material; and a ruler marking on the surface of the substrate proximate the test portion.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: September 20, 2011
    Assignee: Alpha & Omega Semiconductor, Ltd
    Inventors: Yingying Lou, Tiesheng Li, Yu Wang, Anup Bhalla
  • Patent number: 8021566
    Abstract: An apparatus and method suitable for the pre-conditioning of a polishing pad on a CMP apparatus prior to the polishing of production wafers on the apparatus. The apparatus includes a pre-conditioning arm on which is mounted an ingot of suitable material. In use, the ingot is pressed against the polishing surface of the rotating polishing pad for a selected period of time to increase the temperature of the polishing surface by friction. The pre-conditioned polishing pad facilitates uniform polishing rates of production semiconductor wafers subsequently polished on the apparatus.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: September 20, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Che Chuang, Wen-Chih Chiou, Hsin-Hsien Lu, Liang-Guang Chen
  • Patent number: 8021564
    Abstract: A method for detecting an end point of a resist peeling process in which a resist is gasified to be peeled off by producing hydrogen radicals by catalytic cracking reaction where a hydrogen-containing gas contacts with a high-temperature catalyst, and contacting the produced hydrogen radicals with a resist on a substrate, includes monitoring one or more parameters indicating a state of the catalyst and detecting the end point of the resist peeling process based on variations of the monitored parameters. The hydrogen-containing gas may be a H2 gas. The parameters indicating the state of the catalyst may be one or more electrical parameters when a power is supplied to the catalyst. Further, the catalyst may be a filament made of a high melting point metal.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: September 20, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Isamu Sakuragi, Kazuhiro Kubota
  • Patent number: 8017029
    Abstract: A plasma etch method includes simultaneously illuminating an array of plural locations on front surface of the workpiece through the backside of the workpiece with light of a wavelength range for which the workpiece is transparent, while viewing light reflected from the array of plural locations to the backside of the workpiece. The method further includes determining plural etch depths at the array of locations from the light reflected from the array of locations on the front side of the workpiece, and deducing from the plural etch depths a spatial distribution of etch rate across the array of locations. The method also includes changing the etch rate distribution by adjusting a tunable element of the reactor.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: September 13, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Madhavi R. Chandrachood, Michael N. Grimbergen, Khiem K. Nguyen, Richard Lewington, Ibrahim M. Ibrahim, Sheeba J. Panayil, Ajay Kumar
  • Patent number: 8012366
    Abstract: A method is provided for defining a pattern on a workpiece such as a transparent substrate or mask or a workpiece that is at least transparent within a range of optical wavelengths. The method includes defining a photoresist pattern on the top surface of the mask, the pattern including a periodic structure having a periodic spacing between elements of the structure. The method further includes placing the mask on a support pedestal in a plasma reactor chamber and generating a plasma in the chamber to etch the top surface of the mask through openings in the photoresist pattern. The method also includes transmitting light through the pedestal and through the bottom surface of the mask, while viewing through the support pedestal light reflected from the periodic structure and detecting an interference pattern in the reflected light. The method further includes determining from the interference pattern a depth to which periodic structure has been etched in the top surface.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: September 6, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Richard Lewington, Michael N. Grimbergen, Khiem K. Nguyen, Darin Bivens, Madhavi R. Chandrachood, Ajay Kumar
  • Publication number: 20110186545
    Abstract: Methods and systems for controlling temperatures in plasma processing chamber with reduced controller response times and increased stability. Temperature control is based at least in part on a feedforward control signal derived from a plasma power input into the processing chamber. A feedforward control signal compensating disturbances in the temperature attributable to the plasma power may be combined with a feedback control signal counteracting error between a measured and desired temperature.
    Type: Application
    Filed: October 15, 2010
    Publication date: August 4, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Chetan MAHADESWARASWAMY, Walter R. MERRY, Sergio Fukuda SHOJI, Chunlei ZHANG, Yashaswini B. PATTAR, Duy D. NGUYEN, Tina TSONG, Shane C. NEVIL, Douglas A. BUCHBERGER, JR., Fernando M. SILVEIRA, Brad L. MAYS, Kartik RAMASWAMY, Hamid NOORBAKHSH
  • Publication number: 20110174776
    Abstract: A plasma processing apparatus (100) includes: a plasma generation means for generating a plasma in a processing chamber (1); a measurement section (60) for measuring an integrated value of the particle number of an active species contained in the plasma and moving toward a processing object (wafer W); and a control section (50) for controlling the apparatus in such a manner as to terminate plasma processing when the measured integrated value has reached a set value. The measurement section (60) measures the particle number of the active species by emitting a predetermined laser light from a light source section (61) toward the plasma, and receiving the laser light in a detection section (63) provided with a VUV monochromator.
    Type: Application
    Filed: August 26, 2008
    Publication date: July 21, 2011
    Applicant: Tokyo Electron Limited
    Inventors: Yoshiro Kabe, Kinya Ota, Junichi Kitagawa
  • Patent number: 7981306
    Abstract: Generating drive signals of at least two RF power generators which supply RF power to a plasma process, in which at least two drive signals, each driving one RF power generator, are generated in an RF generator driver. Each drive signal is generated by a respective function generator, such as a digital sine generator, of the generator driver.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: July 19, 2011
    Assignee: HUETTINGER Elektronik GmbH + Co. KG
    Inventors: Manfred Blattner, Markus Winterhalter, Ekkehard Mann
  • Patent number: 7981305
    Abstract: A method for forming high density emission elements and field emission displays formed according to the method. Oxygen and a silicon etchant are introduced into a plasma etching chamber containing a silicon substrate. The oxygen reacts with the silicon surface to form regions of silicon dioxide, while the silicon etchant etches the silicon to form the emission elements. The silicon dioxide regions mask the underlying silicon during the silicon etch process. High density and high aspect ratio emission elements are formed without using photolithographic processes. The emission elements formed according to the present invention provide a more uniform emission of electrons. Further, a display incorporating emission elements formed according to the present invention provides increased brightness. The reliability of the display is increased due to the use of a plurality of emission elements to supply electrons for stimulating the phosphor substrate material to produce the image.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: July 19, 2011
    Assignee: Agere Systems Inc.
    Inventors: Seong Jin Koh, Gerald W. Gibson, Jr.
  • Publication number: 20110168671
    Abstract: In accordance with an embodiment of the invention, a step in a fabrication process can be conducted so as to determine when the process has reached an end point. End point detection can be performed by detecting when a operating process condition changes. For example, in one embodiment, a step in a fabrication process (e.g., an etching step) can be conducted in a chamber by varying a position of a throttle valve connected to the chamber so as to maintain a desired pressure within the chamber. In such method, it can be determined when the etching step has reached an end point by detecting when a signal representative of the throttle valve position changes in a particular way which matches an expected signature. In another embodiment, a step in a fabrication process can be conducted in a chamber by maintaining a desired flow within the chamber, such as by controlling a throttle valve, and allowing the pressure within the chamber to vary.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 14, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John M. Yamartino, Anthony D. Lisi
  • Publication number: 20110165382
    Abstract: This invention presents a method for the fabrication of periodic nanostructures on polymeric surfaces by means of plasma processing, which method comprises the following steps: (i) provision of a homogeneous organic polymer (such as PMMA, or PET, or PEEK, or PS, or PE, or COC) or inorganic polymer (such as PDMS or ORMOCER); (ii) exposure of the polymer to an etching plasma such as oxygen (O2) or sulphur hexafluoride (SF6) or a mixture of oxygen (O2) and sulphur hexafluoride (SF6), or mixtures of etching gases with inert gases such as any Noble gas (Ar, He, Ne, Xe).
    Type: Application
    Filed: June 15, 2009
    Publication date: July 7, 2011
    Applicant: NATIONAL CENTER FOR SCIENTIFIC RESEARCH "DEMOKRITOS"
    Inventors: Evangelos Gogolides, Aagelike Tserepi, Vassilios Constantoudis, Nikolaos Vourdas, Georgios Boulousis, Maria-Elenma Vlachopoulou LACHOPOULOU, Aikaterini Tsougeni, Dimitrios Kontziampasis
  • Patent number: 7967995
    Abstract: The invention provides a method of processing a substrate using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more masking layer creation procedures, one or more pre-processing measurement procedures, one or more Partial-Etch (P-E) procedures, one or more Final-Etch (F-E) procedures, and one or more post-processing measurement procedures.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: June 28, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Merritt Funk, Radha Sundararajan, Hyung Joo Lee, Daniel Prager, Asao Yamashita
  • Publication number: 20110139749
    Abstract: A substrate processing method which is capable of enhancing productivity in manufacturing product substrates. In process chambers of an etching apparatus, etching is carried out on a substrate as an object to be processed, and dummy processing is carried out on at least one non-product substrate before execution of the etching. A host computer determines whether or not the dummy processing is to be executed. The host computer determines whether or not the interior of each of the process chambers and is in a stable state, and omits the execution of the dummy processing when it is determined that it is in the stable state.
    Type: Application
    Filed: February 24, 2011
    Publication date: June 16, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Satoshi YAMAZAKI, Mitsuru Hashimoto
  • Patent number: 7959819
    Abstract: The present invention provides a method and an apparatus for reducing aspect ratio dependent etching that is observed when plasma etching deep trenches in a semiconductor substrate through an alternating deposition/etch process. A plurality of different sized features on the substrate are monitored in real time during the alternating deposition/etch process. Then, based on the information received from the monitor, at least one process parameter is adjusted in the alternating deposition/etch process to achieve equivalent etch depths of at least two different sized features on the substrate.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: June 14, 2011
    Inventors: Shouliang Lai, David Johnson, Russell Westerman