Substrate Contains Silicon Or Silicon Compound Patents (Class 216/99)
  • Patent number: 8523426
    Abstract: The invention relates to a one-piece regulating member including a balance cooperating with a hairspring made in a layer of silicon-based material and including a balance spring coaxially mounted on a collet. According to the invention, the collet includes one extending part that projects from the balance spring and which is made in a second layer of silicon-based material and is secured to the balance.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: September 3, 2013
    Assignee: Nivarox-FAR S.A.
    Inventors: Pierre-André Bühler, Marco Verardo, Thierry Conus, Jean-Philippe Thiebaud, Jean-Bernard Peters, Pierre Cusin
  • Patent number: 8518279
    Abstract: A method for providing a capping layer configured for an energy assisted magnetic recording (EAMR) head including at least one slider. The method comprises etching a substrate having a top surface using an etch to form a trench in the substrate, the trench having a first surface at a first angle from the top surface and a second surface having a second angle from the top surface. The method further comprises providing a protective coating exposing the second surface and covering the first surface, removing a portion of the substrate including the second surface to form a laser cavity within the substrate configured to fit a laser therein, and providing a reflective layer on the first surface to form a mirror, the cavity and mirror being configured for alignment of the laser to the laser cavity and to the mirror and for bonding the laser to the laser cavity.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: August 27, 2013
    Assignee: Western Digital (Fremont), LLC
    Inventors: Lei Wang, Pezhman Monadgemi
  • Patent number: 8518275
    Abstract: Methods for fabricating sub-lithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: August 27, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Donald Westmoreland
  • Patent number: 8512587
    Abstract: Etch solutions for selectively etching doped oxide materials in the presence of silicon nitride, titanium nitride, and silicon materials, and methods utilizing the etch solutions, for example, in construction of container capacitor constructions are provided. The etch solutions are formulated as a mixture of hydrofluoric acid and an organic acid having a dielectric constant less than water, optionally, with an inorganic acid, and a pH of 1 or less.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: August 20, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Niraj Rana, Prashant Raghu, Kevin Torek
  • Patent number: 8513125
    Abstract: A method for manufacturing a device comprising a structure with nanowires based on a semiconducting material such as Si and another structure with nanowires based on another semiconducting material such as SiGe, and is notably applied to the manufacturing of transistors.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: August 20, 2013
    Assignee: Commissariat a l'energie atomique et aux alternatives
    Inventors: Emeline Saracco, Jean-Francois Damlencourt, Michel Heitzmann
  • Patent number: 8512588
    Abstract: A method of fabricating a nanoporous membrane filter having a uniform array of nanopores etch-formed in a thin film structure (e.g. (100)-oriented single crystal silicon) having a predetermined thickness, by (a) using interferometric lithography to create an etch pattern comprising a plurality array of unit patterns having a predetermined width/diameter, (b) using the etch pattern to etch frustum-shaped cavities or pits in the thin film structure such that the dimension of the frustum floors of the cavities are substantially equal to a desired pore size based on the predetermined thickness of the thin film structure and the predetermined width/diameter of the unit patterns, and (c) removing the frustum floors at a boundary plane of the thin film structure to expose, open, and thereby create the nanopores substantially having the desired pore size.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: August 20, 2013
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Joseph W. Tringe, Rodney L. Balhorn, Saleem Zaidi
  • Patent number: 8506832
    Abstract: Example embodiments are directed to a wafer dividing apparatus and method thereof. The wafer dividing apparatus includes a chuck unit having upper and lower chucks, a cutting wire that is provided in a space between the upper and lower chucks to cut a wafer and driven by a first driving unit, and an etchant supplying nozzle supplying etchant to a groove of the wafer, which is formed by the cutting wire.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: August 13, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hotae Jin, Seonju Oh, HeuiSeog Kim
  • Publication number: 20130199539
    Abstract: The present invention is directed to methods for inhibiting growth of bacteria and to nanometer scale surfaces having antibacterial properties.
    Type: Application
    Filed: April 11, 2011
    Publication date: August 8, 2013
    Applicant: BROWN UNIVERSITY
    Inventor: Thomas J. Webster
  • Patent number: 8497215
    Abstract: The present invention relates to a method for the wet-chemical edge deletion of solar cells. An etching paste is applied to the edge of a solar cell substrate surface and after the reaction is complete, the paste residue is removed. Optionally, the substrate surface is cleaned and dried. The etching paste comprises 85% H3PO4, NH4HF2 and 65% HNO3 in a ratio in the range from 7:1:1.5 to 10:1:3.5, based on the weight.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: July 30, 2013
    Assignee: Merck Patent GmbH
    Inventors: Oliver Doll, Ingo Koehler
  • Patent number: 8491809
    Abstract: A process for producing an aluminum wheel includes a cleaning step, in which the surface of the aluminum wheel is chemically etched with an alkali cleaning liquid which contains an alkali builder, an organic builder, and a chelating agent to such an extent that the Si atomic ratio of metal Si to oxide Si is from 0.01 to 9, and a shot blast treatment step can be omitted for cleaning the surface of the aluminum wheel.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: July 23, 2013
    Assignees: Central Motor Wheel Co., Ltd., Nihon Parkerizing Co., Ltd.
    Inventors: Takeshi Yamada, Yoshitomo Fujii, Hiroyuki Sato, Soichi Nomoto
  • Patent number: 8486282
    Abstract: Surface texturing of the transparent conductive oxide (TCO) front contact of a thin film photovoltaic (TFPV) solar cell is needed to enhance the light-trapping capability of the TFPV solar cells and thus improving the solar cell efficiency. Embodiments of the current invention describe chemical formulations and methods for the wet etching of the TCO. The formulations and methods may be optimized to tune the surface texturing of the TCO as desired.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: July 16, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Zhi-Wen Sun, Nitin Kumar, Guizhen Zhang, Minh Anh Nguyen, Nikhil Kalyankar
  • Patent number: 8475666
    Abstract: A toughening agent composition for increasing the hydrophobicity of an organosilicate glass dielectric film when applied to said film. It includes a component capable of alkylating or arylating silanol moieties of the organosilicate glass dielectric film via silylation, and an activating agent selected from the group consisting of an amine, an onium compound and an alkali metal hydroxide.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: July 2, 2013
    Assignee: Honeywell International Inc.
    Inventors: Teresa A. Ramos, Robert R. Roth, Anil S. Bhanap, Paul G. Apen, Denis H. Endisch, Brian J. Daniels, Ananth Naman, Nancy Iwamoto, Roger Y. Leung
  • Publication number: 20130165365
    Abstract: There are provided a processing liquid for suppressing pattern collapse of a microstructure which includes at least one compound selected from the group consisting of an imidazolium halide containing an alkyl group having 12, 14 or 16 carbon atoms, a pyridinium halide containing an alkyl group having 14 or 16 carbon atoms and an ammonium halide containing an alkyl group having 16 or 18 carbon atoms, and water; and a method for producing a microstructure formed of silicon oxide using the processing liquid.
    Type: Application
    Filed: July 14, 2011
    Publication date: June 27, 2013
    Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Hiroshi Matsunaga, Masaru Ohto
  • Patent number: 8466067
    Abstract: Processes for forming high density gap-filling silicon oxide on a patterned substrate are described. The processes increase the density of gap-filling silicon oxide particularly in narrow trenches. The density may also be increased in wide trenches and recessed open areas. The densities of the gap-filling silicon oxide in the narrow and wide trenches/open areas become more similar following the treatment which allows the etch rates to match more closely. This effect may also be described as a reduction in the pattern loading effect. The process involves forming then planarizing silicon oxide. Planarization exposes a new dielectric interface disposed closer to the narrow trenches. The newly exposed interface facilitates a densification treatment by annealing and/or exposing the planarized surface to a plasma.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: June 18, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Jingmei Liang, Nitin K. Ingle, Shankar Venkataraman
  • Patent number: 8465662
    Abstract: Provided is an etching composition for electively removing silicon dioxide at a high etch rate, more particularly, a composition for wet etching of silicon dioxide, including 1 to 40 wt % of hydrogen fluoride (HF); 5 to 40 wt % of ammonium hydrogen fluoride (NH4HF2); and water, and further including a surfactant to improve selectivity of the silicon dioxide and a silicon nitride film. Since the composition for wet etching of silicon dioxide has the high etch selectivity of the silicon dioxide to the silicon nitride film, it is useful for selectively removing silicon dioxide.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: June 18, 2013
    Assignee: Techno Semichem Co., Ltd.
    Inventors: Jung Hun Lim, Dae Hyun Kim, Chang Jin Yoo, Seong Hwan Park
  • Patent number: 8460561
    Abstract: The present invention provides a crystal oscillator piece in which the cross section of its vibrating tine, while not symmetrical in shape, has a principal axis that is oriented parallel to an X axis to suppress the generation of leakage vibration, and a method for manufacturing such a crystal oscillator piece.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: June 11, 2013
    Assignee: Citizen Holdings Co., Ltd.
    Inventor: Akiko Katoh
  • Patent number: 8461057
    Abstract: The present invention relates to a novel process for producing textured surfaces on multicrystalline, tricrystalline and monocrystalline silicon surfaces of solar cells or on silicon substrates which are used for photovoltaic purposes. It relates in particular to an etching process and an etching agent for producing a textured surface on a silicon substrate.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: June 11, 2013
    Assignee: BASF Aktiengesellschaft
    Inventors: Arnim Kuebelbeck, Claudia Zielinski, Thomas Goelzenleuchter
  • Patent number: 8454844
    Abstract: A method for processing a wafer to form a plurality of hollow microneedles projecting from a substrate includes forming, by use of a dry etching process, a number of groups of recessed features, each including at least one slot deployed to form an open shape having an included area and at least one hole located within the included area. The internal surfaces of the holes and the slots are then coated with a protective layer. An anisotropic wet etching process is then performed in such a manner as to remove material from outside the included areas while leaving a projecting feature within each of the included areas. The protective layer is then removed to reveal the microneedles.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: June 4, 2013
    Assignee: NanoPass Technologies Ltd.
    Inventors: Yehoshua Yeshurun, Mier Hefetz, Meint De Boer, Erwin J W Berenschot, Hans Gardeniers
  • Patent number: 8455268
    Abstract: Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: June 4, 2013
    Assignee: Spansion LLC
    Inventors: Chungho Lee, Hiroyuki Kinoshita, Kuo-Tung Chang, Rinji Sugino, Chi Chang, Huaqiang Wu
  • Publication number: 20130122717
    Abstract: A method for treating silicon to form pillars, especially for use as the active anode material in Li-ion batteries, is disclosed. The process is simple to operate on a commercial scale since it uses a solution containing only a small number of ingredients whose concentration needs to be controlled and it can be cheaper to operate than previous processes. The solution includes: 0.01 to 5M HF 0.002 to 0.2M of metal ions capable of nucleating on and forming a porous layer comprising regions of elemental metal on the silicon surface; 0.001 to 0.7M of an oxidant selected from the group O2, O3, H2O2, the acid, ammonium or alkali metal salt of NO3?, S2O82?, NO2?, B4O72? and ClO4? or a mixture thereof. The treated silicon is suitably removed from the solution.
    Type: Application
    Filed: April 8, 2011
    Publication date: May 16, 2013
    Applicant: NEXEON LIMITED
    Inventors: Mino Green, Feng-Ming Liu, Yuxiong Jiang, Valerie Elizabeth Dawn Stevens, Benjamin Odarkwei Mills-Lamptey
  • Patent number: 8440573
    Abstract: A method is provided for processing a wafer used in fabricating semiconductor devices. The method can comprise forming high-aspect ratio features on the wafer, which is followed by wet processing and drying. During drying, pattern collapse can occur. This pattern collapse can be repaired to allow for additional processing of the wafer. In some instance, pattern collapse can be repaired via etching where the etching breaks bonds that can have formed during pattern collapse.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: May 14, 2013
    Assignee: Lam Research Corporation
    Inventors: Katrina Mikhaylichenko, Denis Syomin, Qian Fu, Glenn W. Gale, Shenjian Liu, Mark H. Wilcoxson
  • Patent number: 8435900
    Abstract: The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 7, 2013
    Assignee: Semiconductor Manufacturing International Corp.
    Inventors: Qun Shao, Zhongshan Hong
  • Publication number: 20130092657
    Abstract: The present invention relates to a novel etching media in the form of printable, homogeneous etching pastes with non-Newtonian flow properties for the improved etching of inorganic oxides and silicon surfaces and which allow to prepare smaller features.
    Type: Application
    Filed: May 17, 2011
    Publication date: April 18, 2013
    Applicants: NANO TERRA, INC., MERCK PATENT GESELLSCHAFT MIT BESCHRANKTER HAFTUNG
    Inventors: Jennifer Gillies, Ralf Kuegler, Eric Stern, Brian Mayers, Patrick Reust, Lindsay Hunting
  • Patent number: 8415254
    Abstract: A method is provided for fabricating a semiconductor device. The method includes removing a silicon material from a gate structure located on a substrate through a cycle including: etching the silicon material to remove a portion thereof, where the substrate is spun at a spin rate, applying a cleaning agent to the substrate, and drying the substrate; and repeating the cycle, where a subsequent cycle includes a subsequent spin rate for spinning the substrate during the etching and where the subsequent spin rate does not exceed the spin rate of the previous cycle.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: April 9, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matt Yeh, Fan-Yi Hsu, Shun Wu Lin, Shu-Yuan Ku, Hui Ouyang
  • Patent number: 8409449
    Abstract: Methods for fabricating sub-lithographic, nanoscale linear microchannel arrays over surfaces without defined features utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Embodiments of the methods use a multi-layer induced ordering approach to align lamellar films to an underlying base film within trenches, and localized heating to anneal the lamellar-phase block copolymer film overlying the trenches and outwardly over the remaining surface.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: April 2, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Eugene P. Marsh
  • Patent number: 8404124
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: March 26, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Donald Westmoreland, Gurtej Sandhu
  • Patent number: 8398867
    Abstract: Method for producing a probe for atomic force microscopy with a silicon nitride cantilever and an integrated single crystal silicon tetrahedral tip with high resonant frequencies and low spring constants intended for high speed AFM imaging.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: March 19, 2013
    Inventor: Chung Hoon Lee
  • Patent number: 8366954
    Abstract: Treating thin film amorphous or mono- or multi-crystalline silicon wafer substrate for use in a photovoltaic cell, the wafer substrate having at least one of a pn- or np junction and a partial phosphosilicate or borosilicate glass layer on a top surface of the wafer substrate, to increase at least one of (a) the sheet resistance of he wafer and (b) the power density level of the photovoltaic cell made from said wafer. The treatment solution being an acidic treatment solution of a buffered oxide etch (BOE) solution of at least one tetraalkylammonium hydroxide, acetic acid, at least one non-ionic surfactant, at least one metal chelating agent, a metal free source of ammonia, a metal free source, of fluoride ions, and water, mixed with an oxidizer solution and optionally water.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: February 5, 2013
    Assignee: Avantor Performance Materials, BV
    Inventors: Joannes T. V. Hoogboom, Johannes A. E. Oosterholt, Sabrina Ritmeijer, Lucas M. H. Groenewoud
  • Patent number: 8349739
    Abstract: The present disclosure provides a method for etching a substrate. The method includes forming a resist pattern on the substrate; applying an etching chemical fluid to the substrate, wherein the etching chemical fluid includes a diffusion control material; removing the etching chemical fluid; and removing the resist pattern.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: January 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ching-Yu Chang
  • Patent number: 8343873
    Abstract: A method for producing a semiconductor wafer includes a number of steps in order including a bilateral material-removing process followed by rounding off an edge of the wafer and grinding front and back sides of the wafer by holding one side and grinding the other. The front and back arc then polished with a polishing cloth including bound abrasives and subsequently treated with an etching medium to carry out a material removal of no more than 1 ?m on each side. The front side is then polished using a polishing cloth including bound abrasives and the back side is simultaneously polished using a polishing cloth free of abrasives while a polish with abrasives is provided. The edge is then polished followed by polishing the back with a polishing cloth including bound abrasives and simultaneously polishing the front with a cloth free of abrasives while a polish including abrasives is provided.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: January 1, 2013
    Assignee: Siltronic AG
    Inventor: Juergen Schwandner
  • Patent number: 8343369
    Abstract: A method of producing a MEMS device removes the bottom side of a device wafer after its movable structure is formed. To that end, the method provides the device wafer, which has an initial bottom side. Next, the method forms the movable structure on the device wafer, and then removes substantially the entire initial bottom side of the device wafer. Removal of the entire initial bottom side effectively forms a final bottom side.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: January 1, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Manolo G. Mena, Elmer S. Lacsamana, William A. Webster, Lawrence E. Felton
  • Patent number: 8333882
    Abstract: The method of polishing a work is capable of reducing a polishing cost, polishing a surface of the work with high polishing accuracy and easily disposing used polishing liquid and used washing liquid. The method comprises the steps of: pressing the work onto a polishing member; feeding polishing liquid; and relatively moving the work with respect to the polishing member. Electrolytic reduced water produced by electrolyzing an electrolyte solution is used as the polishing liquid.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: December 18, 2012
    Assignee: Fujikoshi Machinery Corp.
    Inventors: Unkai Sato, Koichiro Ichikawa, Yoshinobu Nishimoto, Yoshio Nakamura, Tsuyoshi Hasegawa, Masumi Iihama
  • Patent number: 8329046
    Abstract: Methods for performing damage etch and texturing of single crystal silicon substrates, particularly for use as solar cells or photovoltaic cells. Damage etch with a TMAH solution followed by texturing using solution of KOH or NaOH mixed with IPA is particularly advantageous. The substitution of some of the IPA with ethylene glycol further improves results. Also disclosed is a process that combines both damage etch and texturing etch into a single step.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: December 11, 2012
    Assignee: Asia Union Electronic Chemical Corporation
    Inventors: Curtis Dove, Cindy Dutton, Greg Bauer, Christopher Myers, Mehdi Balooch
  • Patent number: 8324113
    Abstract: A silicon processing method includes: forming a mask pattern on a principal plane of a single-crystal silicon substrate; and applying crystal anisotropic etching to the principal surface to form a structure including a (111) surface and a crystal surface equivalent thereto and having width W1 and length L1. The principal plane includes a (100) surface and a crystal surface equivalent thereto or a (110) surface and a crystal surface equivalent thereto. A determining section for determining the width W1 of the structure is formed in the mask pattern. The width of the determining section for the width W1 of the mask pattern is width W2. The width of the mask pattern other than the determining section is larger than the width W2 over a length direction of the mask pattern.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: December 4, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takahisa Kato, Yasuhiro Shimada
  • Patent number: 8298435
    Abstract: An etching method. The method includes etching a first plurality of silicon wafers in a first enchant, each silicon wafer having SiO2 and Si3N4 deposited thereon, where the etching includes dissolving a quantity of the SiO2 and a quantity of the Si3N4 in the first echant. A quantity of insoluble SiO2 precipitates. A ratio of a first etch rate of Si3N4 to a first etch rate of SiO2 is determined to be less than a predetermined threshold. A portion of the first etchant is combined with a second etchant to form a conditioned etchant. A second plurality of silicon wafers is etched in the conditioned etchant. A ratio of a second etch rate of Si3N4 to a second etch rate of SiO2 in the conditioned etchant is greater than the threshold. A method for exchanging an etching bath solution and a method for forming a selective etchant are also disclosed.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Russell Herbert Arndt, Paul F. Findeis, Charles Jesse Taft
  • Patent number: 8287747
    Abstract: A method of processing a substrate includes the steps of providing a silicon substrate that has an etching mask layer with an opening portion at a first surface thereof and has plane orientation of {100} with the surface of the silicon being exposed from the opening portion; preparing a recessed portion that faces from the first surface to a second surface, opposite to the first surface, in the opening portion of the silicon substrate; and forming a penetration port that passes through the first surface and the second surface of the silicon substrate by executing crystalline anisotropic etching in the silicon substrate using an etching liquid in which an etching rate for etching a (100) surface of silicon is higher than an etching rate for etching a (110) surface of silicon, from the recessed portion of the silicon substrate toward the second surface.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: October 16, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keisuke Kishimoto, Taichi Yonemoto
  • Patent number: 8283260
    Abstract: A method for preparing an interlayer dielectric to minimize damage to the interlayer's dielectric properties, the method comprising the steps of: depositing a layer of a silicon-containing dielectric material onto a substrate, wherein the layer has a first dielectric constant and wherein the layer has at least one surface; providing an etched pattern in the layer by a method that includes at least one etch process and exposure to a wet chemical composition to provide an etched layer, wherein the etched layer has a second dielectric constant, and wherein the wet chemical composition contributes from 0 to 40% of the second dielectric constant; contacting the at least one surface of the layer with a silicon-containing fluid; optionally removing a first portion of the silicon-containing fluid such that a second portion of the silicon-containing fluid remains in contact with the at least one surface of the layer; and exposing the at least one surface of the layer to UV radiation and thermal energy, wherein the lay
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: October 9, 2012
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Scott Jeffrey Weigel, Mark Leonard O'Neill, Mary Kathryn Haas, Laura M. Matz, Glenn Michael Mitchell, Aiping Wu, Raymond Nicholas Vrtis, John Giles Langan
  • Patent number: 8246847
    Abstract: There are provided an aqueous solution for separation of a conductive ceramics sintered body in which a conductive ceramic sintered body separated form a glass can be collected in a recyclable condition, and a separating method therefor, and an aqueous solution for separation with which a dark ceramics sintered body, a conductive ceramics sintered body and a glass are separately collected from a glass with a dark ceramics sintered body in which a conductive ceramics sintered body is formed on the dark ceramics sintered body, and a separating method therefor. A treatment liquid having an etching ability for at least one of a glass and a conductive ceramic sintered body is prepared as an aqueous solution 20 for separation of the conductive ceramics sintered body, then the aqueous solution 20 for separation is filled in a container 11, and a glass with a conductive ceramics sintered body 30 is immersed into the aqueous solution 20 for separation in the container 11.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: August 21, 2012
    Assignee: Nippon Sheet Glass Company, Limited
    Inventors: Masahiro Hori, Kazuishi Mitani, Yasuhiro Saito, Nobuyuki Takatsuki, Kyouichi Shukuri, Shunji Kuramoto
  • Publication number: 20120187088
    Abstract: There are provided a liquid processing method and a liquid processing apparatus capable of providing a high etching rate and a high etching selectivity for silicon nitride against silicon oxide, and a storage medium storing the method thereon. In the method for etching, by an etching solution, a substrate on which silicon nitride and silicon oxide are exposed, the etching solution is produced by mixing a fluorine ion source material, water and a boiling point adjusting agent; the produced etching solution is heated to a substrate processing temperature equal to or higher than 140° C.; after a temperature of the etching solution reaches the substrate processing temperature, the temperature of the etching solution is maintained at the substrate processing temperature for a first preset time; and after a lapse of the first preset time, the substrate is etched by the etching solution maintained at the substrate processing temperature.
    Type: Application
    Filed: January 23, 2012
    Publication date: July 26, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hiroki Ohno, Takehiko Orii
  • Patent number: 8226840
    Abstract: Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: July 24, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • Patent number: 8221642
    Abstract: A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a dielectric layer overlying another dielectric layer, contacting the substrate at a first temperature with an acid solution exhibiting a positive etch selectivity at the first temperature, and then contacting the substrate at a second temperature with an acid solution exhibiting a positive etch selectivity at the second temperature. The dielectric layers exhibit different etch rates when etched at the first and second temperatures. The first and second acid solutions may contain phosphoric acid. The first dielectric layer may be silicon nitride and the second dielectric layer may be silicon oxide. Under these conditions, the first temperature may be about 175° C. and the second temperature may be about 155° C.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: July 17, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Don L. Yates
  • Patent number: 8216434
    Abstract: A micromachined sensor for measuring vascular parameters, such as fluid shear stress, includes a substrate having a front-side surface, and a backside surface opposite the front-side surface. The sensor includes a diaphragm overlying a cavity etched within the substrate, and a heat sensing element disposed on the front-side surface of the substrate and on top of the cavity and the diaphragm. The heat sensing element is electrically couplable to electrode leads formed on the backside surface of the substrate. The sensor includes an electronic system connected to the backside surface and configured to measure a change in heat convection from the sensing element to surrounding fluid when the sensing element is heated by applying an electric current thereto, and further configured to derive from the change in heat convection vascular parameters such as the shear stress of fluid flowing past the sensing element.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: July 10, 2012
    Assignee: University of Southern California
    Inventors: Tzung K. Hsiai, Gopikrishnan Soundararajan, Eun Sok Kim, Hongyu Yu, Mahsa Rouhanizadeh, Christina Tiantian Lin
  • Patent number: 8211320
    Abstract: A carbon nanotube device includes a flexible substrate and a patterned carbon nanotube layer. The flexible substrate defines a plurality of recesses. The patterned carbon nanotube layer is formed on the flexible substrate. The carbon nanotube layer includes a plurality of carbon nanotube arrays. Each carbon nanotube array is fixedly attached in the corresponding recess.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: July 3, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Shao-Kai Pei
  • Patent number: 8187487
    Abstract: A method for removing (e.g., etching) different dielectric materials from a semiconductor substrate includes exposing the semiconductor substrate to a solution at temperatures below and at or above a set threshold. Below the threshold temperature, the solution removes one dielectric material (e.g., silicon nitride) faster than it removes another, different dielectric material (e.g., silicon oxide). At or above the threshold temperature, the selectivity of the solution is reversed.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: May 29, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Don L. Yates
  • Patent number: 8182710
    Abstract: A method of structuring multicrystalline silicon surfaces comprises the provision of a texturing solution, the application of the texturing solution to a surface of a semiconductor substrate to be structured and the heating of the texturing solution to a texturing temperature, wherein the texturing solution comprises at least a portion of phosphoric acid.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: May 22, 2012
    Assignee: Deutsche Cell GmbH
    Inventor: Detlef Sontag
  • Patent number: 8183163
    Abstract: An etching liquid used for selectively etching silicon nitride, the etching liquid includes: water; a first liquid that can be mixed with the water to produce a mixture liquid having a boiling point of 150° C. or more; and a second liquid capable of producing protons (H+). Alternatively, an etching liquid includes: water; phosphoric acid; and sulfuric acid, the phosphoric acid and the sulfuric acid having a volume ratio of 300:32 to 150:300.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: May 22, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuya Eguchi, Naoya Hayamizu, Hiroyuki Fukui
  • Patent number: 8168076
    Abstract: A mould for objects made of polymer material is produced by successively depositing a barrier thin layer and a thin layer of diamond-like carbon on at least a part of a metal support. The thin layer of diamond-like carbon is then nanopatterned with a predetermined pattern presenting a form factor of more than 1. Nanopatterning is performed by selective chemical etching in dry phase through a hard mask and etching stops at an interface between the thin layer of diamond-like carbon and the barrier thin layer. The hard mask used was formed beforehand on a free surface of the thin layer of diamond-like carbon by selective chemical etching in dry phase performed through a void lattice delineated by nanoparticles deposited beforehand on a free surface of said hard mask. The barrier thin layer and the nanopatterned thin layer of diamond-like carbon form a bilayer coating presenting a thickness comprised between about 100 nm and about 10 ?m.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: May 1, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Jerome Gavillet, Pierre Juliet
  • Publication number: 20120091100
    Abstract: The present disclosure provides a chemical etchant which is capable of removing Ge and Ge-rich SiGe alloys in a controlled manner. The chemical etchant of the present disclosure includes a mixture of a halogen-containing acid, hydrogen peroxide, and water. Water is present in the mixture in an amount of greater than 90% by volume of the entire mixture. The present disclosure also provides a method of making such a chemical etchant. The method includes mixing, in any order, a halogen-containing acid and hydrogen peroxide to provide a halogen-containing acid/hydrogen peroxide mixture, and adding water to the halogen-containing acid/hydrogen peroxide mixture. Also disclosed is a method of etching a Ge or Ge-rich SiGe alloy utilizing the chemical etchant of the present application.
    Type: Application
    Filed: October 14, 2010
    Publication date: April 19, 2012
    Applicants: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Nicolas Daval
  • Patent number: 8153019
    Abstract: Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, prevents higher material removal rates at the corners than at smoother areas of the structure or film from which material is removed. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses in a surface of a film or other structure at undesirably high rates are also disclosed.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: April 10, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, J. Neil Greeley
  • Patent number: 8141386
    Abstract: A method for fabricating a glass substrate containing SiO2 as a main ingredient thereof for an information recording medium which ensures removal of abrasive or foreign mater adhered to the glass substrate without complicating a cleaning step, involves, after a polishing step, keeping the surface of the glass substrate in contact with a liquid having a Si element elution in a range from 100 to 10 000 ppb/mm2 before a scrub-cleaning step.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: March 27, 2012
    Assignee: Konica Minolta Opto, Inc.
    Inventors: Hideki Kawai, Yukitoshi Nakatsuji, Hiroaki Sawada, Shinichi Saeki