Substrate Contains Silicon Or Silicon Compound Patents (Class 216/99)
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Patent number: 7776228Abstract: A catalyst-aided chemical processing method is a novel processing method having a high processing efficiency and suited for processing in a space wavelength range of not less than several tens of ?m. The catalyst-aided chemical processing method comprises: immersing a workpiece in a processing solution in which a halogen-containing molecule is dissolved, said workpiece normally being insoluble in said processing solution; and bringing a platinum, gold or ceramic solid catalyst close to or into contact with a processing surface of the workpiece, thereby processing the workpiece through dissolution in the processing solution of a halogenide produced by chemical reaction between a halogen radical generated at the surface of the catalyst and a surface atom of the workpiece.Type: GrantFiled: April 11, 2006Date of Patent: August 17, 2010Assignee: Ebara CorporationInventors: Kazuto Yamauchi, Yasuhisa Sano
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Publication number: 20100196780Abstract: An anode structure comprises an array of carbon nanotubes having a diffusion side and a membrane side, and catalyst particles interspersed on inner surfaces of the membrane side of the carbon nanotubes. The carbon nanotubes have an average diameter greater than the size of the hydrogen molecule but smaller than the size of the carbon monoxide molecule. Thus, hydrogen flowing toward the catalyst particles interspersed inside the carbon nanotubes are able to go through, while the flow of trace amounts of carbon monoxide contained in the hydrogen is blocked, preventing the poisoning of the catalyst particles by the carbon monoxide. A fuel cell utilizing the anode structure and a method for manufacturing the anode structure are also disclosed.Type: ApplicationFiled: January 30, 2009Publication date: August 5, 2010Inventor: Mark Kaiser
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Patent number: 7767099Abstract: The present invention is directed to the formation of sublithographic features in a semiconductor structure using self-assembling polymers. The self-assembling polymers are formed in openings in a hard mask, annealed and then etched, followed by etching of the underlying dielectric material. At least one sublithographic feature is formed according to this method. Also disclosed is an intermediate semiconductor structure in which at least one interconnect wiring feature has a dimension that is defined by a self-assembled block copolymer.Type: GrantFiled: January 26, 2007Date of Patent: August 3, 2010Assignee: International Business Machines CorporaitonInventors: Wai-Kin Li, Haining S. Yang
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Patent number: 7767555Abstract: A method for cutting a substrate is disclosed which uses a femtosecond laser capable of preventing thermal expansion and generation of shock waves from occurring around a region where a cutting process is carried out when the femtosecond laser is used to cut the substrate, thereby being capable of achieving a reduction in costs. The method includes the steps of arranging the substrate on a stage, and irradiating a femtosecond laser to a predetermined portion of the substrate arranged on the stage, thereby cutting the substrate along the predetermined substrate portion.Type: GrantFiled: June 28, 2005Date of Patent: August 3, 2010Assignee: LG. Display Co., Ltd.Inventor: Jeong Kweon Park
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Patent number: 7767101Abstract: A method of fabricating a probe tip for use in a scanning probe microscope, includes the steps of: forming a triangular prism provided with a passivation film by patterning a {111} general silicon wafer, the passivation film being deposited on two sidewalls of the triangular prism; etching the silicon wafer to make the triangular prism into a probe tip of a triangular pyramid shape; and removing the passivation film.Type: GrantFiled: May 24, 2007Date of Patent: August 3, 2010Assignee: M2N Inc.Inventors: Young Geun Park, Hee Ok Jang
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Publication number: 20100183885Abstract: A bonding method of silicon base members is provided. The bonding method of silicon base members comprises: applying an energy to a first silicon base member including Si—H bonds to selectively cut the Si—H bonds so that the first silicon base member is cleaved and divided to one silicon base member and the other silicon base member, and the one silicon base member having a cleavage surface and dangling bonds of silicon obtained by cutting the Si—H bonds; and bonding the cleavage surface of the one silicon base member and a surface of a second silicon base member on which dangling bonds of silicon are exposed to thereby bond the cleavage surface and the surface together through their dangling bonds.Type: ApplicationFiled: June 16, 2008Publication date: July 22, 2010Applicant: SEIKO EPSON CORPORATIONInventors: Mitsuru Sato, Yoshiaki Mori
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Patent number: 7759258Abstract: A surface texturization process for a silicon wafer, which is applied to a method for making a solar cell, is provided. The surface texturization process substantially comprises: 1) providing an acidic mixed solution; 2) immersing the silicon wafer in the acidic mixed solution; and 3) etching the acidic mixed solution for a predetermined time section. The mixed acidic solution includes nitric acid and ammonium fluoride and a predetermined mixture selecting from the group consisting of phosphoric acid, sulfuric acid or acetic acid.Type: GrantFiled: December 29, 2005Date of Patent: July 20, 2010Assignee: Industrial Technology Research InstituteInventor: Chen-Hsun Du
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Patent number: 7759252Abstract: The present invention is related to a method of two-step backside-etching. First, a substrate with a plurality of hard masks is provided. Next, the back and the edge of the substrate are backside-etched to remove parts of the hard masks on the back and the edge of the substrate. Then, the hard masks and the substrate are patterned in sequence to form a plurality of trenches in the substrate. Finally, before performing a wet bath step, the edge of the substrate is backside-etched to remove needle structures on the edge of the substrate.Type: GrantFiled: July 10, 2007Date of Patent: July 20, 2010Assignee: Promos Technologies Inc.Inventor: Yeng-Peng Wang
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Publication number: 20100151206Abstract: Described herein is a method for removing at least a portion of the carbon-containing species within an organosilicate (OSG) film by treating the OSG film with a chemical, such as but not limited to an oxidizer, exposing the OSG film to an energy source comprising ultraviolet light, or treating the OSG film with a chemical and exposing the OSG film to an energy source.Type: ApplicationFiled: October 8, 2009Publication date: June 17, 2010Applicant: Air Products and Chemicals, Inc.Inventors: Aiping Wu, Scott Jeffrey Weigel, Thomas Albert Braymer
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Patent number: 7731861Abstract: A liquid drop discharge head includes a chip 21 that is formed by separation of a silicon wafer 20. The silicon wafer 20 has a first direction and a second direction which are mutually intersected. The chip 21 is separated from the silicon wafer 20 by etching the wafer along a separation line 22 parallel to the first direction of the wafer and by dicing the wafer 20 along a separation line 23 parallel to the second direction of the wafer.Type: GrantFiled: June 19, 2006Date of Patent: June 8, 2010Assignee: Ricoh Company, Ltd.Inventors: Kenichiroh Hashimoto, Tadashi Mimura
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Publication number: 20100129610Abstract: Silicon in prismatic shape is produced by using a silicon wafer with (110) surface and sequentially carrying out an alignment configuration forming step for forming alignment configurations having surfaces that are along two (111) surfaces perpendicular to a substrate surface inside the silicon wafer, a primary anisotropic etching step for forming perpendicular walls having wall surfaces aligned to one of these (111) surfaces, and a secondary anisotropic etching step for forming silicon in the prismatic shape having wall surfaces aligned to the other of these (111) surfaces with respect to the perpendicular walls.Type: ApplicationFiled: May 14, 2007Publication date: May 27, 2010Applicant: NATIONAL UNIVERSITY CORPORATION KAGAWA UNIVERSITYInventors: Fumikazu Oohira, Gen Hashiguchi, Shinya Nagao
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Patent number: 7718084Abstract: A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a dielectric layer overlying another dielectric layer, contacting the substrate at a first temperature with an acid solution exhibiting a positive etch selectivity at the first temperature, and then contacting the substrate at a second temperature with an acid solution exhibiting a positive etch selectivity at the second temperature. The dielectric layers exhibit different etch rates when etched at the first and second temperatures. The first and second acid solutions may contain phosphoric acid. The first dielectric layer may be silicon nitride and the second dielectric layer may be silicon oxide. Under these conditions, the first temperature may be about 175° C. and the second temperature may be about 155° C.Type: GrantFiled: May 3, 2004Date of Patent: May 18, 2010Assignee: Micron Technology, Inc.Inventors: Li Li, Don L. Yates
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Patent number: 7713478Abstract: Disclosed is equipment for measuring a silicon concentration in a phosphoric acid solution under use as an etching solution during operation of a semiconductor substrate processing system. The equipment is provided with at least a reaction tank and a concentration-measuring tank. The reaction tank includes a reaction unit for adding hydrofluoric acid to a predetermined constant amount of the phosphoric acid solution drawn out of the semiconductor substrate processing system to form a silicon fluoride compound and then causing the silicon fluoride compound to evaporate. The concentration-measuring tank comprises a hydrolysis unit for bubbling the silicon fluoride compound, which has evaporated from the reaction tank, through deionized water to hydrolyze the silicon fluoride compound and a measurement unit for determining a change rate of silicon concentration in the deionized water subsequent to the bubbling.Type: GrantFiled: May 17, 2006Date of Patent: May 11, 2010Assignee: Apprecia Technology Inc.Inventors: Haruru Watatsu, Nobuhiko Izuta, Hideo Yata
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Publication number: 20100108642Abstract: A method and an apparatus for removing fine-grain silicon material from coarse-grain ground silicon material are disclosed. In the method, ground silicon material is selected that exhibits a predominantly brown color in an aqueous suspension, indicating that a considerable fraction of the ground silicon material has a grain size of less than 0.25 ?m, and the ground silicon material is supplied to a reaction vessel. An aqueous or water-containing solution of a base is added to the ground silicon material, causing an etching process which chemically removes a fine fraction with a grain size of less than approximately 1 ?m. Acid or water is then added to terminate etching and cause rapid sedimentation of a suspension in form of a relatively coarse-grain solid, which can be removed for further processing. The solution formed above the relatively coarse-grain solid can also be withdrawn.Type: ApplicationFiled: November 3, 2009Publication date: May 6, 2010Applicant: Adensis GmbHInventors: Jörg Acker, Anja Rietig, Birgit Meinel
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Publication number: 20100102033Abstract: A method for preparing nanotubes by providing nanorods of a piezoelectric material having an asymmetric crystal structure and by further providing hydroxide ions to the nanorods to etch inner parts of the nanorods to form the nanotubes.Type: ApplicationFiled: October 26, 2009Publication date: April 29, 2010Applicants: SAMSUNG ELECTRONICS CO., LTD., KUMOH NATIONAL INSTITUTE OF TECHNOLOGYInventors: Jaeyoung CHOI, Sangwoo KIM
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Patent number: 7699998Abstract: A method of substantially uniformly etching oxides from non-homogeneous substrates is provided. The method utilizes a substantially non-aqueous etchant including an organic solvent and a fluorine-containing compound. The fluorine containing compound may include HF, HF:NH4F, (NH4)HF2, or TMAF:HF and mixtures thereof. The etchant may be applied to chemically non-homogeneous layers such as shallow trench isolation fill oxide layers, or to layers having a non-homogeneous composition or density at different depths within the layers, such as spin-on-glass or spin-on-dielectric films.Type: GrantFiled: August 22, 2005Date of Patent: April 20, 2010Assignee: Micron Technology, Inc.Inventors: Janos Fucsko, Grady Waldo, Bob Carstensen, Satish Bedge
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Publication number: 20100084628Abstract: Disclosed herein are a branched nanowire having parasitic nanowires grown at a surface of the branched nanowire, and a method for fabricating the same. The branched nanowire may be fabricated in a fractal form and seeds of the parasitic nanowires may be formed by thermal energy irradiation and/or a wet-etching process. The branched nanowire may effectively be used in a wide variety of applications such as, for example, sensors, photodetectors, light emitting elements, light receiving elements, and the like.Type: ApplicationFiled: March 11, 2009Publication date: April 8, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Eun Kyung LEE, Byoung Ryong CHOI, Sang Jin LEE
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Patent number: 7686973Abstract: A wafer etching and impurity analysis method is presented in which a wafer is held in a vessel having gas introduction and exhaust ports, a solution including a mixture of hydrofluoric acid and nitric acid alone or together with sulfuric acid is bubbled with a carrier gas without being heated, which generates a gas containing vaporized hydrofluoric acid and nitric acid, and the inside of the vessel is purged so that the amount of gas supplied is kept constant at all times. All or a specific portion of the wafer is cooled to a specific temperature. Consequently, the gas is condensed on the surface of the wafer, which allows the required portion of the wafer to be etched. The method reduces the amount of liquid needed for residue recovery, the amount of admixed silicon during impurity analysis, and the concentration time.Type: GrantFiled: April 24, 2007Date of Patent: March 30, 2010Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Katsuya Hirano, Hiroshi Horie
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Publication number: 20100044344Abstract: A silicon nanoparticle formation method that can rapidly produce substantial quantities of silicon nanoparticles, which are readily recoverable for subsequent uses. Methods of the invention treat silicon powder in hexachloroplatinic acid.Type: ApplicationFiled: July 25, 2006Publication date: February 25, 2010Inventors: Munir H. Nayfeh, Jon Host, David Nielsen
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Patent number: 7666795Abstract: A method for manufacturing a semiconductor device includes forming a SiGe layer on a Si substrate, forming a dummy pattern to expose a surface of the Si substrate, and wet etching the SiGe layer while an etchant is contacted with, the dummy pattern.Type: GrantFiled: December 13, 2007Date of Patent: February 23, 2010Assignee: Seiko Epson CorporationInventors: Juri Kato, Hideaki Oka, Masamitsu Uehara
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Patent number: 7662299Abstract: A method for forming a template useful for nanoimprint lithography comprises forming at least one pillar which provides a topographic feature extending from a template base. At least one conformal pattern layer and one conformal spacing layer, and generally a plurality of alternating pattern layers and spacing layers, are formed over the template base and pillar. A planarized filler layer is formed over the pattern and spacing layers, then the filler, the spacing layer and the pattern layer are partially removed, for example using mechanical polishing, to expose the pillar. One or more etches are performed to remove at least a portion of the pillar, the filler, and the spacing layer to result in the pattern layer protruding from the spacing layer and providing the template pattern.Type: GrantFiled: August 30, 2005Date of Patent: February 16, 2010Assignee: Micron Technology, Inc.Inventors: Krupakar M. Subramanian, Mirzafer Abatchev
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Patent number: 7642198Abstract: A method for evaluating crystal defects of a silicon wafer comprising: etching a surface of the silicon wafer by immersing the wafer in an etching solution; and observing etch pits formed on the etched surface of the wafer, wherein the silicon wafer of which crystal defects are evaluated has low electrical resistivity of 1 ?·cm or less, and the etching solution is a mixture of hydrofluoric acid, nitric acid, acetic acid and water further including iodine or iodide, in which a volume ratio of nitric acid in the etching solution is the largest among volume ratios of hydrofluoric acid, nitric acid, acetic acid and water, and the etching solution is adjusted to have an etching rate of 100 nm/min or less for the silicon wafer. Thereby, there is provided a method for evaluating crystal defects of a silicon wafer with low electrical resistivity by using a chromium-free etching solution without toxic chromium with high capability of detecting defects.Type: GrantFiled: March 11, 2005Date of Patent: January 5, 2010Assignee: Shin-Etsu Handotai Co., Ltd.Inventor: Hideki Sato
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Patent number: 7629257Abstract: The invention concerns etching and doping substances free of hydrochloric/fluoride acid used for etching inorganic layers as well as for doping subjacent layers. The invention also concerns a method wherein said substances are used.Type: GrantFiled: September 13, 2002Date of Patent: December 8, 2009Assignee: Merck PatentgesellschaftInventors: Sylke Klein, Armin Kübelbeck, Werner Stockum, Wilfried Schmidt, Berthold Schum
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Patent number: 7628932Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.Type: GrantFiled: June 2, 2006Date of Patent: December 8, 2009Assignee: Micron Technology, Inc.Inventors: Whonchee Lee, Janos Fucsko, David H. Wells
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Publication number: 20090280368Abstract: A method for forming an increased efficiency microreactor for an energy production for portable applications includes at least one micro fuel cell. The microreactor has a reaction chamber including a catalyst for the production of gaseous hydrogen to be supplied to the micro fuel cell. The method may include providing at least one first silicon die, a face thereof defining an active surface of the reaction chamber. The method may include anisotropically etching the at least one first silicon die for realizing a plurality of notches and countershaped ridges suitable for increasing the area of the active surface so as to define an increased active surface. The method may also include depositing on at least one portion of the increased active surface a layer of the catalyst.Type: ApplicationFiled: March 23, 2009Publication date: November 12, 2009Applicant: STMicroelectronics S.r.l.Inventors: Giuseppe Spoto, Cristian Dall'Oglio, Roberta Zito
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Publication number: 20090272720Abstract: A method for forming polysilicon material for photovoltaic cells. A first silicon material characterized by a first purity level is provided. The first silicon material is subjected to a thermal process to transform the first silicon material to a molten state confined in a first spatial volume. The molten first silicon material is subjected to a directional cooling process provided in a second spatial volume for a predetermined period, removing thermal energy from a first region. A polycrystalline silicon material characterized by a second purity level and an average grain size greater than about 0.1 mm is formed from the molten first silicon material in a vicinity of the first region. One or more silicon wafers is formed from the polycrystalline silicon material. A polysilicon film material characterized by a grain size greater than about 0.1 mm is deposited overlying each of the silicon wafers.Type: ApplicationFiled: April 30, 2009Publication date: November 5, 2009Applicant: Jian Zhong YuanInventor: JIAN ZHONG YUAN
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Publication number: 20090236317Abstract: A method (300) for etching a silicon surface (116). The method (300) includes positioning (310) a substrate (112) with a silicon surface (116) into a vessel (122). The vessel (122) is filled (330, 340) with a volume of an etching solution (124) so as to cover the silicon surface (116). The etching solution (124) includes a catalytic solution (140) and an oxidant-etchant solution (146), e.g., an aqueous solution of hydrofluoric acid and hydrogen peroxide. The catalytic solution (140) may be a solution that provides metal-containing molecules or ionic species of catalytic metals. The silicon surface (116) is etched (350) by agitating the etching solution (124) in the vessel (122) such as with ultrasonic agitation, and the etching may include heating (360) the etching solution (124) and directing light (365) onto the silicon surface (116).Type: ApplicationFiled: March 21, 2008Publication date: September 24, 2009Applicant: MIDWEST RESEARCH INSTITUTEInventors: VERNON YOST, HOWARD BRANZ
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Patent number: 7591959Abstract: An etchant for removing materials with a plurality of selectivities exhibits a first etch selectivity at a first temperature and a second etch selectivity at a second temperature. The etchant may include phosphoric acid, fluoboric acid, or sulfuric acid. The materials that the etchant is configured to remove may include dielectric materials, such as silicon nitride and silicon oxide. The first temperature may be about 175° C. and the second temperature may be about 155° C.Type: GrantFiled: January 4, 2006Date of Patent: September 22, 2009Assignee: Micron Technology, Inc.Inventors: Li Li, Don L. Yates
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Patent number: 7591958Abstract: The manufacturing of electronic components on individual substrates made of an insulating material includes molding, in a silicon wafer, an insulating material with a thickness corresponding to the final thickness desired for the substrates, manufacturing the electronic components, and removing the silicon from the rear surface of the wafer after manufacturing of the components.Type: GrantFiled: August 26, 2005Date of Patent: September 22, 2009Assignee: STMicroelectronics SAInventors: Pascal Gardes, Fabrice Guitton
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Patent number: 7582219Abstract: A method is provided of fabricating a reflective mirror having a reflective surface on which light is incident. This method includes: coating at least one of opposite faces of a plate-shaped etchable material made of a single crystal material, with a film-like etching mask; forming a mask pattern on at least one of opposite faces of the etching mask, the mask pattern having a planar shape to which a circle is more similar than a quadrangle; and wet-etching the etchable material. This method allows the reflective mirror to be fabricated so as to have a silhouette of a planar shape to which a circle is more similar than a quadrangle, when viewed in a direction normal to the reflective surface.Type: GrantFiled: November 30, 2006Date of Patent: September 1, 2009Assignee: Brother Kogyo Kabushiki KaishaInventors: Nobuaki Asai, Emi Morioka
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Patent number: 7582221Abstract: The present invention provides a wafer manufacturing method and a wafer polishing apparatus which enable control of sags in a periphery of a wafer and improvement of nanotopology values thereof that is strongly required recently, and a wafer. In a polishing process for making a mirror surface of the wafer, a back surface of the wafer is polished to produce a reference plane thereof.Type: GrantFiled: October 22, 2001Date of Patent: September 1, 2009Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Shigeyoshi Netsu, Hisashi Masumura
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Patent number: 7581645Abstract: A method for manufacturing carbon nanotubes with a desired length includes the steps of: providing an array of carbon nanotubes; placing a mask having at least an opening defined therein on the array of carbon nanotubes, with at least one portion of the array of carbon nanotubes being at least partially exposed through a corresponding opening of the mask; forming a protective film on at least one exposed portion of the array of carbon nanotubes; removing the mask from the array of the carbon nanotubes, with the carbon nanotubes being compartmentalized into at least a first portion covered by the protective film and at least one uncovered second portion; breaking/separating the first portion from the second portion of the array of the carbon nanotubes using a chemical method, thereby obtaining at least a carbon nanotube segment with a protective film covered thereon; and removing the protective film from the carbon nanotube segment.Type: GrantFiled: August 1, 2006Date of Patent: September 1, 2009Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Chi-Chuang Ho, Bor-Yuan Hsiao, Ching-Chou Chang
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Publication number: 20090215156Abstract: The present invention relates to a method of fabricating a nanogap and a nanogap sensor, and to a nanogap and a nanogap sensor fabricated using the method. The present invention relates to a method of fabricating a nanogap and a nanogap sensor, which can be realized by an anisotropic etching using a semiconductor manufacturing process. According to the method of present invention, the nanogap and nanogap sensor can be simply and cheaply produced in large quantities.Type: ApplicationFiled: September 5, 2006Publication date: August 27, 2009Inventors: Bong hyun Chung, Sang kyu Kim, Hye Jung Park
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Patent number: 7578889Abstract: Systematic and effective methodology to clean capacitively coupled plasma reactor electrodes and reduce surface roughness so that the cleaned electrodes meet surface contamination specifications and manufacturing yields are enhanced. Pre-cleaning of tools used in the cleaning process helps prevent contamination of the electrode being cleaned.Type: GrantFiled: March 30, 2007Date of Patent: August 25, 2009Assignee: Lam Research CorporationInventors: Hong Shih, Yaobo Yin, Shun Jackson Wu, Armen Avoyan, John E. Daugherty, Linda Jiang
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Patent number: 7578943Abstract: A loss in the rigidity of a substrate for a liquid discharge head having nozzles at a high density can be suppressed. A liquid discharge head includes plural pressure generating chambers respectively provided with pressure generating elements, plural nozzle apertures respectively communicating with the plural pressure generating chambers and adapted to discharge a liquid, and a reservoir with which the plural pressure generating chambers commonly communicate respectively through communicating parts. The pressure generating chambers and the reservoir respectively have recessed portions formed respectively on one and the other of two principal planes of the same substrate, and the reservoir contains a portion shallower than a portion within the reservoir that communicates with the pressure generating chambers.Type: GrantFiled: May 19, 2006Date of Patent: August 25, 2009Assignee: Canon Kabushiki KaishaInventors: Rei Kurashima, Takashi Ushijima, Koichiro Nakanishi
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Patent number: 7572661Abstract: Described is a method for manufacturing a micromechanical sensor element and a micromechanical sensor element manufactured in particular using such a method which has a hollow space or a cavity and a membrane for detecting a physical variable. Different method steps are performed for manufacturing the sensor element, among other things, a structured etch mask having a plurality of holes or apertures being applied on a semiconductor substrate. Moreover, an etch process is used to create depressions in the semiconductor substrate beneath the holes in the structured etch mask. Anodization of the semiconductor material is subsequently carried out, the anodization taking place preferably starting from the created depressions in the semiconductor substrate. Due to this process, porous areas are created beneath the depressions, a lattice-like structure made of untreated, i.e., non-anodized, substrate material remaining between the porous areas and the depressions.Type: GrantFiled: September 8, 2005Date of Patent: August 11, 2009Assignee: Robert Bosch GmbHInventors: Hubert Benzel, Stefan Finkbeiner, Matthias Illing, Frank Schaefer, Simon Armbruster, Gerhard Lammel, Christoph Schelling, Joerg Brasas
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Patent number: 7569491Abstract: A method and system for fabricating nano-scale structures, such as channels (i.e., nano-channels) or vias (i.e., nano-vias. An open nano-structure, is formed in a substrate. Thereafter, an optional conformal material film may be deposited within and over the nano-structure using a first deposition process condition, and then the open nano-structure is closed off to form a closed nano-structure using a second deposition process condition, including one or more process steps.Type: GrantFiled: August 30, 2006Date of Patent: August 4, 2009Assignee: Tokyo Electron LimitedInventor: Jacques Faguet
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Patent number: 7569412Abstract: A method for producing a micromechanical diaphragm sensor includes providing a semiconductor substrate having a first region, a diaphragm, and a cavity that is located at least partially below the diaphragm. Above at least one part of the first region, a second region is generated in or on the surface of the semiconductor substrate, with at least one part of the second region being provided as crosspieces. The diaphragm is formed by a deposited sealing layer, and includes at least a part of the crosspieces.Type: GrantFiled: December 13, 2004Date of Patent: August 4, 2009Assignee: Robert Bosch GmbHInventors: Hubert Benzel, Frank Schaefer, Simon Armbruster, Gerhard Lammel, Christoph Schelling, Joerg Brasas
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Patent number: 7560036Abstract: The invention relates to a method of fabricating a microneedle array in a substrate, a drug delivery device comprising one or more microneedles extending upwards from the front surface of the substrate, the microneedles having a generally conical-shaped body defined by a plurality of surfaces sloping upwards from a relatively broad base to a tip, and one or more substances coating the microneedles, the one or more substances being operable to be administered to a patient, wherein the tips of the one or more microneedles are sufficiently sharp to penetrate an outer layer of the skin of the patient, and a method of administering one or more substances to a patient using the device.Type: GrantFiled: May 20, 2005Date of Patent: July 14, 2009Assignee: Apogee Technology, Inc.Inventors: Nevenka Golubovic-Liakopoulos, Glenn Fricano, Michael Danielson
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Publication number: 20090166324Abstract: Embodiments of silicon semiconductor wafers and die having surface marks are described herein. A laser, or other marking tool, may be used to mark, substantially all of a surface of an IC wafer with surface marks, such as microdimples, that camouflage or reduce or eliminate the visibility of any surface imperfections such as smudges, scratches, or other marks that may reduce the marketability of packaged IC's where such surface imperfections are visible to the end customer. By marking the wafer prior to dicing, the entire surface of each individual die may have its entire bottom surface marked. Other embodiments are also described.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Inventor: Kevin J. Lee
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Publication number: 20090148652Abstract: Diamond SPM and AFM probes which are durable, particularly for scanning hard surfaces such as diamond surfaces. Interlayers and seeding can be used to improve diamond deposition, and the diamond can be ultrananocrystalline diamond (UNCD). Tip sharpening improves resolution.Type: ApplicationFiled: July 11, 2008Publication date: June 11, 2009Inventors: John A. Carlisle, Nicolaie Moldovan
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Patent number: 7540968Abstract: A micro movable device includes a base substrate, a fixed portion bonded to the base substrate, a movable portion having a fixed end connected to the fixed portion and extending along the base substrate, and a piezoelectric drive provided on the movable portion and the fixed portion on a side opposite to the base substrate. The piezoelectric drive has a laminate structure provided by a first electrode film contacting the movable portion and the fixed portion, a second electrode film and a piezoelectric film between the first and the second electrode films. At least one of the movable portion and the fixed portion is provided with a groove extending along the piezoelectric drive.Type: GrantFiled: March 16, 2006Date of Patent: June 2, 2009Assignee: Fujitsu LimitedInventors: Anh Tuan Nguyen, Tadashi Nakatani, Takeaki Shimanouchi, Masahiko Imai, Satoshi Ueda
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Publication number: 20090127228Abstract: A method of structuring multicrystalline silicon surfaces comprises the provision of a texturing solution, the application of the texturing solution to a surface of a semiconductor substrate to be structured and the heating of the texturing solution to a texturing temperature, wherein the texturing solution comprises at least a portion of phosphoric acid.Type: ApplicationFiled: November 17, 2008Publication date: May 21, 2009Applicant: Deutsche Cell GmbHInventor: Detlef SONTAG
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Patent number: 7524767Abstract: A technique for manufacturing a micro-electro-mechanical (MEM) structure includes a number of steps. Initially, a substrate is provided. Next, a plurality of trenches are etched into the substrate with a first etch. Then, a charging layer is formed at a bottom of each of the trenches to form undercut trenches. Finally, a second etch is provided into the undercut trenches. The charging layer causes the second etch to laterally etch foots in the substrate between the undercut trenches. The footers undercut the substrate to release a portion of the substrate for providing a movable structure between the undercut trenches and above the footers.Type: GrantFiled: September 29, 2005Date of Patent: April 28, 2009Assignee: Delphi Technologies, Inc.Inventor: Dan W. Chilcott
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Patent number: 7524430Abstract: Methods of forming a fluid channel in a semiconductor substrate may include applying a material layer to at least one surface of the semiconductor substrate. The method may further include manipulating the material layer to form a surface topography corresponding to a channel, the surface topography being configured to control directionality of ion bombardment of said substrate along electromagnetic field lines in a plasma sheath coupled to said surface topography.Type: GrantFiled: December 30, 2004Date of Patent: April 28, 2009Assignee: Lexmark International, Inc.Inventors: John W. Krawczyk, Andrew L. McNees
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Publication number: 20090084440Abstract: A semiconductor photovoltaic device comprises a semiconductor substrate having a first surface and a second surface, the first surface and the second surface being opposed to each other, a plurality of trenches extending into the semiconductor substrate from the first surface, the first surface being a substantially planar surface, a dopant region in the semiconductor substrate near the first surface and the plurality of trenches, a first conductive layer over the semiconductor substrate, and a second conductive layer on the second surface of the semiconductor substrate.Type: ApplicationFiled: October 1, 2007Publication date: April 2, 2009Applicant: INTEGRATED DIGITAL TECHNOLOGIES, INC.Inventors: Brite Jui-Hsien WANG, Naejye HWANG, Zingway PEI
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Publication number: 20090074650Abstract: An exemplary method of production of solar grade silicon is disclosed. The method comprises melting the silicon and directionally solidifying the melt. The method additionally comprises forming a crystallization front during the directional solidification, the front having the shape of at least a section of a spherical surface. Also disclosed are a silicon wafer and a solar cell in accordance with an exemplary embodiment of the present invention.Type: ApplicationFiled: August 9, 2006Publication date: March 19, 2009Applicant: Scheuten Solar Holding BVInventors: Peter Fath, Albrecht Mozer
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Publication number: 20090065482Abstract: Provided is a method of manufacturing a substrate for a liquid discharge head, the substrate including a silicon substrate with a liquid supply opening formed therein, the method including: forming one processed portion by laser processing on the substrate from one surface of the substrate; expanding the one processed portion to form a recess portion by performing laser processing at a position which overlaps a part of the one processed portion and does not overlap another part of the one processed portion; and etching from the one surface the substrate with the recess portion formed therein to form the liquid supply opening.Type: ApplicationFiled: September 3, 2008Publication date: March 12, 2009Applicant: CANON KABUSHIKI KAISHAInventors: Hiroto Komiyama, Hirokazu Komuro, Satoshi Ibe, Takuya Hatsui, Keisuke Kishimoto, Kazuhiro Asai, Shimpei Otaka
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Publication number: 20090065481Abstract: A method of manufacturing a substrate for a liquid discharge head having a silicon substrate in which a liquid supply port is provided includes providing the silicon substrate, an etching mask layer having an opening being formed on a one surface of the silicon substrate, forming a region comprising an amorphous silicon in the interior of the silicon substrate by irradiating the silicon substrate with laser light, forming a recess, which has an opening at a part of a portion exposed from said opening on said one surface, from said one surface of the silicon substrate toward the region, and forming the supply port by performing etching on the silicon substrate in which the recess and the region have been formed from said one surface through the opening of the etching mask layer.Type: ApplicationFiled: September 3, 2008Publication date: March 12, 2009Applicant: CANON KABUSHIKI KAISHAInventors: Keisuke Kishimoto, Hirokazu Komuro, Satoshi Ibe, Takuya Hatsui, Kazuhiro Asai, Shimpei Otaka, Hiroto Komiyama
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Patent number: 7501072Abstract: This invention relates to etching solutions which comprise hydrofluoric acid and organic solvents for use in the process for the production of integrated circuits. The etching solutions according to the invention are particularly suitable for the selective etching of doped silicate layers.Type: GrantFiled: April 2, 2007Date of Patent: March 10, 2009Assignee: BASF AktiengesellschaftInventors: Claudia Wiegand, Rudolf Rhein, Eberhard Tempel