Abstract: A protection device includes a triac and triggering units. Each triggering unit is formed by a MOS transistor configured to operate at least temporarily in a hybrid operating mode and a field-effect diode. The field-effect diode has a controlled gate that is connected to the gate of the MOS transistor.

Abstract: A semiconductor device includes a silicon pillar formed substantially perpendicular to a principal surface of a silicon substrate, a first impurity diffusion layer and a second impurity diffusion layer arranged below and above the silicon pillar, respectively, a gate electrode arranged to penetrate through the silicon pillar in a horizontal direction, a gate dielectric film arranged between the gate electrode and the silicon pillar, a back-gate electrode arranged adjacent to the silicon pillar, and a back-gate dielectric film arranged between the back-gate electrode and the silicon pillar.

Abstract: A rectifier building block has four electrodes: source, drain, gate and probe. The main current flows between the source and drain electrodes. The gate voltage controls the conductivity of a narrow channel under a MOS gate and can switch the RBB between OFF and ON states. Used in pairs, the RBB can be configured as a three terminal half-bridge rectifier which exhibits better than ideal diode performance, similar to synchronous rectifiers but without the need for control circuits. N-type and P-type pairs can be configured as a full bridge rectifier. Other combinations are possible to create a variety of devices.

Abstract: A vertical bidirectional switch of the type having its control referenced to the rear surface, including on its rear surface a first main electrode and on its front surface a second main electrode and a gate electrode, this switch being controllable by a positive voltage between its gate and its first electrode, wherein the gate electrode is arranged on the front surface of a via crossing the chip in which the switch is formed.

Abstract: A power semiconductor structure with a field effect rectifier having a drain region, a body region, a source region, a gate channel, and a current channel is provided. The body region is substantially located above the drain region. The source region is located in the body region. The gate channel is located in the body region and adjacent to a gate structure. The current channel is located in the body region and is extended from the source region downward to the drain region. The current channel is adjacent to a conductive structure coupled to the source region.

Abstract: Provided is a semiconductor bistable switching device that includes a thyristor portion including an anode layer, a drift layer, a gate layer and a cathode layer, the gate layer operable to receive a gate trigger current that, when the anode layer is positively biased relative to the cathode layer, causes the thyristor portion to latch into a conducting mode between the anode and the cathode. The device also includes a transistor portion formed on the thyristor portion, the transistor portion including a source, a drain and a transistor gate, the drain coupled to the cathode of the thyristor portion.

Abstract: A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell region is provided. The drift zone contains at least one region through which charge carriers flow in an operating mode of the semiconductor component in one polarity and charge carriers do not flow in an operating mode of the semiconductor component in an opposite polarity.

Abstract: A voltage-controlled vertical bi-directional monolithic switch, referenced with respect to the rear surface of the switch, formed from a lightly-doped N-type semiconductor substrate, in which the control structure includes, on the front surface side, a first P-type well in which is formed an N-type region, and a second P-type well in which is formed a MOS transistor, the first P-type well and the gate of the MOS transistor being connected to a control terminal, said N-type region being connected to a main terminal of the MOS transistor, and the second main terminal of the MOS transistor being connected to the rear surface voltage of the switch.

Abstract: An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.

Abstract: An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference.

Abstract: A three terminal bi-directional laterally diffused metal oxide semiconductor (LDMOS) transistor which includes two uni-directional LDMOS transistors in series sharing a common drain node, and configured such that source nodes of the uni-directional LDMOS transistors serve as source and drain terminals of the bi-directional LDMOS transistor. The source is shorted to the backgate of each LDMOS transistor. The gate node of each LDMOS transistor is clamped to its respective source node to prevent source-gate breakdown, and the gate terminal of the bi-directional LDMOS transistor is connected to the gate nodes of the constituent uni-directional LDMOS transistors through blocking diodes. The common drain is a deep n-well which isolates the two p-type backgate regions. The gate node clamp can be a pair of back-to-back zener diodes, or a pair of self biased MOS transistors connected source-to-source in series.

Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively.

Abstract: An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference.

Abstract: According to one embodiment, in a reverse conducting-insulated gate bipolar transistor, the buffer layer is provided on the backside of the second base layer, has a higher impurity concentration in comparison with the second base layer. The first collector layer is in contact with a portion of the backside of the buffer layer, has a higher impurity concentration in comparison with the second base layer. The second collector layer is in contact with a portion of the backside of the buffer layer, is provided so as to surround the first collector layer, has a higher impurity concentration in comparison with the first base layer. The third collector layer is in contact with a portion of the backside of the buffer layer, is provided so as to surround the second collector layer, has a higher impurity concentration in comparison with the second collector layer.

Abstract: A voltage-controlled vertical bi-directional monolithic switch, referenced with respect to the rear surface of the switch, formed from a lightly-doped N-type semiconductor substrate, in which the control structure includes, on the front surface side, a first P-type well in which is formed an N-type region, and a second P-type well in which is formed a MOS transistor, the first P-type well and the gate of the MOS transistor being connected to a control terminal, said N-type region being connected to a main terminal of the MOS transistor, and the second main terminal of the MOS transistor being connected to the rear surface voltage of the switch.

Abstract: An electrostatic discharge protection device including a substrate, a first doped region, a first gate electrode, a second doped region, a second gate electrode, and a third doped region is disclosed. The substrate has a first conductive type. The first doped region has a second conductive type and is formed in the substrate. The first gate electrode is formed on the substrate. The second doped region has the second conductive type and is formed in the substrate. A transistor is constituted by the first doped region, the first gate electrode, and the second doped region. The second gate electrode is formed on the substrate. The first and the second gate electrodes are separated. The third doped region has the first conductive type and is formed in the substrate. A discharge element is constituted by the first doped region, the second gate electrode, and the third doped region.

Abstract: An insulated gate bipolar transistor includes bump pad connectors to provide thermal contact with a heat spreader for dissipating heat away form the insulated gate bipolar transistor.

Abstract: A system and method for providing symmetric, efficient bi-directional power flow and power conditioning for high-voltage applications. Embodiments include a first vertical-channel junction gate field-effect transistor (VJFET), a second VJFET, a gate drive coupled to the first VJFET gate and the second VJFET gate. Both VJFETs include a gate, drain (D1 and D2), and a source, and have gate-to-drain and gate-to-source built-in potentials. The first VJFET and the second VJFET are connected back-to-back in series so that the sources of each are shorted together at a common point S. The gate drive applies an equal voltage bias (VG) to both the gates. The gate drive is configured to selectively bias VG so that current flows through the VJFETs in the D1 to D2 direction, flows through the VJFETs in the D2 to D1 direction or voltages applied to D1 of the first VJFET or D2 of the second VJFET are blocked.

Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides one semiconductor die with a first and a second FET. One of source/drain of the first FET and one of source/drain of the second FET are electrically coupled to at least one contact area at a first side of one semiconductor die, respectively. The other one of source/drain of the first FET, a gate of the first FET, the other one of source/drain of the second FET and the gate of the second FET are electrically coupled to contact areas at a second side of the one semiconductor die opposite to the first side, respectively. The contact areas of the other one of source/drain of the first FET, of the gate of the first FET, of the other one of source/drain of the second FET and of the gate of the second FET are electrically separated from each other, respectively.

Abstract: The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas.

Abstract: In an LDMOS-SCR ESD protection structure gate voltage of an ESD protection LDSCR is defined by connecting the gate to the source of a reference LDSCR. The reference LDSCR is implemented as a self-triggering device in which the snapback drain-source voltage (avalanche breakdown voltage) is controlled to be lower than that for the major LDSCR by adjusting the RESURF layer-composite overlap for the reference LDSCR to be different to that of the major LDSCR.

Abstract: Provided is a semiconductor bistable switching device that includes a thyristor portion including an anode layer, a drift layer, a gate layer and a cathode layer, the gate layer operable to receive a gate trigger current that, when the anode layer is positively biased relative to the cathode layer, causes the thyristor portion to latch into a conducting mode between the anode and the cathode. The device also includes a transistor portion formed on the thyristor portion, the transistor portion including a source, a drain and a transistor gate, the drain coupled to the cathode of the thyristor portion.

Abstract: An integrated switching device has a switching IGFET connected between a pair of main terminals, a protector IGFET connected between the drain and gate electrodes of the switching IGFET, and a gate resistor connected between a main control terminal and the gate electrode of the switching IGFET. The protector IGFET has its gate electrode connected to the source electrode of the switching IGFET. The protector IGFET turns on in response to an application of a verse voltage to the switching IGFET thereby protecting the same from a reverse current flow.

Abstract: An electronic device includes a silicon carbide layer having a first conductivity type and having a first surface and a second surface opposite the first surface, and first and second silicon carbide Zener diodes on the silicon carbide layer. Each of the first and second silicon carbide Zener diodes may include a first heavily doped silicon carbide region having a second conductivity type opposite the first conductivity type on the silicon carbide layer, and an ohmic contact on the first heavily doped silicon carbide region.

Abstract: A semiconductor device and a method of fabrication thereof includes a bidirectional device having a high breakdown voltage and a decreased ON voltage. An n-type extended drain region is formed in the bottom surface of each trench. A p-type offset region is formed in each split semiconductor region. First and second n-source regions are formed in the surface of the p-type offset region. This reduces the in-plane distance between the first and second n-source regions to thereby increase the density of cells. The breakdown voltage is maintained along the trenches. This increases the resistance to high voltages. Channels are formed in the sidewalls of the trenches by making the voltage across each gate electrode higher than the voltage across each of the first and second n-source electrodes. Thus, a bidirectional LMOSFET through which current flows in both directions is achieved. The LMOSFET has a high breakdown voltage and a decreased ON voltage.

Abstract: An ESD protection device includes a p-well with first protrudent portions, an N-well with second protrudent portions, a P-well/N-well boundary, a PMOS transistor disposed in the N-well, an NMOS transistor disposed in the P-well, first P+ diffusion regions in the first protrudent portions, first N+ diffusion regions in the second protrudent portions, second P+ diffusion regions disposed between the PMOS transistor and the second protrudent portions, second N+ diffusion regions disposed between the NMOS transistor and the first protrudent portions, third P+ diffusion regions disposed between the NMOS transistor, the boundary, and two adjacent second P+ diffusion regions, and third N+ diffusion regions disposed between the PMOS transistor, the boundary, and two adjacent second N+ diffusion regions, wherein the first and second protrudent portions are interlacedly arranged at the boundary.

Abstract: A three terminal bi-directional laterally diffused metal oxide semiconductor (LDMOS) transistor which includes two uni-directional LDMOS transistors in series sharing a common drain node, and configured such that source nodes of the uni-directional LDMOS transistors serve as source and drain terminals of the bi-directional LDMOS transistor. The source is shorted to the backgate of each LDMOS transistor. The gate node of each LDMOS transistor is clamped to its respective source node to prevent source-gate breakdown, and the gate terminal of the bi-directional LDMOS transistor is connected to the gate nodes of the constituent uni-directional LDMOS transistors through blocking diodes. The common drain is a deep n-well which isolates the two p-type backgate regions. The gate node clamp can be a pair of back-to-back zener diodes, or a pair of self biased MOS transistors connected source-to-source in series.

Abstract: The integrated circuit may include at least one electronic protection circuit for protecting against at least one electrostatic discharge and being able to discharge the overvoltage current generated by the electrostatic discharge. The electronic protection circuit includes a controlled short-circuiting switch embodied in CMOS technology including a CMOS technology TRIAC or a CMOS technology thyristor arranged in anti-parallel with a CMOS technology diode, and a triggering circuit for controlling the short-circuiting switch.

Abstract: A bidirectional switch includes a first switch and a second switch. The switch includes a well region of a first-conductivity-type formed on a semiconductor substrate, and serving as drains of the first switch and the second switch, a gate electrode of the first switch provided in a first trench formed in the well region through a first gate insulating film, a gate electrode of the second switch formed in a second trench formed in the well region so as to be spaced apart from the first trench with a second gate insulating film, a source region of the first switch formed on a side wall of the first trench, and on a surface of the well region via a first channel region of a second-conductivity-type, and a source region of the second switch formed on a side wall of the second trench, and on a surface of the well region via a second channel region of the second-conductivity-type. The well region is formed in a region between the first trench and the second trench.

Abstract: In a semiconductor device, a metal oxide semiconductor field effect transistor (MOSFET) is formed in a semiconductor substrate, and an isolation layer is formed on the semiconductor substrate so as to extend along a side of the semiconductor substrate. A first conductive layer is formed on the isolation layer along the side of the semiconductor substrate so as to be electrically connected to a gate of the MOSFET. A second conductive layer is formed on the isolation layer along the side of the semiconductor substrate so as to be electrically connected to a drain of the MOSFET. A protection circuit is made of at least two diodes which are defined between the first conductive layer and the second conductive layer.

Abstract: A modified MOSFET structure comprises an integrated field effect rectifier connected between the source and drain of the MOSFET to shunt current during switching of the MOSFET. The integrated FER provides faster switching of the MOSFET due to the absence of injected carriers during switching while also decreasing the level of EMI relative to discrete solutions. The integrated structure of the MOSFET and FER can be fabricated using N-, multi-epitaxial and supertrench technologies, including 0.25 ?m technology. Self-aligned processing can be used.

Abstract: A bi-directional power switch is formed as a monolithic semiconductor device. The power switch has two MOSFETs formed with separate source contacts to the external package and a common drain. The MOSFETs have first and second channel regions formed over a well region above a substrate. A first source is formed in the first channel. A first metal makes electrical contact to the first source. A first gate region is formed over the first channel. A second source region is formed in the second channel. A second metal makes electrical contact to the second source. A second gate region is formed over the second channel. A common drain region is disposed between the first and second gate regions. A local oxidation on silicon region and field implant are formed over the common drain region. The metal contacts are formed in the same plane as a single metal layer.

Abstract: A silicon controlled rectifier structure with the symmetrical layout is provided. The N-type doped regions and the P-type doped regions are disposed with the N-well and symmetrically arranged relative to the isolation structure in-between, while the P-type buried layer is located under the N-type doped regions and the P-type doped regions and fully isolates the N-type doped regions from the N-well.

Abstract: A main semiconductor region grown on a substrate has formed on its surface a pair of main electrodes spaced from each other, a gate electrode between the main electrodes, and a pair of diode-forming electrodes spaced farther away from the gate electrode than are the main electrodes. Making ohmic contact with the main semiconductor region, the pair of main electrodes serve both as drain or source of a HEMT switch and as cathodes of a pair of Schottky diodes integrated with the HEMT switch. Both gate electrode and diode-forming electrodes are in Schottky contact with the main semiconductor region.

Abstract: A voltage-controlled vertical bidirectional monolithic switch, referenced with respect to the rear surface of the switch, formed from a lightly-doped N-type semiconductor substrate, in which the control structure includes, on the front surface side, a first P-type well in which is formed an N-type region, and a second P-type well in which is formed a MOS transistor, the first P-type well and the gate of the MOS transistor being connected to a control terminal, said N-type region being connected to a main terminal of the MOS transistor, and the second main terminal of the MOS transistor being connected to the rear surface voltage of the switch.

Abstract: An integrated circuit structure includes a semiconductor substrate and a horizontal semiconductor fin on top of the semiconductor substrate. An access transistor gate and a thyristor gate are on top of the semiconductor substrate and in contact with the horizontal semiconductor fin. An access transistor is at least a portion of the horizontal semiconductor fin and the access transistor gate. A thyristor is at least a portion of the horizontal semiconductor fin and the thyristor gate, the access transistor is in contact with the thyristor.

Abstract: Electronic switch device having a smaller number of component parts. Resistor R1 is connected between gate and source of a PchTr P1 and resistor R2 is connected between gate of the PchTr P1 and one end of pushbutton switch SW. Resistor R3 is connected between drain of the PchTr P1 and gate of NchTr N1, and resistor R4 is connected between gate and source of the NchTr N1. The NchTr N1 has source connected to one end of DC power supply 11 and to one end of load 12, while having drain connected to the gate of the PchTr P1. The PchTr P1 has source connected to the other end of the DC power supply 11, while having drain connected to the other end of the load 12. Capacitor C has one end connected to one end of pushbutton switch SW, while having the other end connected to one end of the DC power supply. The pushbutton switch SW has the other end connected to the gate of the NchTr N1. The PchTr P1 is alternately repeatedly rendered conductive and non-conductive for each opening/closing operation.

Abstract: A semiconductor device and method of manufacturing the same includes an n?-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n?-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.

Abstract: An SCR device having a first P type region disposed in a semiconductor body and electrically connected to anode terminal of the device. At least one N type region is also disposed in the body adjacent the first P type region so as to form a PN junction having a width Wn near a surface of the semiconductor body. A further P type region is also disposed in the body to form a further PN junction with the N type region, with the junction having a width Wp near the body surface, with Wp being at least 1.5 times width Wn. A further N type region is provided which is electrically connected to a cathode terminal of the device and forming a third PN junction with the further N type region.

Abstract: A thyristor-based semiconductor device exhibits a relatively increased base-emitter capacitance. According to an example embodiment of the present invention, a base region and an adjacent emitter region of a thyristor are doped such that the emitter region has a lightly-doped portion having a light dopant concentration, relative to the base region. In one embodiment, the thyristor is implemented in a memory circuit, wherein the emitter region is coupled to a reference voltage line and a control port is arranged for capacitively coupling to the thyristor for controlling current flow therein. In another implementation, the thyristor is formed on a buried insulator layer of a silicon-on-insulator (SOI) structure. With these approaches, current flow in the thyristor, e.g., for data storage therein, can be tightly controlled.

Abstract: A T-RAM array having a plurality of T-RAM cells is presented where each T-RAM cell has dual devices. Each T-RAM cell is planar and has a buried vertical thyristor and a horizontally stacked pseudo-TFT transfer gate. The buried vertical thyristor is located beneath the horizontally stacked pseudo-TFT transfer gate. A method is also presented for fabricating the T-RAM array having the buried vertical thyristors, the horizontally stacked pseudo-TFT transfer gates and the planar cell structure.

Abstract: An N?-type silicon substrate (1) has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N?-type silicon substrate (1), a P-type impurity diffusion layer (3) of high concentration is entirely formed by diffusing a P-type impurity. In the upper surface of the N?-type silicon substrate (1), a P-type isolation region (2) is partially formed by diffusing a P-type impurity. The P-type isolation region (2) has a bottom surface reaching an upper surface of the P-type impurity diffusion layer (3). As viewed from the upper surface side of the N?-type silicon substrate (1), the P-type isolation region (2) is formed, surrounding an N? region (1a) which is part of the N?-type silicon substrate (1). The N? region (1a) surrounded by the P-type isolation region (2) is defined as an element formation region of the N?-type silicon substrate (1).

Abstract: A thyristor-based semiconductor device includes a thyristor body that has at least one region in the substrate and a thyristor control port in a trenched region of the device substrate. According to an example embodiment of the present invention, the trench is at least partially filled with a dielectric material and a control port adapted to capacitively couple to the at least one thyristor body region in the substrate. In a more specific implementation, the dielectric material includes deposited dielectric material that is adapted to exhibit resistance to voltage-induced stress that thermally-grown dielectric materials generally exhibit. In another implementation, the dielectric material includes thermally-grown dielectric material, and when used in connection with highly-doped material in the trench, grows faster on the highly-doped material than on a sidewall of the trench that faces the at least on thyristor body region in the substrate.

Abstract: A semiconductor device is formed having a thyristor and trench arranged to electrically insulate an emitter region of the thyristor from another circuit structure. In one example embodiment of the present invention, a trench having a bottom portion with two different trench depths is etched in the substrate. A thyristor is formed having a control port in a trench and having an emitter region adjacent to the trench and below an upper surface of the substrate. A deeper portion of the trench electrically insulates the emitter region from the other circuit structure. The control port is capacitively coupled to the thyristor and to the other circuit structure (e.g. in response to at least one edge of a voltage pulse applied thereto). In one implementation, the trench further includes an emitter-access connector extending from the emitter region to an upper surface of the substrate.

Abstract: An MIS gate type semiconductor device having a low resistive loss in the ON state and a wide safe operation region is disclosed. In this semiconductor device, the p-base layer of the thyristor and the emitter electrode are connected together using a suitable nonlinear device. As a result, lower loss and higher capacity of the semiconductor device can be realized in order not only to make it easy to turn ON the thyristor but also to make the safe operation region wide.

Abstract: Disclosed is a semiconductor device including a transistor structure including an epitaxial silicon layer formed on a main surface of an n-type semiconductor substrate, source-drain diffusion layers formed on at least the epitaxial silicon layer, a channel region formed between the source and drain regions, and a gate electrode formed on the channel region with a gate insulating film interposed therebetween, an element isolation region being sandwiched between adjacent transistor structures, wherein a punch-through stopper layer formed in a lower portion of the channel region has an impurity concentration higher than that of the channel region, and the source-drain diffusion layers do not extend to overlap with edge portion of insulating films for the element isolation.

Abstract: A method of fabricating a thin film transistor substrate for an X-ray detector reduces the number of steps in etching processes using masks. In the method, a gate line, a gate pad and a gate electrode of a thin film transistor are simultaneously formed on a certain substrate. A gate insulating layer is entirely coated, and then a semiconductor layer of the thin film transistor is formed. A data pad, a data line, source and drain electrodes of the thin film transistor and a ground electrode are simultaneously formed. An electrode for a charging capacitor is formed, and then an insulating film for the charging capacitor is formed. An electrode for preventing an etching of the insulating film for the charging capacitor is formed. A protective film for protecting the thin film transistor is formed. Contact holes are formed in the protective film. Finally, a pixel electrode is provided.

Abstract: In a SiC substrate (10), a first active region (12) composed of n-type heavily doped layers (12a) and undoped layers (12b), which are alternately stacked, and a second active region (13) composed of p-type heavily doped layers (13a) and undoped layers (13b), which are alternately stacked, are provided upwardly in this order. A Schottky diode (20) and a pMOSFET (30) are provided on the first active region (12). An nMOSFET (40), a capacitor (50), and an inductor (60) are provided on the second active region (13). The Schottky diode (20) and the MOSFETs (30, 40) have a breakdown voltage characteristic and a carrier flow characteristic due to a multilayer structure composed of &dgr;-doped layers and undoped layers and are integrated in a common substrate.

Abstract: Semiconductor structure configured as a semiconductor switch that can be used in various forms to switch currents. Semiconductor switch comprising non-doped or very lightly doped semiconductor crystal for switching currents in at least one direction at higher to high voltages which are significantly higher than the operating voltages of gate circuits, comprising an active region and a termination portion, wherein at least one opposite surface of the active region is provided with fine structures distributed over a wide area, which structures are substantially uniformly configured and include one conductive terminal surface each, by which charge carriers can be moved in a controlled manner into the active region of the semiconductor crystal via the fine structures in order to control a concentration of the charge carriers in the active region and thus the off-state and/or on-state of the semiconductor switch.

Abstract: A high-voltage component and a method for its manufacture. The component functions to switch currents at high voltages. The component is composed of partial components that are connected in series and are laterally supported on a self-supporting semiconductor wafer. The partial components switch through, for example, at a given voltage applied between a first bridge cathode and an anodic metallization.