Abstract: A circuit including a source, a load, and an isolation circuit for controllably isolating the load from the source. The isolation circuit is disposed between the source and the load. The isolation circuit includes at least one insulated-gate bipolar transistor (IGBT) and at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor. When no fault condition exists, the GTO is configured to be ON to couple the load to the source. When a fault condition exists, the at least one IGBT is configured to turn ON. After the at least one IGBT turns ON, the at least one GTO is configured to turn OFF. After a predetermined amount of time, reflecting the post fabrication alteration to the GTO's minority carrier lifetime (e.g. electron irradiation), after the at least one GTO turns OFF, the at least one IGBT is configured to turn OFF.

Abstract: Non-crystalline silicon non-volatile resistive switching devices include a metal electrode, a non-crystalline silicon layer and a planar doped silicon electrode. An electrical signal applied to the metal electrode drives metal ions from the metal electrode into the non-crystalline silicon layer to form a conducting filament from the metal electrode to the planar doped silicon electrode to alter a resistance of the non-crystalline silicon layer. Another electrical signal applied to the metal electrode removes at least some of the metal ions forming the conducting filament from the non-crystalline silicon layer to further alter the resistance of the non-crystalline silicon layer.

Abstract: The present invention relates to a sensor including a core-shell nanostructure, and more particularly, to a sensor including: a base material; a sensing part including a core-shell nanostructure that has a core including a first metal oxide and a shell including a second metal oxide formed on the core; and two electrode layers spaced from each other on the sensing part.

Abstract: An RF switch is provided with a direct heating method. The RF switch is comprised of two RF electrodes disposed on opposing sides of a phase change element. Depending on the state of the phase change material, the RF electrodes form a conductive path through the phase change material for an RF signal. To control the state of the phase change material, the RF switch further includes a heater formed from two heater electrodes. The two heater electrodes are configured to draw a current through the phase change element in a direction transverse to the conductive path.

Abstract: A micro-electro-mechanical system (MEMS), methods of forming the MEMS and design structures are provided. The method includes forming a coplanar waveguide (CPW) comprising a signal electrode and a pair of electrodes on a substrate. The method includes forming a first sacrificial material over the CPW, and a wiring layer over the first sacrificial material and above the CPW. The method includes forming a second sacrificial material layer over the wiring layer, and forming insulator material about the first sacrificial material and the second sacrificial material. The method includes forming at least one vent hole in the insulator material to expose portions of the second sacrificial material, and removing the first and second sacrificial material through the vent hole to form a cavity structure about the wiring layer and which exposes the signal line and pair of electrodes below the wiring layer. The vent hole is sealed with sealing material.

Abstract: A vertical power component including a silicon substrate of a first conductivity type and, on the side of a lower surface supporting a single electrode, a well of the second conductivity type, in which the component periphery includes, on the lower surface side, a peripheral trench at least partially filled with a passivation and, between the well and the trench, a porous silicon insulating ring.

Abstract: A semiconductor light emitting device includes a structural body, a first electrode layer, an intermediate layer and a second electrode layer. The structural body includes a first semiconductor layer of first conductivity type, a second semiconductor layer of second conductivity type, and a light emitting layer between the first and second semiconductor layers. The first electrode layer is on a side of the second semiconductor layer opposite to the first semiconductor layer; the first electrode layer includes a metal portion and plural opening portions piercing the metal portion along a direction from the first semiconductor layer toward the second semiconductor layer, having an equivalent circular diameter not less than 10 nanometers and not more than 5 micrometers. The intermediate layer is between the first and second semiconductor layers in ohmic contact with the second semiconductor layer. The second electrode layer is electrically connected to the first semiconductor layer.

Abstract: Provided is a semiconductor rectifier device. The semiconductor rectifier device may include a substrate doped with a first conductive type, a second electrode provided on a bottom surface of the substrate, an active region and a field region defined on the substrate, a gate provided in the active region, a gate insulating film provided between the gate and the substrate, body regions provided on the substrate adjacent to first and second sides of the gate, facing each other, and doped with a second conductive type dopant different from the first conductive type, and a second conductive type plug region formed on the substrate adjacent to third and fourth sides of the gate, connecting the first and second sides.

Abstract: According to a method of fabricating the semiconductor memory device, a contact plug can be protected while mold openings are formed. A semiconductor memory device may include a mold dielectric layer on an entire surface of a substrate, the substrate including a first region and a second region. A contact plug may be provided in a contact hole formed through the mold dielectric layer in the first region. A variable resistor may be provided in a mold opening formed through the mold dielectric layer in the second region. An upper surface of the contact plug may be at a level equal to or lower than an upper surface of the mold dielectric layer.

Abstract: A modified MOSFET structure comprises an integrated field effect rectifier connected between the source and drain of the MOSFET to shunt current during switching of the MOSFET. The integrated FER provides faster switching of the MOSFET due to the absence of injected carriers during switching while also decreasing the level of EMI relative to discrete solutions. The integrated structure of the MOSFET and FER can be fabricated using N-, multi-epitaxial and supertrench technologies, including 0.25 ?m technology. Self-aligned processing can be used.

Abstract: Disclosed is a method for controlling the recombination rate in the base region of a bipolar semiconductor component, and a bipolar semiconductor component.

Abstract: A SiC semiconductor device includes: a SiC substrate including a first or second conductive type layer and a first conductive type drift layer and including a principal surface having an offset direction; a trench disposed on the drift layer and having a longitudinal direction; and a gate electrode disposed in the trench via a gate insulation film. A sidewall of the trench provides a channel formation surface. The vertical semiconductor device flows current along with the channel formation surface of the trench according to a gate voltage applied to the gate electrode. The offset direction of the SiC substrate is perpendicular to the longitudinal direction of the trench.

Abstract: A 1D nanowire photodetector device includes a nanowire that is individually contacted by electrodes for applying a longitudinal electric field which drives the photocurrent. An intrinsic radial electric field to inhibits photo-carrier recombination, thus enhancing the photocurrent response. Circuits of 1D nanowire include groups of photodetectors addressed by their individual 1D nanowire electrode contacts. Placement of 1D nanostructures is accomplished with registration onto a substrate. A substrate is patterned with a material, e.g., photoresist, and trenches are formed in the patterning material at predetermined locations for the placement of 1D nanostructures. The 1D nanostructures are aligned in a liquid suspension, and then transferred into the trenches from the liquid suspension. Removal of the patterning material places the 1D nanostructures in predetermined, registered positions on the substrate.

Abstract: A rectifier building block has four electrodes: source, drain, gate and probe. The main current flows between the source and drain electrodes. The gate voltage controls the conductivity of a narrow channel under a MOS gate and can switch the RBB between OFF and ON states. Used in pairs, the RBB can be configured as a three terminal half-bridge rectifier which exhibits better than ideal diode performance, similar to synchronous rectifiers but without the need for control circuits. N-type and P-type pairs can be configured as a full bridge rectifier. Other combinations are possible to create a variety of devices.

Abstract: A switching element comprising: an insulative substrate; a first electrode and a second electrode provided on one surface of the insulative substrate; and an interelectrode gap which is provided between the first electrode and the second electrode, and which has a gap on the order of nanometers in which switching phenomenon of resistance occurs by applying predetermined voltage between the first electrode and the second electrode, wherein the one surface of the insulative substrate contains nitrogen.

Abstract: Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

Abstract: A power semiconductor structure with a field effect rectifier having a drain region, a body region, a source region, a gate channel, and a current channel is provided. The body region is substantially located above the drain region. The source region is located in the body region. The gate channel is located in the body region and adjacent to a gate structure. The current channel is located in the body region and is extended from the source region downward to the drain region. The current channel is adjacent to a conductive structure coupled to the source region.

Abstract: An IGBT with a fast reverse recovery time rectifier includes an N-type drift epitaxial layer, a gate, a gate insulating layer, a P-type doped base region, an N-type doped source region, a P-type doped contact region, and a P-type lightly doped region. The P-type doped base region is disposed in the N-type drift epitaxial layer, and the P-type doped contact region is disposed in the N-type drift epitaxial layer. The P-type lightly doped region is disposed between the P-type contact doped region and the N-type drift epitaxial layer, and is in contact with the N-type drift epitaxial layer.

Abstract: A graphene-based memristor includes a first electrode, a defective graphene layer adjacent the first electrode, a memristive material that includes a number of ions adjacent the defective graphene layer, a second electrode adjacent the memristive material, and a voltage source that generates an electric field between the first and the second electrodes. Under the influence of the electric field, ions in the memristive material form an ion conducting channel between the second electrode and the defective graphene layer.

Abstract: An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference.

Abstract: A power semiconductor structure with a field effect rectifier having a drain region, a body region, a source region, a gate channel, and a current channel is provided. The body region is substantially located above the drain region. The source region is located in the body region. The gate channel is located in the body region and adjacent to a gate structure. The current channel is located in the body region and is extended from the source region downward to the drain region. The current channel is adjacent to a conductive structure coupled to the source region.

Abstract: An over-voltage protection thyristor has reduced junction capacitance making it suitable for use in high bandwidth applications. The reduced capacitance is achieved through the introduction of a deep base region. The deep base region has a graded doping concentration which reduces with depth into the substrate. The thyristor is useful for protecting sensitive electrical equipment from transient surges.

Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.

Abstract: Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements comprise one or more structures based on Phase Change Memory, Programmable Metallization, Carbon Nano-Electromechanical (CNT-NEM), or Metal Nano-Electromechanical device technologies.

Abstract: The present invention provides a semiconductor apparatus for improving a switching speed and a withstand voltage, and a manufacturing method of the semiconductor apparatus.

Abstract: A switching element for ON/OFF switching includes a pair of electrodes provided on a substrate separately from each other, a phase change film contacting the electrodes and having its resistance varied in accordance with the history of heating, and a heating mechanism for heating the phase change film.

Abstract: Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements comprise one or more structures based on Phase Change Memory, Programmable Metallization, Carbon Nano-Electromechanical (CNT-NEM), or Metal Nano-Electromechanical device technologies.

Abstract: An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference.

Abstract: The present invention comprises an integrated circuit fabricated on a single substrate where the integrated circuit comprises a first block comprising an enhancement mode pHEMT transistor on a substrate; a second block comprising a depletion mode pHEMT transistor on the substrate, the second block operatively connected to the first block; and a third block comprising a power pHEMT transistor on the substrate, the third block operatively connected to at least one of the first block and the second block. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope of meaning of the claims.

Abstract: A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.

Abstract: A power semiconductor device having high avalanche capability comprises an N+ doped substrate and, in sequence, N? doped, P? doped, and P+ doped semiconductor layers, the P? and P+ doped layers having a combined thickness of about 5 ?m to about 12 ?m. Recombination centers comprising noble metal impurities are disposed substantially in the N? and P? doped layers. A process for forming a power semiconductor device with high avalanche capability comprises: forming an N? doped epitaxial layer on an N+ doped substrate, forming a P? doped layer in the N? doped epitaxial layer, forming a P+ doped layer in the P? doped layer, and forming in the P? and N? doped layers recombination centers comprising noble metal impurities. The P+ and P? doped layers have a combined thickness of about 5 ?m to about 12 ?m.

Abstract: Organic light emitting devices include an anode, a cathode and a plurality of organic light emitting units. The adjacent organic light emitting units are separated by a charge transfer layer formed of various fullerenes in combination. The charge transfer layer may be a relatively homogenous layer that is a mixture comprising fullerene.

Abstract: A semiconductor device comprises: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type provided on the semiconductor layer, the first semiconductor region being one of an anode region and a cathode region; a second semiconductor region of the first conductivity type provided on the first semiconductor region, the second semiconductor region being the other of the anode region and the cathode region; and a semiconductor buried region of the second conductivity type provided between the semiconductor layer and the first semiconductor region. The semiconductor buried region has an aperture where the first semiconductor region is in contact with the semiconductor layer.

Abstract: An electronic power device comprising a single crystal silicon segment being characterized in that the segment comprises a non-uniform distribution of minority carrier recombination centers, the minority carrier recombination centers comprising a substitutional metal, with the concentration of the centers in a bulk layer being greater than the concentration in a surface layer. The centers have a concentration profile in which the peak density of the centers is at or near the central plane with the concentration generally decreasing from the position of peak density in the direction of the front surface of the segment and generally decreasing from the position of peak density in the direction of the back surface of the segment.

Abstract: The invention relates to a semiconductor circuit (20) having an electrically programmable switching element (10), an “antifuse”, which includes a substrate electrode (2), produced in a substrate (1) which can be electrically biased with a substrate potential (Vo), and an opposing electrode (5) which is isolated from the substrate electrode (2) by an insulating layer (8), where the substrate electrode (2) includes at least one highly doped substrate region (3), and where the opposing electrode (5) can be connected to an external first electrical potential (V+) which can be provided outside of the semiconductor circuit (20). In line with the invention, the substrate electrode (2) can be connected to a second electrical potential (V?), which is provided inside the circuit and which, together with the external first potential (V+), produces a higher programming voltage (V) than the external first potential (V?) together with the substrate potential (Vo).

Abstract: A switching semiconductor device includes a first compound layer formed on a single crystal substrate which includes silicon carbide or sapphire, and including a general formula InxGa1-xN, where 0?x?1; a second compound layer formed on the first compound layer, and including a general formula InyALzGa1-y-zN, where 0?y?1 and 0<z?1; and a gate electrode formed on the second compound layer. The gate electrode is electrically connected to a resistance element formed on a first interlayer insulating film that covers the gate electrode, through a metal wiring formed on a second interlayer insulating film that covers the first interlayer insulating film.

Abstract: A power switching device comprises a semiconductor substrate; a plurality of cells, each of which switches a current from a power supply to a load on the basis of a potential at a gate electrode, said cells being arranged on said semiconductor substrate to form a cell array; and a plurality of drivers connected to the gate electrode, said plurality of drivers being distributively arranged in said cell array or being distributively arranged peripheral said cell array.

Abstract: Switching operations, such as those used in memory devices, are enhanced using a thyristor-based semiconductor device adapted to switch between a blocking state and a conducting state. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor having first and second base regions coupled between first and second emitter regions, respectively. A first control port capacitively couples a first signal to the first base region, and a second control port capacitively couples a second signal to the second base region. Each of the first and second signals have a charge that is opposite in polarity, and the opposite polarity signals effect the switching of the thyristor at a lower power, relative to the power that would be required to switch the thyristor having only one control port.

Abstract: A high power switch includes diode and BJT structures interdigitated in a drift layer and separated by insulated trench gates; electrodes contacting the diode and BJT structures provide anode and cathode connections. Shallow N+ regions extend below and around the corners of the oxide side-walls and bottoms of respective gates. A voltage applied across the anode and cathode sufficient to forward bias the diode's p-n junction causes electrons to be injected which provide a base drive current to the BJT sufficient to turn it on and enable current to flow from anode to cathode via the diode and BJT structures. A gate voltage sufficient to reverse bias the junction between the shallow N+ regions and the drift layer forms a potential barrier which blocks current flow through the diode and BJT structures and eliminates the base drive current such that the BJT and said switch are turned off.

Abstract: A structure of a p-electrode formed at the light-emerging side of an LED that comprises (a) an n-type semiconductor substrate, (b) an n-type cladding layer, an active layer, a p-type cladding layer, and a p-type contact layer formed on the substrate in this order, and (c) an n-electrode formed on the back face of the substrate. The structure of the p-electrode comprises a mesh-shaped semi-transparent thin-film metal electrode for diffusing electric current formed on the p-type contact layer and a bonding electrode for wire bonding. The metal electrode comprises a covering portion having a transmittance of at least 10% and an opening portion having an opening ratio of at least 20%. The bonding electrode is formed at the periphery of the p-type contact layer and is bonded directly to the mesh-shaped semi-transparent thin-film metal electrode. This structure can increase the intensity of the output light emerging from the p-side.

Abstract: A process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the segment is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The segment is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a segment having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the segment. Platinum atoms are then in-diffused into the silicon matrix such that the resulting platinum concentration profile is substantially related to the concentration profile of the crystal lattice vacancies.

Abstract: The switching element has a switching layer between a first electrode layer and a second electrode layer. The switching layer includes a charge transfer complex containing an electron donor and an electron acceptor. An insulating layer is provided between the first electrode layer and the switching layer, and contacts the switching layer. The switching layer switches from a high-resistance state to a low-resistance state upon application of a voltage greater than a first threshold value in a first bias direction. Thereafter, the switching layer maintains the low-resistance state when the applied voltage decreases beyond the first threshold value. When the applied voltage becomes not smaller than a second threshold value in a second bias direction or a reverse direction to the first bias direction, the switching layer switches from the low-resistance state to the high-resistance state.

Abstract: A power switching device comprises a semiconductor substrate; a plurality of cells, each of which switches a current from a power supply to a load on the basis of a potential at a gate electrode, said cells being arranged on said semiconductor substrate to form a cell array; and a plurality of drivers connected to the gate electrode, said plurality of drivers being distributively arranged in said cell array or being distributively arranged peripheral said cell array.

Abstract: The switching element has a switching layer between a first electrode layer and a second electrode layer. The switching layer includes a charge transfer complex containing an electron donor and an electron acceptor. An insulating layer is provided between the first electrode layer and the switching layer, and contacts the switching layer. The switching layer switches from a high-resistance state to a low-resistance state upon application of a voltage greater than a first threshold value in a first bias direction. Thereafter, the switching layer maintains the low-resistance state when the applied voltage decreases beyond the first threshold value. When the applied voltage becomes not smaller than a second threshold value in a second bias direction or a reverse direction to the first bias direction, the switching layer switches from the low-resistance state to the high-resistance state.

Abstract: A semiconductor circuit configuration is described, in particular for ignition applications, having a semiconductor power switching device (100) which has a first main terminal (102), a second main terminal (101) and a control terminal (103); a clamping diode device (205a, 205b) which is switched between the first main terminal (102) and the control terminal (103) for clamping an external voltage (VA) which is applied at the first main terminal (202); the clamping diode device (205a, 205b) having a first part (205a) with a first clamp voltage and a second part (205b) with a second clamp voltage (VKL′), the second part (205b) being connected in series with the first part (205a); a controllable semiconductor switching device (402, 650) which is connected in parallel with the first part (205a) for controllable bridging of the first part (205a), so that either the sum (VKL) of the first and the second clamp voltages, or the second clamp voltage (VKL′) is provided for clamping the external voltage (VA)

Abstract: A semiconductor device comprises a first semiconductor layer of a first conductivity type provided on a semiconductor substrate of the first conductivity type, a base layer of a second conductivity type provided in the first semiconductor layer, for defining a vertical MISFET including source regions and a gate electrode on a gate insulation film, a Schottky barrier diode (SBD)-forming region provided in the first semiconductor layer around the base layer, a guard ring region of the second conductivity type provided around SBD-forming region, a first main electrode disposed above the first semiconductor layer and provided in common as both a source electrode of the MISFET and an anode of the SBD, a surface gate electrode disposed above the first semiconductor layer, and a second main electrode provided in common as a drain electrode of the MISFET and a cathode of the SBD.

Abstract: Microswitch, comprising a base element (G) with a contact surface (KG) and an electrode (EG), and a switching element (S) with a contact surface (KS) and an electrode (ES) disposed opposite the electrode (EG) of the base element (G) at a distance (g). The switching element (S) is provided with a spring constant and is connected at least with a part of its edge portion with the base element (G) in a fixed manner. The contact surfaces (KG, KS) form a switching contact which is closable against a reaction force caused by the spring constant by means of a voltage applied to the electrodes (EG, ES). The base element (G) and the switching element (S) each comprise an auxiliary electrode (HG, HS) at a distance (a) from the electrode (EG, ES), to which a voltage can be applied. For opening the switching contact the electrodes (EG, ES) have a first voltage potential (U1) and the auxiliary electrodes have a second voltage potential (U2) of the voltage.

Abstract: A device (10) comprises a semiconductor diode (12) and a switchable element (14) positioned in stacked adjacent relationship so that the semiconductor diode (12) and the switchable element (14) are electrically connected in series with one another. The switchable element (14) is switchable from a low-conductance state to a high-conductance state in response to the application of a forming voltage to the switchable element (14).

Abstract: A monolithic bidirectional switch formed in a semiconductor substrate of type N, including a first main vertical thyristor, the rear surface layer of which is of type P, a second main vertical thyristor, the rear surface layer of which is of type N, an auxiliary vertical thyristor, the rear surface layer of which is of type P and is common with that of the first main thyristor, a peripheral region of type P especially connecting the rear surface layer of the auxiliary thyristor to the layer of this thyristor located on the other side of the substrate, a first metallization on the rear surface side, a second metallization on the front surface side connecting the front surface layers of the first and second thyristors. An additional region has a function of isolating the rear surface of the auxiliary thyristor and the first metallization.

Abstract: In order that the DC potential of the input terminal does not rise, whereby ON/OFF switching is accordingly performed normally, even when a signal having a large amplitude is inputted to an input terminal, thereby the depletion layer expands due to electron trapping effect, a first field effect transistor is connected between a first switch input terminal and a first switch output terminal in a manner that the source is arranged on the first switch input terminal side, a second field effect transistor is connected between the first switch output terminal and a second switch input terminal in a manner that the source is arranged on the second switch input terminal side, a third field effect transistor is connected between the second switch input terminal and a second switch output terminal in a manner that the source is arranged on the second switch input terminal side, and a fourth field effect transistor is connected between the second switch output terminal and the first switch input terminal in a manner th