With Extended Latchup Current Level (e.g., Gate Turn Off "gto" Device) Patents (Class 257/147)
  • Patent number: 7902601
    Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: March 8, 2011
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, John M. Parsey, Jr., Peter J. Zdebel, Gordon M. Grivna
  • Publication number: 20110049564
    Abstract: This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 3, 2011
    Inventors: Lingpeng Guan, Anup Bhalla, Madhur Bobde, Tinggang Zhu
  • Publication number: 20110049561
    Abstract: Provided is a semiconductor bistable switching device that includes a thyristor portion including an anode layer, a drift layer, a gate layer and a cathode layer, the gate layer operable to receive a gate trigger current that, when the anode layer is positively biased relative to the cathode layer, causes the thyristor portion to latch into a conducting mode between the anode and the cathode. The device also includes a transistor portion formed on the thyristor portion, the transistor portion including a source, a drain and a transistor gate, the drain coupled to the cathode of the thyristor portion.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 3, 2011
    Inventors: Robert J. Callanan, Sei-Hyung Ryu, Qingchun Zhang
  • Publication number: 20110018029
    Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.
    Type: Application
    Filed: July 21, 2009
    Publication date: January 27, 2011
    Applicant: Infineon Technologies Austria AG
    Inventors: Frank Pfirsch, Maria Cotorogea, Franz Hirler, Franz-Josef Niedernostheide, Thomas Raker, Hans-Joachim Schulze, Hans Peter Felsl
  • Patent number: 7834377
    Abstract: A finger length a1 of a transistor P11 is longer than a finger length A1 of a transistor P1, and a finger length b1 of a transistor N11 is longer than a finger length B1 of a transistor N1. The finger length b1 of the transistor N11 is shorter than the finger length A1 of the transistor P1, and the relation: a1>A1>b1>B1 is established. In a relation between an I/O section and a logic circuit section, as for MOS transistor of the same conductive type, a finger length of a MOS transistor constituting the logic circuit section is set so as to be longer than a finger length of a MOS transistor constituting the I/O section.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: November 16, 2010
    Assignee: Renesas Electronics Corporation
    Inventor: Toshiaki Iwamatsu
  • Publication number: 20100283529
    Abstract: An electronic device includes a wide bandgap thyristor having an anode, a cathode, and a gate terminal, and a wide bandgap bipolar transistor having a base, a collector, and an emitter terminal. The emitter terminal of the bipolar transistor is directly coupled to the anode terminal of the thyristor such that the bipolar transistor and the thyristor are connected in series. The bipolar transistor and the thyristor define a wide bandgap bipolar power switching device that is configured to switch between a nonconducting state and a conducting state that allows current flow between a first main terminal corresponding to the collector terminal of the bipolar transistor and a second main terminal corresponding to the cathode terminal of the thyristor responsive to application of a first control signal to the base terminal of the bipolar transistor and responsive to application of a second control signal to the gate terminal of the thyristor. Related control circuits are also discussed.
    Type: Application
    Filed: May 8, 2009
    Publication date: November 11, 2010
    Inventors: Qingchun Zhang, James Theodore Richmond, Robert J. Callanan
  • Patent number: 7816706
    Abstract: The power semiconductor device with a four-layer npnp structure can be turned-off via a gate electrode. The first base layer comprises a cathode base region adjacent to the cathode region and a gate base region adjacent to the gate electrode, but disposed at a distance from the cathode region. The gate base region has the same nominal doping density as the cathode base region in at least one first depth, the first depth being given as a perpendicular distance from the side of the cathode region, which is opposite the cathode metallization. The gate base region has a higher doping density than the cathode base region and/or the gate base region has a greater depth than the cathode base region in order to modulate the field in blocking state and to defocus generated holes from the cathode when driven into dynamic avalanche.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: October 19, 2010
    Assignee: ABB Technology AG
    Inventors: Munaf Rahimo, Peter Streit
  • Patent number: 7732833
    Abstract: In a base region of a first conductivity type, at least one emitter region of a second conductivity type and at least one sense region of the second conductivity type, spaced away from the emitter region, are selectively formed. The emitter region and the sense region are located so as to be aligned in a second direction perpendicular to a first direction going from a collector region of the first conductivity type, which is formed so as to be spaced away from the base region, toward the base region. The width of the sense region, the width of the emitter region, the width of a part of the base region that is adjacent to the sense region, and the width of a part of the base region that is adjacent to the emitter region in the second direction are set in such a manner that a sense ratio varies in a desired manner in accordance with variation in collector current.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: June 8, 2010
    Assignee: Panasonic Corporation
    Inventors: Hiroto Yamagiwa, Takashi Saji
  • Patent number: 7705368
    Abstract: An insulated gate type thyristor includes: a first current terminal semiconductor region of a first conductivity type having a high impurity concentration; a first base semiconductor region of a second conductivity type opposite to the first conductivity type having a low impurity concentration and formed on the first current terminal semiconductor region; a second base semiconductor region of the first conductivity type having a low impurity concentration and formed on the first base semiconductor region; a second current terminal semiconductor region of the second conductivity type having a high impurity concentration and formed on the second base semiconductor region; a trench passing through the second current terminal semiconductor region and entering the second base semiconductor region leaving some depth thereof, along a direction from a surface of the second current terminal semiconductor region toward the first base semiconductor region; and an insulated gate electrode structure formed in the trench.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: April 27, 2010
    Assignee: Fujifilm Corporation
    Inventors: Vladimir Rodov, Hidenori Akiyama
  • Patent number: 7696530
    Abstract: A sensor includes a first gate electrode, a second gate electrode, a semiconductor layer, a gate-insulating layer, a source electrode, a drain electrode, and a sensing portion including an accommodating part and a receiving layer. The first and second gate electrodes are opposed to each other with the sensing portion, the semiconductor layer, and the gate-insulating layer therebetween. One surface of the semiconductor layer is in contact with a surface of the sensing portion, and another surface of the semiconductor layer is in contact with the gate-insulating layer. A surface of the gate-insulating layer is in contact with the second gate electrode. The first gate electrode and the receiving layer are opposed to each other with the accommodating part therebetween. The source and drain electrodes are in contact with the semiconductor layer.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: April 13, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tetsushi Yamamoto, Tadahiko Hirai, Shunji Imanaga
  • Patent number: 7692211
    Abstract: A gate turn-off thyristor (GTO) device has a lower portion, an upper portion and a lid. The lower portion has a lower base region of a first conductivity type, and a lower emitter region of a second conductivity type disposed at or from a lower surface of the lower base region. A lower junction is formed between the lower base region and the lower emitter region. The upper portion has an upper base region of the second conductivity type, and upper emitter regions of the first conductivity type disposed at or from an upper surface of the upper base region. An upper-lower junction is formed between the lower base region and the upper base region, and upper junctions are formed between the upper base region and the upper emitter regions. The upper base region and upper emitter regions form an upper base surface with first conductive contacts to the upper base region alternating with second conductive contacts to the upper emitter regions. The lid has a layer of insulator with upper and lower surfaces.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: April 6, 2010
    Assignee: Silicon Power Corporation
    Inventors: Vic Temple, Forrest Holroyd, Sabih Al-Marayati, Deva Pattanayak
  • Publication number: 20090309132
    Abstract: A lateral Insulated Gate Bipolar Transistor (LIGBT) includes a semiconductor substrate and an anode region in the semiconductor substrate. A cathode region of a first conductivity type in the substrate is laterally spaced from the anode region, and a cathode region of a second conductivity type in the substrate is located proximate to and on a side of the cathode region of the first conductivity type opposite from the anode region. A drift region in the semiconductor substrate extends between the anode region and the cathode region of the first conductivity type. An insulated gate is operatively coupled to the cathode region of the first conductivity type and is located on a side of the cathode region of the first conductivity type opposite from the anode region. An insulating spacer overlies the cathode region of the second conductivity type.
    Type: Application
    Filed: March 26, 2009
    Publication date: December 17, 2009
    Inventor: Jun Cai
  • Patent number: 7582939
    Abstract: The invention relates to a semiconductor diode, an electronic component and to a voltage source converter. According to the invention, the semiconductor diode having at least one pn-transition can be switched between a first state and a second state. In comparison to the first state, the second state has a greater on-state resistance and a smaller accumulated charge, and the pn-transition is capable of blocking both in the first state as well as in the second state with at least one predetermined blocking ability. An MOS-controlled diode is hereby obtained in which the transition from the on-state to the blocking state is simplified and is thus not critical with regard to the temporal sequence of the control pulses.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: September 1, 2009
    Assignee: Siemens Aktiengesellschaft
    Inventors: Mark-Matthias Bakran, Hans-Günter Eckel
  • Patent number: 7560773
    Abstract: A vertical-type semiconductor device for controlling a current flowing between electrodes opposed against each other across a semiconductor substrate, including: a semiconductor substrate having first and second surfaces opposed against each other; a first electrode formed in the first surface; a second electrode formed in the second surface through a high-resistance electrode whose resistance is Rs; and a third electrode formed along at least a part of the outer periphery of the second surface, wherein a potential difference Vs between the second and third electrodes is measured with a current I flowing between the first and second electrodes, and the current I is detected from the resistance Rs and the potential difference Vs.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: July 14, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masahiro Tanaka
  • Publication number: 20090152587
    Abstract: An embodiment of an integrated circuit includes a semiconductor layer, a well, first and second source/drain regions, and a guard region. The semiconductor layer has a first conductivity, and the well is disposed in the layer and has a second conductivity. The first source/drain region is formed in the well and has the first conductivity, and the second source/drain region is formed in the layer outside of the well and has the second conductivity. The guard region is disposed in the layer between the well and the second source/drain region and has the second conductivity. The guard region may prevent latch up by inhibiting the triggering of a silicon-controlled rectifier (SCR) having one of the first and second source/drain regions as an anode and the other of the first and second source/drain regions as a cathode.
    Type: Application
    Filed: December 15, 2008
    Publication date: June 18, 2009
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Lorenzo CERATI, Luca CECCHETTO, Mariano DISSEGNA
  • Patent number: 7544970
    Abstract: The temperature of a bipolar semiconductor element using a wide-gap semiconductor is raised using heating means, such as a heater, to obtain a power semiconductor device being large in controllable current and low in loss. The temperature is set at a temperature higher than the temperature at which the decrement of the steady loss of the wide-gap bipolar semiconductor element corresponding to the decrement of the built-in voltage lowering depending on the temperature rising of the wide-gap bipolar semiconductor element is larger than the increment of the steady loss corresponding to the increment of the ON resistance increasing depending on the temperature rising.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: June 9, 2009
    Assignee: The Kansai Electric Power Co., Inc.
    Inventor: Yoshitaka Sugawara
  • Patent number: 7498614
    Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: March 3, 2009
    Assignee: Third Dimension (3D) Semiconductor, Inc.
    Inventor: Xing-bi Chen
  • Patent number: 7462888
    Abstract: The temperature of a bipolar semiconductor element using a wide-gap semiconductor is raised using heating means, such as a heater, to obtain a power semiconductor device being large in controllable current and low in loss. The temperature is set at a temperature higher than the temperature at which the decrement of the steady loss of the wide-gap bipolar semiconductor element corresponding to the decrement of the built-in voltage lowering depending on the temperature rising of the wide-gap bipolar semiconductor element is larger than the increment of the steady loss corresponding to the increment of the ON resistance increasing depending on the temperature rising.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: December 9, 2008
    Assignee: The Kansai Electric Power Co., Inc.
    Inventor: Yoshitaka Sugawara
  • Patent number: 7462886
    Abstract: The temperature of a bipolar semiconductor element using a wide-gap semiconductor is raised using heating means, such as a heater, to obtain a power semiconductor device being large in controllable current and low in loss. The temperature is set at a temperature higher than the temperature at which the decrement of the steady loss of the wide-gap bipolar semiconductor element corresponding to the decrement of the built-in voltage lowering depending on the temperature rising of the wide-gap bipolar semiconductor element is larger than the increment of the steady loss corresponding to the increment of the ON resistance increasing depending on the temperature rising.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: December 9, 2008
    Assignee: The Kansai Electric Power Co., Inc.
    Inventor: Yoshitaka Sugawara
  • Patent number: 7456439
    Abstract: A semiconductor device may comprise a plurality of memory cells. A memory cell may comprise a thyristor, at least a portion of which is formed in a pillar of semiconductor material. The pillar may comprise sidewalls defining a cylindrical circumference of a first diameter. In a particular embodiment, the pillars associated with the plurality of memory cells may define rows and columns of an array. In a further embodiment, a pillar may be spaced by a first distance of magnitude up to the first diameter relative to a neighboring pillar within its row. In an additional further embodiment, the pillar may be spaced by a second distance of a magnitude up to twice the first diameter, relative to a neighboring pillar within its column.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: November 25, 2008
    Assignee: T-RAM Semiconductor, Inc.
    Inventor: Andrew E. Horch
  • Publication number: 20080164490
    Abstract: The power semiconductor device with a four-layer npnp structure can be turned-off via a gate electrode. The first base layer comprises a cathode base region adjacent to the cathode region and a gate base region adjacent to the gate electrode, but disposed at a distance from the cathode region. The gate base region has the same nominal doping density as the cathode base region in at least one first depth, the first depth being given as a perpendicular distance from the side of the cathode region, which is opposite the cathode metallization. The gate base region has a higher doping density than the cathode base region and/or the gate base region has a greater depth than the cathode base region in order to modulate the field in blocking state and to defocus generated holes from the cathode when driven into dynamic avalanche.
    Type: Application
    Filed: January 16, 2008
    Publication date: July 10, 2008
    Applicant: ABB Technology AG
    Inventors: Munaf Rahimo, Peter Streit
  • Patent number: 7391057
    Abstract: High voltage silicon carbide (SiC) devices, for example, thyristors, are provided. A first SiC layer having a first conductivity type is provided on a first surface of a voltage blocking SiC substrate having a second conductivity type. A first region of SiC is provided on the first SiC layer and has the second conductivity type. A second region of SiC is provided in the first SiC layer. The second region of SiC has the first conductivity type and is adjacent to the first region of SiC. A second SiC layer having the first conductivity type is provided on a second surface, opposite the first surface, of the voltage blocking SiC substrate. First, second and third contacts are provided on the first region of SiC, the second region of SiC and the second SiC layer, respectively. Related methods of fabricating high voltage SiC devices are also provided.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: June 24, 2008
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Jason R. Jenny, Mrinal K. Das, Hudson McDonald Hobgood, Anant K. Agarwal, John W. Palmour
  • Publication number: 20080128744
    Abstract: A lateral Insulated Gate Bipolar Transistor (LIGBT) includes a semiconductor substrate and an anode region in the semiconductor substrate. A cathode region of a first conductivity type in the substrate is laterally spaced from the anode region, and a cathode region of a second conductivity type in the substrate is located proximate to and on a side of the cathode region of the first conductivity type opposite from the anode region. A drift region in the semiconductor substrate extends between the anode region and the cathode region of the first conductivity type. An insulated gate is operatively coupled to the cathode region of the first conductivity type and is located on a side of the cathode region of the first conductivity type opposite from the anode region. An insulating spacer overlies the cathode region of the second conductivity type.
    Type: Application
    Filed: November 30, 2006
    Publication date: June 5, 2008
    Inventor: Jun Cai
  • Patent number: 7335947
    Abstract: An insulated gate trench type semiconductor device having L-shaped diffused regions, each diffused region having a vertically oriented portion and a horizontally oriented portion extending laterally from the vertically oriented portion, and a method for manufacturing the device in which the vertically oriented portion of each L-shaped diffused region is formed by directing dopants at an angle toward a sidewall of a trench to form the vertically oriented portion using the edge of the opposing sidewall of the trench as a mask.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: February 26, 2008
    Assignee: International Rectifier Corporation
    Inventors: Richard Francis, Chiu Ng
  • Publication number: 20070295988
    Abstract: A sensor includes a first gate electrode, a second gate electrode, a semiconductor layer, a gate-insulating layer, a source electrode, a drain electrode, and a sensing portion including an accommodating part and a receiving layer. The first and second gate electrodes are opposed to each other with the sensing portion, the semiconductor layer, and the gate-insulating layer therebetween. One surface of the semiconductor layer is in contact with a surface of the sensing portion, and another surface of the semiconductor layer is in contact with the gate-insulating layer. A surface of the gate-insulating layer is in contact with the second gate electrode. The first gate electrode and the receiving layer are opposed to each other with the accommodating part therebetween. The source and drain electrodes are in contact with the semiconductor layer.
    Type: Application
    Filed: June 8, 2007
    Publication date: December 27, 2007
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Tetsushi YAMAMOTO, Tadahiko HIRAI, Shunji IMANAGA
  • Patent number: 7309898
    Abstract: A method and apparatus for improving the latchup tolerance of circuits embedded in an integrated circuit while avoiding the introduction of noise from such tolerance into the power rails.
    Type: Grant
    Filed: May 20, 2002
    Date of Patent: December 18, 2007
    Assignee: International Business Machines Corporation
    Inventors: Raminderpal Singh, Steven Howard Voldman
  • Publication number: 20070267652
    Abstract: A field-effect transistor includes a channel layer formed of a III-V compound semiconductor excluding aluminum; a gate contact layer formed of a III-V compound semiconductor and provided on the channel layer, the III-V compound semiconductor having a dopant concentration equal to or less than 1×1016 cm?3, containing aluminum, and having a large band gap energy; a gate buried layer of a III-V compound semiconductor and provided on the gate contact layer; and a gate electrode buried in the gate buried layer and in contact with the gate contact layer. A recess in the gate buried layer is opposed to an upper side wall of the gate electrode with a gap therebetween and a part of the gate buried layer, and where a contact with a lower side wall of the gate electrode is established, part of the gate buried layer remains without being removed.
    Type: Application
    Filed: November 8, 2006
    Publication date: November 22, 2007
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hirotaka AMASUGA, Tetsuo KUNII
  • Publication number: 20070252168
    Abstract: An electrostatic discharge protection element and a protection resistor, which are formed on an N-drain region with a field oxide film interposed therebetween for the purpose of preventing electrical breakdown of a field effect transistor, are composed as a stacked bidirectional Zener diode of one or a plurality of N+ polycrystalline silicon regions of a first layer and a P+ polycrystalline silicon region of a second layer, and a stacked resistor of one or a plurality of N+ resistor layers of the first layer and an N+ resistor layer of the second layer, respectively. One end of the plurality of N+ polycrystalline silicon regions of the first layer is connected to an external gate electrode terminal, and the other end is connected to a source electrode. One end of the plurality of N+ resistor layers of the first layer is connected to a gate electrode, and the other end is connected to the external gate electrode terminal.
    Type: Application
    Filed: April 27, 2007
    Publication date: November 1, 2007
    Inventors: Yoshio Shimoida, Masakatsu Hoshi, Tetsuya Hayashi, Hideaki Tanaka, Shigeharu Yamagami
  • Publication number: 20070241365
    Abstract: A finger length a1 of a transistor P11 is longer than a finger length A1 of a transistor P1, and a finger length b1 of a transistor N11 is longer than a finger length B1 of a transistor N1. The finger length b1 of the transistor N11 is shorter than the finger length A1 of the transistor P1, and the relation: a1>A1>b1>B1 is established. In a relation between an I/O section and a logic circuit section, as for MOS transistor of the same conductive type, a finger length of a MOS transistor constituting the logic circuit section is set so as to be longer than a finger length of a MOS transistor constituting the I/O section.
    Type: Application
    Filed: April 10, 2007
    Publication date: October 18, 2007
    Applicant: Renesas Technology Corp.
    Inventor: Toshiaki IWAMATSU
  • Publication number: 20070228411
    Abstract: A display substrate includes a plurality of pixel parts, each including a first and second gate lines, a source line, first, second, and third transistors, and a pumping capacitor. A display device includes a display panel, a gate driving part, a source driving part, and an output selecting part. Each pixel part of a display panel includes a transmissive part, a reflective part, and an adjusting part. The adjusting part adjusts the transmission voltage charged in the reflective part to a reflection voltage based on a control voltage. Thus, transmission voltage applied to the transmissive part is adjusted to reflection voltage to be applied to the reflective part. Therefore, optical reflectivity and optical transmissivity versus voltage are matched with each other, while embodying a single cell-gap and applying a single voltage.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 4, 2007
    Applicant: SAMSUNG ELECTRONICS., LTD.
    Inventors: Gi-Chang Lee, II-Gon Kim, Cheol-Min Kim, Joon-IIa Park
  • Publication number: 20070215899
    Abstract: A merged gate transistor in accordance with an embodiment of the present invention includes a semiconductor element, a supply electrode electrically connected to a top surface of the semiconductor element, drain electrode electrically connected to the top surface of the semiconductor element and spaced laterally away from the supply electrode, a first gate positioned between the supply electrode and the drain electrode and capacitively coupled to the semiconductor element to form a first portion of the transistor and a second gate positioned adjacent to the first gate, and between the supply electrode and the drain electrode to form a second portion of the transistor, wherein the second gate is also capacitively coupled to the semiconductor element.
    Type: Application
    Filed: March 20, 2007
    Publication date: September 20, 2007
    Inventor: Thomas Herman
  • Publication number: 20070210329
    Abstract: A semiconductor wafer to be diced into individual SBDs, HEMTs or MESFETs has a substrate with a main semiconductor region and counter semiconductor region formed on its opposite surfaces. The main semiconductor region is configured to provide the desired semiconductor devices. In order to counterbalance the warping effect of the main semiconductor region on the substrate, as well as to enhance the voltage strength of the devices made from the wafer, the counter semiconductor region is made similar in configuration to the main semiconductor region. The main semiconductor region and counter semiconductor region are arranged in bilateral symmetry as viewed in a cross-sectional plane at right angles with the substrate surfaces.
    Type: Application
    Filed: March 7, 2007
    Publication date: September 13, 2007
    Applicant: Sanken Electric Co., Ltd.
    Inventor: Hirokazu Goto
  • Patent number: 7242036
    Abstract: A semiconductor element includes a first semiconductor layer of a first conductivity type including a non-deposition region and a deposition region. The first semiconductor layer has a first upper surface on the non-deposition region. The semiconductor element also includes a second semiconductor layer of a second conductivity type on the deposition region of the first semiconductor layer. The second semiconductor layer has a second upper surface. The semiconductor element includes first and second electrode layers on the first and second semiconductor layers, respectively, which define an inclined surface for continuous connection therebetween. The semiconductor element includes an insulating layer on the inclined surface, spaced from at least either one of the first and second electrode layers. At least either one of the first and second semiconductor layers includes a recessed portion between the respective one of the first and second electrode layers and the insulating layer.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: July 10, 2007
    Assignee: Mitsubishi Electric Corporation
    Inventor: Nobuhisa Nakashima
  • Patent number: 7227197
    Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as to the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: June 5, 2007
    Assignee: Third Dimension (3D) Semiconductor, Inc.
    Inventor: Xingbi Chen
  • Patent number: 7173290
    Abstract: A semiconductor switch includes a thyristor and a current shunt, preferably a transistor in parallel with and controlled by the thyristor, which shunts thyristor current at turn-off. The thyristor includes a portion of a bottom drift layer, with a p-n junction formed below a gate adjacent to the bottom drift layer to establish a depletion region with a high potential barrier to thyristor current flow at turn-off. The bottom drift layer also provides the transistor base, as well as a current path allowing the transistor base current to be controlled by the thyristor. The switch is voltage-controlled device using an insulated gate for turn-on and turn-off.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: February 6, 2007
    Assignee: Teledyne Licensing, LLC
    Inventor: Hsueh-Rong Chang
  • Patent number: 7144792
    Abstract: Fabrication processes for manufacturing and connecting a semiconductor switching device are disclosed, including an embodiment for dicing a wafer into individual circuit die by sawing the interface between adjacent die with a saw blade that has an angled configuration across its width, preferably in a generally V-shape so that the adjacent die are severed from one another while simultaneously providing a beveled surface on the sides of each separated die. Another embodiment relates to the manner in which damage to a beveled side surface of the individual die can be smoothed by a chemical etching process.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: December 5, 2006
    Assignee: Woodward Governor Company
    Inventors: Theodore S. Wilmot, John C. Driscoll, Eugene N. Bryan
  • Patent number: 7126204
    Abstract: The invention relates to a semiconductor circuit (20) having an electrically programmable switching element (10), an “antifuse”, which includes a substrate electrode (2), produced in a substrate (1) which can be electrically biased with a substrate potential (Vo), and an opposing electrode (5) which is isolated from the substrate electrode (2) by an insulating layer (8), where the substrate electrode (2) includes at least one highly doped substrate region (3), and where the opposing electrode (5) can be connected to an external first electrical potential (V+) which can be provided outside of the semiconductor circuit (20). In line with the invention, the substrate electrode (2) can be connected to a second electrical potential (V?), which is provided inside the circuit and which, together with the external first potential (V+), produces a higher programming voltage (V) than the external first potential (V?) together with the substrate potential (Vo).
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: October 24, 2006
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Frey, Andreas Felber, Jürgen Lindolf
  • Patent number: 6936867
    Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as to the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: August 30, 2005
    Assignee: Third Dimension Semiconductor, Inc.
    Inventor: Xingbi Chen
  • Patent number: 6933541
    Abstract: A family of emitter controlled thyristors employ plurality of control schemes for turning the thyristor an and off. In a first embodiment of the present invention a family of thyristors are disclosed all of which comprise a pair of MOS transistors, the first of which is connected in series with the thyristor and a second which provides a negative feedback to the thyristor gate. A negative voltage applied to the gate of the first MOS transistor causes the thyristor to turn on to conduct high currents. A zero to positive voltage applied to the first MOS gate causes the thyristor to turn off. The negative feedback insures that the thyristor only operates at its breakover boundaries of the latching condition with the NPN transistor portion of the thyristor operating in the active region. Under this condition, the anode voltage VA continues to increase without significant anode current increase.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: August 23, 2005
    Assignee: Virginia Tech Intellectual Properties, Inc.
    Inventor: Alex Q. Huang
  • Patent number: 6900477
    Abstract: A structure and method for a silicon carbide (SiC) gate turn-off (GTO) thyristor device operable to provide an increased turn-off gain comprises a cathode region, a drift region having an upper portion and a lower portion, wherein the drift region overlies the cathode region, a gate region overlying the drift region, an anode region overlying the gate, and at least one ohmic contact positioned on each of the gate region, anode region, and cathode region, wherein the upper portion of the drift region, the gate region, and the anode region have a free carrier lifetime and mobility lower than a comparable SiC GTO thyristor for providing the device with an increased turn-off gain, wherein the free carrier lifetime is approximately 10 nanoseconds. The reduced free carrier lifetime and mobility are affected by altering the growth conditions, such as temperature under which epitaxy occurs.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: May 31, 2005
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Pankaj B. Shah
  • Patent number: 6861706
    Abstract: A compensation semiconductor component has a drift zone formed in a semiconductor body and at least one compensation zone formed in the edge region of the semiconductor body in the drift zone. The compensation zone is doped complementarily to the drift zone and connected by at least one connecting zone to a channel zone, which is doped complementarily to the drift zone and isolates the drift zone from a first terminal zone of the same conductivity type as the drift zone. A control electrode is formed in a manner insulated from the channel zone.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: March 1, 2005
    Assignee: Infineon Technologies AG
    Inventor: Jenoe Tihanyi
  • Publication number: 20040173814
    Abstract: A semiconductor switch includes a thyristor and a current shunt, preferably a transistor in parallel with and controlled by the thyristor, which shunts thyristor current at turn-off. The thyristor includes a portion of a drift layer, with a p-n junction formed below a gate adjacent to the drift layer to establish a depletion region with a high potential barrier to thyristor current flow at turn-off. The drift layer also provides the transistor base, as well as a current path allowing the transistor base current to be controlled by the thyristor. The switch is voltage controlled using an insulated gate.
    Type: Application
    Filed: March 7, 2003
    Publication date: September 9, 2004
    Applicants: Innovative Technology Licensing, LLC, Rockwell Scientific Company
    Inventor: Hsueh-Rong Chang
  • Patent number: 6727529
    Abstract: A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: April 27, 2004
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Farid Nemati, James D. Plummer
  • Patent number: 6727528
    Abstract: A semiconductor device includes a thyristor designed to reduce or eliminate manufacturing and operational difficulties commonly experienced in the formation and operation of NDR devices. According to one example embodiment of the present invention, the semiconductor substrate is trenched adjacent a doped or dopable substrate region, which is formed to include at least two vertically-adjacent thyristor regions of different polarity. A capacitively-coupled control port for the thyristor is coupled to at least one of the thyristor regions. The trench also includes a dielectric material for electrically insulating the vertically-adjacent thyristor regions. The thyristor is electrically connected to other circuitry in the device, such as a transistor, and used to form a device, such as a memory cell.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: April 27, 2004
    Assignee: T-RAM, Inc.
    Inventors: Scott Robins, Andrew Horch, Farid Nemati, Hyun-Jin Cho
  • Patent number: 6713791
    Abstract: A T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array. A method is also presented for fabricating the T-RAM array having the planar cell structure. The method entails simultaneously fabricating a first portion of a T-RAM cell and the n-MOS support device; simultaneously fabricating a second portion of the T-RAM cell and the p-MOS support device; and finishing the fabrication of the T-RAM cell by interconnecting the T-RAM cell with the p-MOS and n-MOS support devices. The first portion of the T-RAM cell is a transfer gate and the second portion of the T-RAM cell is a gated-lateral thyristor storage element. Accordingly, process steps in fabricating the T-RAM cells are shared with process steps in fabricating the n-MOS and p-MOS support devices. The n-MOS and p-MOS support devices refer to sense amplifiers, wordline drivers, column and row decoders, etc.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: March 30, 2004
    Assignee: IBM Corporation
    Inventors: Louis L. Hsu, Rajiv V. Joshi, Fariborz Assaderaghi, Dan Moy, Werner Rausch, James Culp
  • Patent number: 6703642
    Abstract: A SiC gate turn-off (GTO) thyristor that exhibits improved greatly performance includes a p-type anode region, a n-type gated base region positioned beneath the anode region, a n-type drift region positioned beneath the gated base region and doped to a lower concentration of donors than that of the gated base region, a p-type buffer region positioned beneath the n-type drift region and doped with acceptors to a concentration whose magnitude lies between the doping concentration of the anode region and the drift region, and an n-type substrate positioned beneath the buffer region. In another aspect of the invention of this application, a silicon or silicon carbide gate-turn-off thyristor includes a GTO thyristor structure with a thick buffer layer having a high, free-carrier recombination rate.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: March 9, 2004
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Pankaj B. Shah
  • Patent number: 6696705
    Abstract: A power semiconductor component having a mesa edge termination is described. The component has a semiconductor body with first and second surfaces. An inner zone of a first conductivity type is disposed in the semiconductor body. A first zone is disposed in the semiconductor body and is connected to the inner zone. An edge area outside of the first zone has areas etched out. A second zone of a second conductivity type is disposed in the semiconductor body and is connected to the inner zone, and a boundary area between the second zone and the inner zone defines a pn junction. A field stop zone is adjacent the first surface in the edge area. The field stop zone is formed of the first conductivity type and is embedded in the semiconductor body, and the field stop zone is connected to the first zone and to the inner zone.
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: February 24, 2004
    Assignee: Eupec Europaeische Gesellschaft fuer Leistungshalbleiter mbH & Co. KG
    Inventors: Reiner Barthelmess, Gerhard Schmidt
  • Patent number: 6690038
    Abstract: A semiconductor device having a thyristor is arranged in a manner that reduces or eliminates manufacturing difficulties commonly experienced in the formation of such devices, as well as facilitates the implementation of the semiconductor device in a variety of applications. According to an example embodiment of the present invention, a thyristor is formed having some or all of the body of the thyristor extending above a substrate surface of a semiconductor device. The semiconductor device includes at least one transistor having source/drain regions formed in the substrate prior to the formation of the thyristor. One or more layers of material are deposited on the substrate surface and used to form a portion of a body of the thyristor that includes anode and cathode end portions. Each end portion is formed having a base region and an emitter region, and at least one of the end portions includes a portion that is in the substrate and electrically coupled to the transistor.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: February 10, 2004
    Assignee: T-Ram, Inc.
    Inventors: Hyun-Jin Cho, Andrew Horch, Scott Robins, Farid Nemati
  • Patent number: 6683348
    Abstract: A semiconductor device capable of lowering the ON voltage by decreasing the area of the invalid region compared to that of prior art yet maintaining the ability for suppressing the latch-up comparable to that of the conventional IGBTS. The semiconductor device comprises a semiconductor layer of a first conductivity type, a collector layer of a second conductivity type formed on one surface of the semiconductor layer, a base layer of the second conductivity type formed on the other surface of the semiconductor layer, and an emitter layer of the first conductivity type formed in the base layer, wherein the emitter layer having the shape of a ladder being constituted by two crossbeams and cleats formed between the crossbeams, the cleat being provided even between facing end portions of the two crossbeams.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: January 27, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideki Haruguchi, Yoshifumi Tomomatsu
  • Patent number: RE38953
    Abstract: The RBSOA of a device is improved. A gate electrode (10) is linked to a p base layer (4) which is formed in a cell region (CR), and a p semiconductor layer (13) is formed to surround the cell region (CR). An emitter electrode (11) is connected to a top surface of a side diffusion region (SD) of the p semiconductor layer (13) and to a top surface of a margin region (MR) which is adjacent to the side diffusion region (SD), through a contact hole (CH). Further, in these regions, an n+ emitter layer (5) is not formed. Most of avalanche holes (H) which are created in the vicinity of the side diffusion region (SD) when a high voltage is applied pass through the side diffusion region (SD), while some of the avalanche holes (H) pass through the margin region (MR) and are then ejected to the emitter electrode (11). Since there is no n+ emitter layer (5) in these paths, a flow of the holes (H) does not conduct a parasitic bipolar transistor. As a result of this, the RBSOA is improved.
    Type: Grant
    Filed: May 1, 2003
    Date of Patent: January 31, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hideki Takahashi