With Extended Latchup Current Level (e.g., Gate Turn Off "gto" Device) Patents (Class 257/147)
  • Patent number: 6900477
    Abstract: A structure and method for a silicon carbide (SiC) gate turn-off (GTO) thyristor device operable to provide an increased turn-off gain comprises a cathode region, a drift region having an upper portion and a lower portion, wherein the drift region overlies the cathode region, a gate region overlying the drift region, an anode region overlying the gate, and at least one ohmic contact positioned on each of the gate region, anode region, and cathode region, wherein the upper portion of the drift region, the gate region, and the anode region have a free carrier lifetime and mobility lower than a comparable SiC GTO thyristor for providing the device with an increased turn-off gain, wherein the free carrier lifetime is approximately 10 nanoseconds. The reduced free carrier lifetime and mobility are affected by altering the growth conditions, such as temperature under which epitaxy occurs.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: May 31, 2005
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Pankaj B. Shah
  • Patent number: 6861706
    Abstract: A compensation semiconductor component has a drift zone formed in a semiconductor body and at least one compensation zone formed in the edge region of the semiconductor body in the drift zone. The compensation zone is doped complementarily to the drift zone and connected by at least one connecting zone to a channel zone, which is doped complementarily to the drift zone and isolates the drift zone from a first terminal zone of the same conductivity type as the drift zone. A control electrode is formed in a manner insulated from the channel zone.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: March 1, 2005
    Assignee: Infineon Technologies AG
    Inventor: Jenoe Tihanyi
  • Publication number: 20040173814
    Abstract: A semiconductor switch includes a thyristor and a current shunt, preferably a transistor in parallel with and controlled by the thyristor, which shunts thyristor current at turn-off. The thyristor includes a portion of a drift layer, with a p-n junction formed below a gate adjacent to the drift layer to establish a depletion region with a high potential barrier to thyristor current flow at turn-off. The drift layer also provides the transistor base, as well as a current path allowing the transistor base current to be controlled by the thyristor. The switch is voltage controlled using an insulated gate.
    Type: Application
    Filed: March 7, 2003
    Publication date: September 9, 2004
    Applicants: Innovative Technology Licensing, LLC, Rockwell Scientific Company
    Inventor: Hsueh-Rong Chang
  • Patent number: 6727529
    Abstract: A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: April 27, 2004
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Farid Nemati, James D. Plummer
  • Patent number: 6727528
    Abstract: A semiconductor device includes a thyristor designed to reduce or eliminate manufacturing and operational difficulties commonly experienced in the formation and operation of NDR devices. According to one example embodiment of the present invention, the semiconductor substrate is trenched adjacent a doped or dopable substrate region, which is formed to include at least two vertically-adjacent thyristor regions of different polarity. A capacitively-coupled control port for the thyristor is coupled to at least one of the thyristor regions. The trench also includes a dielectric material for electrically insulating the vertically-adjacent thyristor regions. The thyristor is electrically connected to other circuitry in the device, such as a transistor, and used to form a device, such as a memory cell.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: April 27, 2004
    Assignee: T-RAM, Inc.
    Inventors: Scott Robins, Andrew Horch, Farid Nemati, Hyun-Jin Cho
  • Patent number: 6713791
    Abstract: A T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array. A method is also presented for fabricating the T-RAM array having the planar cell structure. The method entails simultaneously fabricating a first portion of a T-RAM cell and the n-MOS support device; simultaneously fabricating a second portion of the T-RAM cell and the p-MOS support device; and finishing the fabrication of the T-RAM cell by interconnecting the T-RAM cell with the p-MOS and n-MOS support devices. The first portion of the T-RAM cell is a transfer gate and the second portion of the T-RAM cell is a gated-lateral thyristor storage element. Accordingly, process steps in fabricating the T-RAM cells are shared with process steps in fabricating the n-MOS and p-MOS support devices. The n-MOS and p-MOS support devices refer to sense amplifiers, wordline drivers, column and row decoders, etc.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: March 30, 2004
    Assignee: IBM Corporation
    Inventors: Louis L. Hsu, Rajiv V. Joshi, Fariborz Assaderaghi, Dan Moy, Werner Rausch, James Culp
  • Patent number: 6703642
    Abstract: A SiC gate turn-off (GTO) thyristor that exhibits improved greatly performance includes a p-type anode region, a n-type gated base region positioned beneath the anode region, a n-type drift region positioned beneath the gated base region and doped to a lower concentration of donors than that of the gated base region, a p-type buffer region positioned beneath the n-type drift region and doped with acceptors to a concentration whose magnitude lies between the doping concentration of the anode region and the drift region, and an n-type substrate positioned beneath the buffer region. In another aspect of the invention of this application, a silicon or silicon carbide gate-turn-off thyristor includes a GTO thyristor structure with a thick buffer layer having a high, free-carrier recombination rate.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: March 9, 2004
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Pankaj B. Shah
  • Patent number: 6696705
    Abstract: A power semiconductor component having a mesa edge termination is described. The component has a semiconductor body with first and second surfaces. An inner zone of a first conductivity type is disposed in the semiconductor body. A first zone is disposed in the semiconductor body and is connected to the inner zone. An edge area outside of the first zone has areas etched out. A second zone of a second conductivity type is disposed in the semiconductor body and is connected to the inner zone, and a boundary area between the second zone and the inner zone defines a pn junction. A field stop zone is adjacent the first surface in the edge area. The field stop zone is formed of the first conductivity type and is embedded in the semiconductor body, and the field stop zone is connected to the first zone and to the inner zone.
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: February 24, 2004
    Assignee: Eupec Europaeische Gesellschaft fuer Leistungshalbleiter mbH & Co. KG
    Inventors: Reiner Barthelmess, Gerhard Schmidt
  • Patent number: 6690038
    Abstract: A semiconductor device having a thyristor is arranged in a manner that reduces or eliminates manufacturing difficulties commonly experienced in the formation of such devices, as well as facilitates the implementation of the semiconductor device in a variety of applications. According to an example embodiment of the present invention, a thyristor is formed having some or all of the body of the thyristor extending above a substrate surface of a semiconductor device. The semiconductor device includes at least one transistor having source/drain regions formed in the substrate prior to the formation of the thyristor. One or more layers of material are deposited on the substrate surface and used to form a portion of a body of the thyristor that includes anode and cathode end portions. Each end portion is formed having a base region and an emitter region, and at least one of the end portions includes a portion that is in the substrate and electrically coupled to the transistor.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: February 10, 2004
    Assignee: T-Ram, Inc.
    Inventors: Hyun-Jin Cho, Andrew Horch, Scott Robins, Farid Nemati
  • Patent number: 6683348
    Abstract: A semiconductor device capable of lowering the ON voltage by decreasing the area of the invalid region compared to that of prior art yet maintaining the ability for suppressing the latch-up comparable to that of the conventional IGBTS. The semiconductor device comprises a semiconductor layer of a first conductivity type, a collector layer of a second conductivity type formed on one surface of the semiconductor layer, a base layer of the second conductivity type formed on the other surface of the semiconductor layer, and an emitter layer of the first conductivity type formed in the base layer, wherein the emitter layer having the shape of a ladder being constituted by two crossbeams and cleats formed between the crossbeams, the cleat being provided even between facing end portions of the two crossbeams.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: January 27, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideki Haruguchi, Yoshifumi Tomomatsu
  • Patent number: 6677622
    Abstract: A semiconductor substrate is of first-conductivity-type and has a principal surface. A first semiconductor region and a second semiconductor region are of second-conductivity-type and formed apart from each other in the principal surface of the semiconductor substrate. A third semiconductor region is of second-conductivity-type and formed on the first semiconductor region. The third semiconductor region has an impurity concentration higher than that of the first semiconductor region. A fourth semiconductor region is of first-conductivity-type and formed on the third semiconductor region. A first main electrode is formed on the fourth semiconductor region. A second main electrode is formed on the second semiconductor region. A gate electrode is formed, at least on the first semiconductor region and on the principal surface of the semiconductor substrate between the fourth semiconductor region and the second semiconductor region, with a gate insulating film therebetween.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: January 13, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumito Suzuki, Hitoshi Takahashi, Haruki Arai, Yoshihiro Yamaguchi
  • Patent number: 6657239
    Abstract: In order to reduce a turn-on time of a power switching semiconductor device at a low cost, a first main electrode divided into a plurality of segments forming segment rows of a multi-concentric circle and a control electrode surrounding the segments are formed on a front major surface of a semiconductor substrate, and a second electrode is formed on a rear major surface thereof, and a turn-on operation is performed between the first main electrode and the second main electrode with a control signal inputted from the control electrode, specifying a relationship between a width of a segment and a distance between adjacent segments, and others.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: December 2, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuhiro Morishita, Katsumi Satoh
  • Patent number: 6635906
    Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p(or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under a high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.
    Type: Grant
    Filed: October 17, 1997
    Date of Patent: October 21, 2003
    Assignee: Third Dimension (3D) Semiconductor
    Inventor: Xingbi Chen
  • Patent number: 6605830
    Abstract: A power semiconductor device including first and second assembly units. The first assembly of units includes a first semiconductor region of a second conductivity type selectively formed in a first main surface of the first semiconductor layer, a second semiconductor region of the first conductivity type selectively formed in a surface of the first semiconductor region, a first gate insulation film formed in contact with at least the surface of the first semiconductor region between the second semiconductor region and the first semiconductor layer, and a first trench-type gate electrode formed on the first gate insulation film and arranged in parallel and extending through the first semiconductor region in a direction of depth thereof.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: August 12, 2003
    Assignee: Mitsubishi Denki Kaisha
    Inventor: Shigeru Kusunoki
  • Patent number: 6583452
    Abstract: A thyristor-based semiconductor device has a thyristor that exhibits increased capacitive coupling between a conductive structure and a portion of a thyristor. According to an example embodiment of the present invention, the thyristor-based semiconductor device is manufactured having an extended portion that is outside a current path through the thyristor and that capacitively couples a conductive structure to a portion of the thyristor for controlling the current through the path. In one particular implementation, the extended portion extends from a base region of the thyristor and is outside of a current path through the base region and between an adjacent base region and an adjacent emitter region. A gate is formed capacitively coupled to the base region via the extended portion. In this manner, the control of the thyristor with the gate exhibits increased capacitive coupling, as compared to the control without the extended portion.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: June 24, 2003
    Assignee: T-RAM, Inc.
    Inventors: Hyun-Jin Cho, Andrew Horch, Scott Robins, Farid Nemati
  • Patent number: 6580101
    Abstract: A semiconductor device having a high breakdown and capable of operating with a large current is realized using GaN-based compound semiconductors which exhibit good electric characteristics. Particularly, a semiconductor material having a larger band gap than semiconductor materials forming other semiconductor layers, for example, AlGaN is used for a semiconductor layer immediately below a gate electrode to realize a power device of vertical structure which comprises GTO or IGBT.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: June 17, 2003
    Assignee: The Furukawa Electric Co., Ltd.
    Inventor: Seikoh Yoshida
  • Patent number: 6570193
    Abstract: The present invention relates to a reverse conducting thyristor device. It aims at preventing heat generated by power loss from filling end field protective rubber and at simplifying a sheath storing a semiconductor substrate. In a reverse conducting thyristor device according to this invention, a self-extinguishing thyristor region is arranged on an inner region of the semiconductor substrate, a reverse conducting diode region whose outer periphery is completely enclosed with an isolation region is arranged on its outer region by at least one, and an external takeout gate electrode region is further arranged on the outermost peripheral region of the semiconductor substrate on the outer part thereof. Thus, a gate electrode provided on a surface of a gate part layer of the self-extinguishing thyristor region is connected with an external takeout gate electrode formed along the outermost periphery of the substrate through a gate wiring pattern formed on a surface of a connecting region.
    Type: Grant
    Filed: July 10, 2000
    Date of Patent: May 27, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinji Koga, Kazuhiro Morishita, Katsumi Satoh
  • Patent number: 6528826
    Abstract: A depletion type MOS semiconductor device is provided which includes a p− well region formed in a surface layer of an n− drift layer, an n+ emitter region formed in a surface layer of the p31 well region, an n− depletion region formed in the surface layer of the p− well region, to extend from the n+ emitter region to a surface layer of the n− drift layer, a gate electrode layer formed on a gate insulating film, over the n− depletion region, an emitter electrode formed in contact with surfaces of both of the n+ emitter region and the p− well region, and a collector electrode formed on a rear surface of the n− drift layer. Also provided is a MOS power IC in which the depletion type MOS semiconductor device is integrated with a vertical MOSFET or IGBT. The MOS power IC has a high breakdown voltage, and includes a circuit for feeding back an increase in the potential of the C terminal to the gate (gm) of the MOSFET or IGBT.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: March 4, 2003
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kazuhiko Yoshida, Motoi Kudoh, Tatsuhiko Fijihira
  • Patent number: 6525374
    Abstract: The invention relates to a semiconductor component with a base zone (3) extending in a lateral direction (x) of a first type of conductivity (n) and at least two contact areas (1, 2) for connection to electric contacts (A, K) which zones are separate at least from the base zone (3) in the lateral direction (x). A base material of the base zone (3) is silicon (Si) and has a dopant concentration of 1012 to 5×1014 cm−3 and a respective dopant concentration (NA) along a lateral direction (x) of less than 2×1012 cm−2 determined by integrating the dopant concentration across the vertical thickness of the base area (3). The semiconductor component further comprises compensation layers (6, 6a, 6b, 6c, 7, 7a, 7b, 7c, 8) of a second type of conductivity (p) opposed to the first type of conductivity. Said layers extend inside or outside the base area in a lateral direction (x).
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: February 25, 2003
    Assignee: Infineon Technologies AG
    Inventors: Roland Sittig, Detlef Nagel
  • Patent number: 6521919
    Abstract: A semiconductor device is composed a semiconductor substrate having a first conducting-type first semiconductor layer, a second conducting-type second semiconductor layer, a first conducting-type third semiconductor layer, a second conducting-type fourth semiconductor layer and a first conducting-type fifth semiconductor layer, a first main electrode for short-circuiting the first semiconductor layer and the second semiconductor layer, a second main electrode for short-circuiting the fourth semiconductor layer and the fifth semiconductor layer, and a control electrode provided on the third semiconductor layer. The first semiconductor layer and the second semiconductor layer form a joint. The second semiconductor layer and the third semiconductor layer form a joint. The third semiconductor layer and the fourth semiconductor layer form a joint. The fourth semiconductor layer and the fifth semiconductor layer form a joint.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: February 18, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Noritoshi Hirano, Katsumi Satoh, Yoshihiro Yamaguchi
  • Patent number: 6501099
    Abstract: A gate turn-off thyristor includes a substrate formed of n-type silicon carbide; a growth buffer formed of n-type silicon carbide and positioned to overlie said substrate; a field buffer region formed of p-type silicon carbide and positioned to overlie said growth buffer; a drift region formed of p-type silicon carbide and positioned to overlie said field buffer region; a gated base region formed of n-type silicon carbide and positioned to overlie said drift region; a modified anode region formed of first, second and third layers of silicon carbide and positioned to overlie said gated base region, said first layer comprising p-type silicon carbide and disposed adjacent said gated base region, said second layer comprising n-type silicon carbide and disposed adjacent said first layer, said third layer comprising p-type silicon carbide and disposed adjacent said second layer; an anode contact disposed on said third layer of said modified anode region; a cathode contact disposed on said substrate; and a gate cont
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: December 31, 2002
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Pankaj B. Shah
  • Patent number: 6469344
    Abstract: A semiconductor device is provided which includes a first p base region and a second p base region formed in one of opposite surface of a high-resistance n base region, a p collector region formed on the other surface of the n base region, an n emitter region formed in a surface layer of the first p base region, and a groove formed in the n base region between the first and second p base regions, to provide a trench gate electrode portion. The first and second p base regions are formed alternately in the Z-axis direction with certain spacing therebetween. The second p base region is held in a floating state in terms of the potential, thus assuring a reduced ON-resistance, and a large quantity of carriers present in the vicinity of the surface of the second p base region are quickly drawn away through a p channel upon turn-off, so that the turn-off time is reduced.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: October 22, 2002
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Noriyuki Iwamuro, Yuichi Harada
  • Publication number: 20020130332
    Abstract: A layout method is provided for a latch-up prevention circuit of a semiconductor memory device which includes the steps of: arranging a cell array at substantially the middle of the device; placing peripheral circuits next to both sides of the cell array; placing a plurality of pads on both sides of the cell array between the peripheral circuits and both edges of the device; and arranging guard rings beneath the plurality of pads. The layout method further includes a plurality of ESD protection transistors disposed axially along the direction as the plurality of pads between the plurality of pads and an edge of the device. And each of guard ring is a NWELL guard ring, and connected to a supply voltage and ground.
    Type: Application
    Filed: August 28, 2001
    Publication date: September 19, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Beak-Hyung Cho, Choong-Keun Kwak
  • Patent number: 6448586
    Abstract: A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other type of NDR-based SRAMs.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: September 10, 2002
    Assignee: The Board of Trustees of the Leland Standford Junior University
    Inventors: Farid Nemati, James D. Plummer
  • Patent number: 6445013
    Abstract: A first cathode flange (14) provided with branch-like protrusions (14d) extending towards substantially its outer periphery and a gate flange (15) provided with branch-like protrusions (15c) extending towards substantially its outer periphery are connected to a cathode electrode (7a) and a gate electrode (7b), respectively, formed on one surface of a gate drive substrate (7). With this structure, a gate commutated turn-off semiconductor device which eliminates the necessity of a gate spacer and a cathode spacer and allows reduction in time and cost required for manufacture can be achieved.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: September 3, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazunori Taguchi
  • Patent number: 6441408
    Abstract: A power semiconductor components has stop zones. In order to optimize the static and dynamic losses of the power semiconductor components, the stop zone is provided with donors which have at least one donor level which lies within the band gap of silicon and is at least 200 meV away from the conduction band edge of silicon.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: August 27, 2002
    Assignee: Infineon Technologies AG
    Inventors: Alfred Porst, Helmut Strack, Anton Mauder, Hans-Joachim Schulze, Heinrich Brunner, Josef Bauer, Reiner Barthelmess
  • Publication number: 20020096691
    Abstract: A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type source diffusion region, which connects to the source electrode, defines the other end of the gate region.
    Type: Application
    Filed: January 24, 2001
    Publication date: July 25, 2002
    Inventor: Donald Ray Disney
  • Patent number: 6423986
    Abstract: Power semiconductor devices have a plurality of semiconductor layers of alternating p-type and n-type conductivity and top and bottom device surfaces. The top semiconductor layer forms a control layer (60). A semiconductor layer junction, remote from both device surfaces, forms a blocking p-n junction (54) capable of sustaining the applied device voltage. A top ohmic contact overlays a top conductive region (64) extending from the top surface into the control layer (60). A conductive tub region (62), spaced apart from the top conductive region (64), extends from the top surface at least through the control layer (60). A field effect region (80) is disposed in the control layer (60) between the top conductive region (64) and tub region (62). A gate contact (18) is formed over the field effect region (80) causing the creation and interruption of a conductive channel (82) between the top conductive region (64) and conductive tub region (62) so as to turn the device on and off.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: July 23, 2002
    Assignee: Rutgers, The State University
    Inventor: Jian J. Zhao
  • Patent number: 6384431
    Abstract: Insulated gate bipolar transistors which can restrain causing surge voltage due to an inductance component while an L-load is turned off and can improve a negative characteristic of a sustain voltage during breakdown. An insulated gate bipolar transistor (IGBT) is provided with: a p+-type semiconductor substrate; an n+-type buffer layer having high impurity concentration; an n-type intermediate layer; and an n−-type base layer having low impurity concentration. A p-type well layer and an n+-type emitter layer having high impurity concentration are formed in the n−-type base layer. The n-type intermediate layer has an intermediate impurity concentration between an impurity concentration of the n+-type buffer layer and that of the n−-type base layer. Thickness of the intermediate layer is determined so that the depletion layer does not reach the n+-type buffer layer even when the switching operation of the L-load is turned off.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: May 7, 2002
    Assignee: Denso Corporation
    Inventors: Shigeki Takahashi, Takanori Teshima, Naohiko Hirano, Norihito Tokura
  • Publication number: 20020033487
    Abstract: A semiconductor device is composed a semiconductor substrate having a first conducting-type first semiconductor layer, a second conducting-type second semiconductor layer, a first conducting-type third semiconductor layer, a second conducting-type fourth semiconductor layer and a first conducting-type fifth semiconductor layer, a first main electrode for short-circuiting the first semiconductor layer and the second semiconductor layer, a second main electrode for short-circuiting the fourth semiconductor layer and the fifth semiconductor layer, and a control electrode provided on the third semiconductor layer. The first semiconductor layer and the second semiconductor layer form a joint. The second semiconductor layer and the third semiconductor layer form a joint. The third semiconductor layer and the fourth semiconductor layer form a joint. The fourth semiconductor layer and the fifth semiconductor layer form a joint.
    Type: Application
    Filed: March 22, 2001
    Publication date: March 21, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Noritoshi Hirano, Katsumi Satoh, Yoshihiro Yamaguchi
  • Patent number: 6359306
    Abstract: In a method of manufacturing a trench-MOS gate structure device, trenches for contact and n-type source layers are alternately formed in a region situated between parallel trench-MOS gates. Thereby, scale down of the device is possible without requiring mask alignment.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: March 19, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideaki Ninomiya
  • Patent number: 6355948
    Abstract: There is provided a semiconductor integrated circuit device having a macro cell structure including: a rectangular macro cell region formed on a semiconductor substrate; a first diffusion region having the minimum permissible width, formed apart at least by a minimum inter-diffusion distance from both left and right side ends in upper and lower sides of the macro cell region, and formed in the vicinity of both upper and lower ends of the macro cell region; and a second diffusion region in which a well contact is formed. The first diffusion region is electrically connected with the second diffusion region.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: March 12, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takenobu Iwao, Ryuichi Sakano
  • Patent number: 6339231
    Abstract: A gate terminal plate (1) of a GCT thyristor (90), a connecting substrate (70) of a driving device and a cathode electrode plate (10) are interposed between a set of metal rings (7A) and (7C) fastened to each other with a screw (8). The cathode electrode plate (10) is connected to a cathode post electrode (31) of the GCT thyristor (90). The screw (8) is electrically insulated from the metal ring (7A) and the gate terminal plate (1) through an insulator (9). By this structure, the gate terminal plate (1) and the cathode electrode plate (10) are directly connected to a first metallized layer (5) and a second metallized layer (6) which are provided on two main surfaces of the connecting substrate (70) of the driving device, respectively. Thus, resistance and inductance components in a path for a gate current are reduced and an assembly is simplified.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: January 15, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kenji Ohta
  • Patent number: 6323547
    Abstract: In a GCT device which controls large current at the operating frequency of 1 kHz or more, a ring-shaped gate terminal (10) is made of a magnetic material with the maximum permeability of 15,000 or less in the CGS Gaussian system of units. Further, in the outer end portion of an outer plane portion (10O) of the ring-shaped gate terminal (10), a plurality of slits extending diametrically are provided along the circumference to be coupled to mounting holes (10b).
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: November 27, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshinobu Kawamura, Katsumi Satoh, Mikio Bessho
  • Patent number: 6271545
    Abstract: Both the blocking voltage as well as the sweep voltage of conventional thyristors exhibit a pronounced temperature behavior, whereby the corresponding voltage values can change by up to 15% within the relevant temperature range (5° C.-120° C.). In the proposed thyristor, the overhead triggering is compelled by the “punch through” effect that is independent of the temperature (expanse of the space charge zone allocated to the p-base/n-base junction 10) up to the neighboring n-base/p-emitter junction 11). Due to the laterally non-uniform distribution of the dopant in the n+ stop zone (7′) of the anode-side base (7), further, it is assured that the central thyristor region always ignites first. Sweep or punch through voltage is not dependent on the temperature in the asymmetrical thyristors.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: August 7, 2001
    Assignee: Siemens Aktiengesellschaft
    Inventor: Hans-Joachim Schulze
  • Patent number: 6252259
    Abstract: A semiconductor layer, through which a main current flows, is so structured that a carrier life time in the semiconductor layer is uniform in accordance with a predetermined distribution of the carrier life time. Thus, turn OFF characteristics of a semiconductor switching device can be improved without causing any unacceptable disadvantages for other characteristics.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: June 26, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tadaharu Minato
  • Patent number: 6236069
    Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: May 22, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Shinohe, Kazuya Nakayama, Minami Takeuchi, Masakazu Yamaguchi, Mitsuhiko Kitagawa, Ichiro Omura, Akio Nakagawa
  • Patent number: 6229161
    Abstract: A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: May 8, 2001
    Assignee: Stanford University
    Inventors: Farid Nemati, James D. Plummer
  • Patent number: 6163200
    Abstract: In a gate driver device, cathode conductor 2, gate conductor 3, and positive and negative conductors 8 and 9 between the principal turn-on and turn-off capacitors and MOSFET switching elements Q11-Q1i and Q21-Q2j are disposed on a wide plate. A thin insulation layer is inserted between conductor 3 and conductors 8 and 9. Numerous chip-type ceramic capacitors C11-C1m and C21-C2n to be used as principal capacitors are arranged in rows in the space between conductor 2 and conductors 8 and 9. The gate voltage of switching elements Q11-Q1i is reduced exponentially by time constant circuit TC, and the leak inductance of transformer Thf is employed to smooth the charging current.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: December 19, 2000
    Assignee: Elmec Inc.
    Inventor: Katsuhiko Iijima
  • Patent number: 6150671
    Abstract: A transistor of SiC having a drain and a highly doped substrate layer is formed on the drain. A highly n type buffer layer may optionally be formed on the substrate layer. A low doped n-type drift layer, a p-type base layer, a high doped n-type source region layer and a source are formed on the substrate layer. An insulating layer with a gate electrode is arranged on top of the base layer and extends substantially laterally from at least the source region layer to a n-type layer. When a voltage is applied to the gate electrode, a conducting inversion channel is formed extending substantially laterally in the base layer at an interface of the p-type base layer and the insulating layer. The p-type base layer is low doped in a region next to the interface to the insulating layer at which the inversion channel is formed and highly doped in a region thereunder next to the drift layer.
    Type: Grant
    Filed: April 24, 1996
    Date of Patent: November 21, 2000
    Assignee: ABB Research Ltd.
    Inventors: Christopher Harris, Ulf Gustafsson, Mietek Bakowski
  • Patent number: 6118150
    Abstract: The RBSOA of a device is improved. A gate electrode (10) is linked to a p base layer (4) which is formed in a cell region (CR), and a p semiconductor layer (13) is formed to surround the cell region (CR). An emitter electrode (11) is connected to a top surface of a side diffusion region (SD) of the p semiconductor layer (13) and to a top surface of a margin region (MR) which is adjacent to the side diffusion region (SD), through a contact hole (CH). Further, in these regions, an n.sup.+ emitter layer (5) is not formed. Most of avalanche holes (H) which are created in the vicinity of the side diffusion region (SD) when a high voltage is applied pass through the side diffusion region (SD), while some of the avalanche holes (H) pass through the margin region (MR) and are then ejected to the emitter electrode (11). Since there is no n.sup.+ emitter layer (5) in these paths, a flow of the holes (H) does not conduct a parasitic bipolar transistor. As a result of this, the RBSOA is improved.
    Type: Grant
    Filed: September 23, 1996
    Date of Patent: September 12, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hideki Takahashi
  • Patent number: 6107649
    Abstract: Power semiconductor devices have a plurality of semiconductor layers of alternating p-type and n-type conductivity and top and bottom device surfaces. A layer of the top surface forms a control layer. A semiconductor layer junction, remote from top and bottom device surfaces, forms a blocking p-n junction capable of sustaining the applied device voltage. A top ohmic contact overlays a top conductive region extending from the top surface into the control layer. A conductive tub region, spaced apart from the top conductive region, extends from the top surface at least through the control layer. A field effect region is disposed in the control layer between the top conductive region and tub region. A gate contact is formed over the field effect region causing the creation and interruption of a conductive channel between the top conductive region and the conductive tub region so as to turn the device on and off.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: August 22, 2000
    Assignee: Rutgers, The State University
    Inventor: Jian H. Zhao
  • Patent number: 6107651
    Abstract: In a gate turn-off thyristor (GTO) with homogeneous anode, emitter and stop layer, a device which short-circuit the stop layer with the anode is provided in an edge termination region. As a result, in a reverse-biased state, the GTO has a structure of a diode in the edge region and amplification of a reverse current is obviated. With this structure, thermal loading in the edge region is reduced, as the GTO tolerates a higher operating temperature at a predetermined voltage.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: August 22, 2000
    Assignee: Asea Brown Boveri AG
    Inventors: Stefan Linder, Andre Weber
  • Patent number: 6091069
    Abstract: An infrared optical system incorporates a lens for imaging a remote scene onto a detector within a cold shield. Stray radiation incident on the detector is reduced by an optical stop in the form of a light emitting diode producing negative luminescence. The LED emits less radiation than background, and contributes less to the detector photon noise than an optical stop not exhibiting negative luminescence.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: July 18, 2000
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: Timothy Ashley, Charles Thomas Elliott, Neil Thomson Gordon, Ralph Stephen Hall
  • Patent number: 6091087
    Abstract: An insulated gate thyristor includes a first-conductivity-type base layer having a high resistivity, first and second second-conductivity-type base regions formed in a surface layer of the first-conductivity-type base layer, a first-conductivity-type source region formed in a surface layer of the first second-conductivity-type base region, and a first-conductivity-type emitter region formed in a surface layer of the second second-conductivity-type base region.
    Type: Grant
    Filed: May 6, 1997
    Date of Patent: July 18, 2000
    Assignee: Fuji Electric Co., Ltd
    Inventors: Noriyuki Iwamuro, Yuichi Harada, Tadayoshi Iwaana
  • Patent number: 6091086
    Abstract: A method of forming a power integrated circuit device (100) including a semiconductor layer of first conductivity type. The semiconductor layer includes a front-side surface (103), a backside surface (116), and a scribe region (117). The semiconductor layer further including a plurality of active cells on the front-side surface (103). The present method includes forming a backside layer (116) of second conductivity type overlying the backside surface, and forming a continuous diffusion region (117) of the second conductivity type through the semiconductor layer to connect the scribe region to the backside layer (116).
    Type: Grant
    Filed: June 6, 1997
    Date of Patent: July 18, 2000
    Assignee: IXYS Corporation
    Inventor: Nathan Zommer
  • Patent number: 6072214
    Abstract: An IGBT includes two trenches extending from an emitter terminal toward a first side of a substrate of a first conductivity material. A collector layer of a second conductivity material is disposed on a second side of the substrate. The trenches each have a gate and a insulator within them. On the outside of the trenches, bulk regions of a second conductivity type are disposed on the first side of the substrate. On top of the bulk regions are bulk connection regions of a second conductivity type and source regions of a first conductivity type. The emitter couples the bulk and source regions. A material of either conductivity type, an insulator, or two MOSFETS are placed between the trenches. With multiple IGBTs, the trenches can be arranged in striped, island-like, or lattice format.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: June 6, 2000
    Assignee: Semikron Elektronik GmbH
    Inventors: Reinhard Herzer, Mario Netzel
  • Patent number: 6072199
    Abstract: A insulated gate bipolar transistor comprising a semiconductor substrate layer having an impurity concentration of not less than 4.0.times.10.sup.13 /cm.sup.3, and being substantially free of lifetime killers.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: June 6, 2000
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Noriyuki Iwamuro
  • Patent number: 6020603
    Abstract: A high voltage semiconductor device such as a gate turn-off thyristor, reduces surface field concentration of a main P-N junction part and attains withstand voltage increase.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: February 1, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Futoshi Tokunoh, Yasuo Tanaka, Tokumitsu Sakamoto, Nobuhisa Nakasima
  • Patent number: 5981984
    Abstract: An insulated gate thyristor includes a first-conductivity-type base layer having a high resistivity, first and second second-conductivity-type base regions formed in a surface layer of the first-conductivity-type base layer, a first-conductivity-type source region formed in a surface layer of the first second-conductivity-type base region, and a first-conductivity-type emitter region formed in a surface layer of the second second-conductivity-type base region.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: November 9, 1999
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tadayoshi Iwaana, Yuichi Harada, Noriyuki Iwamuro