Abstract: A P.sup.+ layer is formed on the lower surface of an N.sup.- substrate, and recesses are defined in the upper surface of the N.sup.- substrate. Then, P.sup.+ gate regions and bottom gate regions are formed in side walls and bottoms of the recesses. The N.sup.- substrate and an N.sup.- substrate are ultrasonically cleaned to remove impurities therefrom, then cleaned by pure water, and dried by a spinner. Then, while lands on the upper surface of the N.sup.- substrate are being held against the surface of the N.sup.- substrate, the N.sup.- substrate are joined to each other by heating then at 800.degree. C. in a hydrogen atmosphere.

Abstract: A double gate type insulated gate thyristor is provided which improves the breakdown withstand capability by turning on at low on-voltage by a thyristor operation mode and by turning off at high speed by an IGBT operation mode. In the insulated gate thyristor, a part of an n.sup.+ source region is removed and a p-base region is directly connected with a part of a cathode so as to connect a bipolar transistor with a main thyristor in parallel. A part of a switching-off current flows through the bipolar transistor to the cathode and the switching-off current which flows through a lateral MOSFET to the second gate electrode is reduced. By this configuration, the breakdown withstand capability is improved.

Abstract: The maximum controllable current of an insulated gate thyristors is improved by optimizing the length and sheet resistance of the poly-silicon constituting the gate electrodes. The device has an n.sup.- base layer with high resistivity, on the first surface of which is selectively formed a p type base region. The first source region, the second source region, and an n.sup.+ emitter region are selectively formed in the surface layer of the p type base region. The first gate electrode is formed above the exposed area of the n.sup.- base layer, and the portion of the p type base region extending between the n.sup.- base layer and the first source region. The second gate electrode is formed above the second source region, and the portion of the p type base region extending between the second source region and the emitter region. The length of the poly-silicon constituting the gate electrodes is set at 4 mm or less or the sheet resistance of the poly-silicon is set at 70 .OMEGA./.quadrature. or less.

Abstract: An insulated gate type semiconductor device has a gate electrode which controls current flow between two regions of the same conductivity type in a semiconductor substrate. A main electrode has a first portion contacting a first one of the two regions, a second portion extending above the gate electrode and a third portion providing a raised external contact surface to contact an external electrode. The gate electrode is insulated above and below by insulating films. To prevent damage to the gate electrode and the lower insulating films due to the pressure of the external electrode, there is a supporting insulating layer on the surface of the substrate underlying the contact portion of the main electrode and having a thickness substantially greater than the thickness of the insulating film below the gate electrode and the contact surface is more remote from the substrate than the second portion of said main electrode.

Abstract: In an MOS-controlled power semiconductor component having a multiplicity of cathode cells, the surface area proportion of the cathode cells relative to the total component surface area is selected at between 0.1% and 10% in the case of circular cell geometry and between 0.4% and 40% in the case of strip-shaped cell geometry. As a result of this, the susceptibility to oscillation caused by small inductances can be reduced. (FIG.

Abstract: A semiconductor device, by which a base in which gates are buried can be formed by the junction of semiconductor substrates to each other at a lower temperature, and a fabrication process thereof are provided. Recesses are defined in the top of an N.sup.- substrate. A P.sup.+ layer is formed on the underside of the N.sup.- substrate. P.sup.+ -Gate regions are each formed in an area ranging from the bottom to lower side portions of the recesses. A metal layer composed of an Au-Sb alloy is formed on the underside of the N.sup.+ substrate. The N.sup.- substrate and the N.sup.+ substrate are subjected to a treatment for removing impurities thereon with an aqueous solution of sulfuric acid and hydrogen peroxide, washed with purified water and dried by a spin dryer. The N.sup.- substrate and the N.sup.+ substrate are heated at about 350.degree. C.

Abstract: To provide thermal relief, particularly of the edge of disk-shaped gate-turn-off GTO thyristors (GTO) as are used in converters in power electronics, at least one cooling segment which is isolated from a GTO cathode metallization of the GTO thyristor segment (GTO) by a gate electrode metallization of a gate electrode is arranged on the edge and laterally adjacent to the GTO thyristor segment (GTO). An insulation layer is provided between a cooling segment metallization and the gate electrode metallization. Cooling segments in an lo outer annular zone can be alternately arranged with GTO thyristor segments (GTO) or offset towards the outside in the radial direction or perpendicular direction thereto. Instead of cooling segments, a p.sup.+ -type GTO emitter layer of the GTO thyristor segments (GTO) can be shortened at the edge in the outer annular zone.

Abstract: High withstand voltage, low on-voltage, low turn-off loss, and high switching speed are realized in semiconductor bidirectional switches in which the potential of the substrate is floating. A switch has a p-type substrate without an electrode, and an n-layer on the substrate. At least one pair of p-well regions and at least one p-region are formed in a surface layer of the n-layer. An n.sup.+ region is formed in the p-well region, and a gate electrode is fixed via an insulation film to the p-well region. A main electrode is fixed to a part of the surface of the n.sup.+ region and the surface of a p.sup.+ contact region in the p-well region.

Abstract: A heavily doped n-type semiconductor region is selectively formed at a surface where a p-type semiconductor layer and an n-type semiconductor layer abut each other. Injection of holes from the p-type semiconductor layer to the n-type semiconductor layer is attained by holes which selectively flow in a region where the heavily doped n-type semiconductor region is not present. The high concentration of the holes at such a region exerts a predominant influence in the device when a collector current is small, whereby flow of the collector current is facilitated and the ON-resistance of the device is suppressed. On the other hand, when the collector current is large, under a dominantly strong influence of a fact that flow of the collector current is allowed only through the region where the heavily doped n-type semiconductor region is not provided, the flow of the collector current is suppressed, and hence, the durability against destruction of the device is enhanced.

Abstract: A field-effect semiconductor device for reducing on-state source-drain voltage and increasing breakdown voltage, has a one conductivity type semiconductor region, a source region of one conductivity type, a drain region, and gate regions of other conductivity type. The source region, the drain region and the gate regions are formed in the semiconductor region and contiguous to a surface of the semiconductor region. The gate regions are located so as to sandwich a portion of the semiconductor region coupling the source region and the drain region.

Abstract: A process for manufacturing a semiconductor switching device (such as a thyristor device) comprises: etching a face of a semiconductor body to provide islands and channels which define a mesa-contoured surface; diffusing dopant of a first conductivity type through said surface so that the lines of equal concentration of the dopant in said body follow substantially the mesa-contoured surface; and diffusing dopant of a second conductivity type into said islands to form p-n junctions with said dopant of a first conductivity type. The diffusion of said dopant of a first conductivity type is followed by an out-diffusion step so that the dopant concentration of said dopant of a first conductivity type is at a maximum at a depth below said surface.

Abstract: The SiC thyristor has a substrate, an anode, a drift region, a gate, and a cathode. The substrate, the anode, the drift region, the gate, and the cathode are each preferably formed of silicon carbide. The substrate is formed of silicon carbide having one conductivity type and the anode or the cathode, depending on the embodiment, is formed adjacent the substrate and has the same conductivity type as the substrate. A drift region of silicon carbide is formed adjacent the anode or cathode and has an opposite conductivity type as the anode or cathode. A gate is formed adjacent the drift region or the cathode, also depending on the embodiment, and has an opposite conductivity type as the drift region or the cathode. An anode or cathode, again depending on the embodiment, is formed adjacent the gate or drift region and has an opposite conductivity type than the gate.

Abstract: A bidirectional semiconductor switching device includes a semiconductor substrate having first and second device terminals on opposite faces thereof, a thyristor in the substrate for providing regenerative conduction in a first direction, between the first device terminal and the second device terminal, and an insulated-gate bipolar junction transistor (IGBT) in the substrate for providing nonregenerative conduction in a second opposite direction, between the second device terminal and the first device terminal. In particular, the switching device includes first and second adjacent trenches therein at a face and respective first and second insulated-gate field effect transistors (IGFETs) in the trenches for providing gate-controlled turn-on and turn-off of the thyristor and the IGBT, by being electrically connected in series therewith.

Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

Abstract: In a gate insulated static induction thyristor with a split gate type shorted cathode structure, a first gate region of the split gate structure is used as a cathode short-circuit gate and the cathode region is formed between the first and second gate regions. A MOS structure is formed on the second gate region as a insulated gate control gate region electrode isolated therefrom. The MOS gate structure suppresses the minority carrier (hole) storage effect to permit high-speed switching of the thyristor, and the shorted cathode structure provides for increased maximum controllable current/voltage durability. The split gate structure can be used in combination with planar, buried, recessed and double gate structures.

Abstract: A semiconductor device thyristor structure includes a first conductive type collector region, second conductive type and first conductive type base regions, and a second conductive type emitter region. First conductive type regions and second conductive type regions have respective first and second type majority carriers. A first MOSFET injects the second type majority carriers into the second conductive type base region. A second MOSFET is opened and closed independent of the first MOSFET and extracts the first type majority carriers from the first conductive type base region. A third MOSFET has a first gate electrode which is also a gate electrode of the first MOSFET, for extracting the first type majority carriers from the first conductive type base region. First conductive type and second conductive type emitter regions are formed within the first conductive type base region and an emitter voltage can be simultaneously applied to these emitter regions.

Abstract: An n-buffer layer and an n.sup.- -base layer are formed on a p.sup.+ -anode layer. A p-base layer is formed on the n.sup.- -base layer. The p-base layer has a p-type impurity layer protruding into n.sup.- -base layer. An n-cathode layer, an n.sup.+ -cathode layer and a P+-impurity layer are formed on p-base layer. First trenches are formed through p.sup.+ -impurity later, n-cathode layer and p-base layer. On-gates are formed in the first trenches. Second trenches are formed through p.sup.+ -impurity layer and n-cathode layer with their bottom surfaces located in p-type impurity layer. Off-gates are formed in the second trenches. First and second trenches are preferably formed alternately. Thereby, a voltage-driven thyristor has improved turn-on and turn-off characteristics and a high reliability.

Abstract: A thyristor includes a semiconductor body with a surface. The semiconductor body has an inner zone of a first conduction type; a cathode-side base zone of a second conduction type opposite the first type, the base zone having a recess formed therein; a layer of the second conduction type being disposed on the surface of the semiconductor body, being disposed in the cathode-side base zone, being thinner than the cathode-side base zone, and being joined to the cathode-side base zone; and an additional zone of the second conduction type being disposed in the recess, being joined to the layer, being thicker than the layer, and being spaced apart from the cathode-side base zone.

Abstract: A MOS semiconductor device which exhibits high switching operations including high turn-on and an excellent self-cooling capability. The device prevents damage to insulation films and electrodes thereof. An IGT includes a multi-layer structure having a p type emitter layer, an n type base layer, a p type base layer and an n type emitter layer superimposed therein. A gate electrode and an overlying gate oxide film are disposed on a recessed surface of the multi-layer structure. A cathode electrode is located only in and around a cathode surface so that most of the top surface of the gate electrode is uncovered. Via an intervening cathode distortion snubbering plate, the cathode electrode is in pressure contact with a cathode electrode body. The gate and the cathode electrodes have a reduced capacitance therebetween. The cathode electrode body serves to cool the cathode electrode. The gate electrode and the gate oxide film are protected from stress, and hence, will not be damaged by stress.

Abstract: A reverse conducting gate turn-off thyristor (RC-GTO) includes, in the same semiconductor body, a gate turn-off thyristor, a reverse current diode, and a semiconductor isolation region between the gate turn-off thyristor and the reverse current diode and having a first conductivity type semiconductor layer adjacent an anode electrode and spaced apart second conductivity type high-dopant-impurity-concentration regions opposite the anode electrode.

Abstract: The semiconductor substrate of a GTO-Thyristor is structured at a cathode-side such that the cathode electrode lies in a first uppermost level of and in a second level lying there below. A gate contact lies in a third lowest level. Passivation layers extend only over the second and third levels. The cathode electrode also contacts the cathode emitter zone in the second level. It is overlapped there by the passivation layers.

Abstract: A gate electrode includes a first region formed in an OFF gate region and a second region formed in an ON gate region. A P-channel region is formed in the OFF gate region and an N-channel region is formed in the ON gate region to separate these gate regions. Since a P.sup.- -type channel region of low impurity concentration is formed at an end of a P-type base region in which the N-channel region is formed, the impurity concentration of the P-type base region can be increased and thus turn-off characteristic is improved.

Abstract: In a turn off type semiconductor device, an n-type emitter layer is divided into a plurality of elements by trenches. A silicide layer of a high melting point metal is provided on a p-type layer adjacent to the individual elements of the n-type emitter layer on a bottom of each of the trenches. A gate electrode is provided on the associated silicide layer so as to surround the plurality of elements of the n-type emitter layer obtained by the division of the emitter layer. An insulator is filled in each of the trenches dividing the n-type emitter layer surrounded by the gate electrode. A cathode electrode is provided on both the insulators and the n-type emitter layer.

Abstract: A GTO thyristor includes a p-type emitter layer, an n-type base layer, a p-type base layer and an n-type emitter layer. An additional n-type layer is formed on the p-type base layer next to the n-type emitter layer An additional p.sup.+ -type layer is formed on the additional n-type layer and stretches to the n-type emitter layer. An anode electrode and a cathode electrode are disposed respectively on the n-type emitter layer and the p-type base layer. The n-type emitter layer and the additional p.sup.+ -type layer are connected with each other by a floating electrode. A first gate electrode is disposed on the additional p.sup.+ -type layer, additional n-type layer and p-type base layer with an insulating film interposed therebetween so as to form a first FET. A second gate electrode is disposed on the n-type base layer, p-type base layer and n-type emitter layer with an insulating film interposed therebetween so as to form a second FET.

Abstract: An insulated gate control thyristor including an n-type base region, an insulating layer, gates formed on the insulating layer, first and second windows formed in the insulating layer, p-type emitter layers and n-type cathode layers diffused into the base region from the first windows, and p-type collector layers diffused into the base region from the second windows. The emitter layer and the collector layer are disposed in close proximity to each other under the gate so that a channel is formed which is conducted when the thyristor is turned off. The turn-off of the thyristor speeds up and becomes reliable, and the quality control of the process steps for fabricating the thyristor becomes easier.

Abstract: A lateral MOS-controlled thyristor (MCT) structure using a single MOS gate for both turn-on and turn-off. By eliminating a parasitic lateral PNP transistor, through the addition of a high resistivity region surrounding one output terminal, and adding a DMOS transistor to a conventional thyristor structure, the maximum turn-off current limit is increased with lower forward voltage drop than that available in prior art lateral MCTs.

Abstract: A composite thyristor comprising a plurality of parallel connected identical thyristor cells, each of the cells including a turn-on field effect transistor (FET) and a turn-off FET. The gate electrodes of all the FETs form a grid-like pattern on a surface of the semiconductor substrate of the device. The pattern includes strips which intersect at corners. Turn-off FETs are formed along the boundary of the grid and beneath it, and turn-on FETs are disposed beneath the corners.

Abstract: A seat frame for reclining type seat which includes a toggle actuated release mechanism for the back support pivot joint. The release mechanism includes a toggle arm connected to peripheral lock members which mesh with rotatable gears connected to the back support. A manually operable lever arm is connected to the toggle arm knee joint to selectively shift the toggle arm between a normally locked position and an unlocked position wherein the back support may be shifted.