With Particular Barrier Dimension Patents (Class 257/17)
  • Patent number: 7294518
    Abstract: The present invention provides a photoresist stripper including about 5 wt % to about 20 wt % alcohol amine, about 40 wt % to about 70 wt % glycol ether, about 20 wt % to about 40 wt % N-methyl pyrrolidone, and about 0.2 wt % to about 6 wt % chelating agent.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: November 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Sick Park, Jong-Hyun Jeong, Suk-Il Yoon, Seong-Bae Kim, Wy-Yong Kim, Soon-Beom Huh, Byung-Uk Kim
  • Patent number: 7282420
    Abstract: A method of manufacturing a flash memory device wherein a stacked structure of an oxide and nitride or the reverse is applied to insulation spacers provided on sidewalls of gates for forming source/drain regions. After completing the source/drain regions, spacers are formed on sidewalls of the gates by using an oxide film as a contacting buffer, thus minimizing the interference between gates and reducing the stress to cells, overcoming the disturbance of threshold voltage.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: October 16, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyoung Sik Han, Sang Wook Park, Sang Deok Kim
  • Patent number: 7282732
    Abstract: Symmetric quantum dots are embedded in quantum wells. The symmetry is achieved by using slightly off-axis substrates and/or overpressure during the quantum dot growth. The quantum dot structure can be used in a variety of applications, including semiconductor lasers.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: October 16, 2007
    Assignees: STC. unm, Innolume Acquisition, Inc.
    Inventors: Allen L Gray, Andreas Stintz, Kevin J Malloy, Luke F Lester, Petros M Varangis
  • Patent number: 7279699
    Abstract: An integrated circuit may include at least one active optical device and a waveguide coupled thereto. The waveguide may include a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: October 9, 2007
    Assignee: RJ Mears, LLC
    Inventors: Robert J. Mears, Robert John Stephenson
  • Publication number: 20070215858
    Abstract: A photo detector is provided with a plurality of quantum dot layers and first conductive type contact layers provided at both sides of the plurality of quantum dot layers so as to sandwich them; a second conductive type impurity is doped in a first semiconductor layer formed between one first conductive type contact layer and a first quantum dot layer which is closest to the one first conductive type contact layer so that it results in a barrier against a carrier positioned at the one first conductive contact layer.
    Type: Application
    Filed: June 14, 2006
    Publication date: September 20, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Yasuhito Uchiyama, Hironori Nishino
  • Patent number: 7271405
    Abstract: A photodetector for use at wavelengths of 2 ?m and longer has an intersubband absorption region to provide absorption at wavelengths beyond 2 ?m, integrated with an avalanche multiplier region to provide low-noise gain. In one particular design, the intersubband absorption region is a quantum-confined absorption region (e.g., based on quantum wells and/or quantum dots).
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: September 18, 2007
    Assignee: STC.UNM
    Inventors: Sanjay Krishna, John P. R David, Majeed M Hayat
  • Patent number: 7256098
    Abstract: A method of making a memory device and a memory device is described. In one embodiment, a method of manufacturing a memory device is described. The method includes providing a substrate having a tunneling layer deposited on a main surface and having a first conductive lines arranged on the tunneling layer running in a first direction. A layer of dielectric material is deposited on the first conductive lines. A control gate layer is deposited. The first conductive lines are patterned to produce gate stacks. Dielectric material is deposited in between the gate stacks. The gate stacks are partially removed to uncover floating gate electrodes in region of selection transistor lines to be prepared creating selection transistor line recesses running in the second direction. The selection transistor line recesses are filled with a conductive material to create the selection transistor lines.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: August 14, 2007
    Assignee: Infineon Technologies AG
    Inventor: Josef Willer
  • Patent number: 7226871
    Abstract: A method for forming a silicon oxynitride layer, suitable to be used in the production of semiconductor devices, e.g. poly-silicon thin film transistors, is provided. A plasma surface treatment is performed over a substrate after a silicon nitride/silicon oxide layer has been formed on the substrate by a glow discharge system to transform the silicon nitride/silicon oxide layer into a silicon oxynitride layer. The semiconductor device may be completely manufactured in simplex equipment. Therefore, the production time and production cost are favorably reduced.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: June 5, 2007
    Assignee: Industrial Technology Research Institute
    Inventors: Lin-En Chou, Hung-Che Ting
  • Patent number: 7220671
    Abstract: Chemical phase deposition processes utilizing organometallic precursors to form thin films are herein described. The organometallic precursors may include a single metal center or multiple metal centers. The chemical phase deposition may be chemical vapor deposition (CVD), atomic layer deposition (ALD), or hybrid CVD and ALD. The use of these chemical phase deposition processes with the organometallic precursors allows for the conformal deposition of films within openings having widths of less than 100 nm and more particularly less than 50 nm to form thin films such as barrier layers, seed layers, and adhesion layers.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: May 22, 2007
    Assignee: Intel Corporation
    Inventors: Harsono Simka, Juan Dominguez, Steven Johnston, Adrien Lavoie, Kevin O'Brien
  • Patent number: 7217658
    Abstract: High density plasma chemical vapor deposition and etch back processes fill high aspect ratio gaps without liner erosion or further underlying structure attack. The characteristics of the deposition process are modulated such that the deposition component of the process initially dominates the sputter component of the process. For example, reactive gasses are introduced in a gradient fashion into the HDP reactor and introduction of bias power onto the substrate is delayed and gradually increased or reactor pressure is decreased. In the case of a multi-step etch enhanced gap fill process, the invention may involve gradually modulating deposition and etch components during transitions between process steps. By carefully controlling the transitions between process steps, including the introduction of reactive species into the HDP reactor and the application of source and bias power onto the substrate, structure erosion is prevented.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: May 15, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Atiye Bayman, George D. Papasouliotis, Yong Ling, Weijie Zhang, Vishal Gauri, Mayasari Lim
  • Patent number: 7214570
    Abstract: An encapsulation for an electrical device is disclosed. A cap support is provided in the non-active regions of the device to prevent the package from contacting the active components of the device due to mechanical stress induced in the package.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: May 8, 2007
    Assignee: Osram GmbH
    Inventor: Ewald Karl Michael Guenther
  • Patent number: 7211513
    Abstract: Nitrogen doped titanium oxide coatings on a hot glass substrate are prepared by providing a uniform vaporized reactant mixture containing a titanium compound, a nitrogen compound and an oxygen-containing compound, and delivering the reactant mixture to the surface of a ribbon of hot glass, where the compounds react to form a nitrogen doped titanium oxide coating. The nitrogen doped titanium oxide coatings deposited in accordance with the invention demonstrate an increase in visible light absorption.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: May 1, 2007
    Assignee: Pilkington North America, Inc.
    Inventors: Michael R. Remington, Jr., Srikanth Varanasi, David A. Strickler
  • Patent number: 7211520
    Abstract: A method for fabricating a field effect transistor, in which, after the etching of the gate electrode, the removal of the etching mask is omitted since the etching mask serves as a gate dielectric. The etching mask or the dielectric has a self-assembled monolayer of an organic compound.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: May 1, 2007
    Assignee: Infineon Technologies AG
    Inventors: Ute Zschieschang, Hagen Klauk, Marcus Halik, Guenter Schmid, Stefan Braun
  • Patent number: 7209207
    Abstract: A flat panel display mainly includes a display panel and a plurality of drive IC chips mounted on the display panel by a chip-on-glass method. The display panel includes a plurality of electrode terminals, a plurality of external terminals and a plurality of first conductive traces. One surface of each drive IC chip is provided with a plurality of output terminals, a plurality of input terminals and a plurality of second conductive traces. The flat panel display is characterized in that corresponding input terminals on adjacent drive IC chips are electrically connected to one another through the first conductive traces of the display panel and the second conductive traces of the drive IC chips.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: April 24, 2007
    Assignee: Chi Mei Optoelectronics Corp.
    Inventor: Chin Lung Ting
  • Patent number: 7208784
    Abstract: A single-electron transistor includes a projecting feature, such as a pyramid, that projects from a face of a substrate. A first electrode is provided on the substrate face that extends onto the projecting feature. A second electrode is provided on the substrate face that extends onto the projecting feature and that is spaced apart from the first electrode. Accordingly, the geometric configuration of the projecting feature can define the spacing between the first and second electrodes. At least one nanoparticle is provided on the projecting feature between the first and second electrodes.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: April 24, 2007
    Assignee: Quantum Logic Devices, Inc.
    Inventor: Louis C. Brousseau, III
  • Patent number: 7205563
    Abstract: A QWIP structure is disclosed that includes a graded emitter barrier and can further be configured with a blocked superlattice miniband. The graded emitter barrier effectively operates to launch dark electrons into the active quantum well region, thereby improving responsivity. A graded collector barrier may also be included for reverse bias applications. The configuration operates to eliminate or otherwise reduce image artifacts or persistence associated with dielectric relaxation effect in low-background applications.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: April 17, 2007
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Mani Sundaram, Axel R Reisinger
  • Patent number: 7205215
    Abstract: The present invention provides a fabrication method of thin film transistor including a step of forming an amorphous silicon layer on a substrate, a step of forming a capping layer on the amorphous silicon layer, a step of forming a metal catalyst layer on the capping layer, a step of diffusing metal catalyst by selectively irradiating a laser beam onto the metal catalyst layer, and a step of crystallizing the amorphous silicon layer. The present invention has an advantage that a fabrication method of thin film transistor is provided, wherein the fabrication method of thin film transistor improves characteristics of device and obtains uniformity of the device by uniformly controlling diffusion of low concentration of metal catalyst through selective irradiation of laser beam and controlling size of grains and crystal growing position and direction in crystallization of amorphous silicon layer using super grain silicon method.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: April 17, 2007
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Byoung-Keon Park, Jin-Wook Seo, Tae-Hoon Yang, Ki-Yong Lee
  • Patent number: 7199038
    Abstract: According to an aspect of the invention, there is provided a method for fabricating a semiconductor device. The method may include forming at least one interconnection layer having a low dielectric constant insulating film and an interconnection buried in the low dielectric constant insulating film, forming a trench or a hole extending in the interconnection layer, performing heat treatment for the interconnection layer having the trench or the hole, and burying a material in the trench or the hole.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: April 3, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideshi Miyajima
  • Patent number: 7192868
    Abstract: A method of patterning and releasing chemically sensitive low k films without the complication of a permanent hardmask stack, yielding an unaltered free-standing structure is provided. The method includes providing a structure including a Si-containing substrate having in-laid etch stop layers located therein; forming a chemically sensitive low k film and a protective hardmask having a pattern atop the structure; transferring the pattern to the chemically sensitive low k film to provide an opening that exposes a portion of the Si-containing substrate; and etching the exposed portion of the Si-containing substrate through the opening to provide a cavity in the Si-containing substrate in which a free-standing low k film structure is formed, while removing the hardmask. In accordance with the present invention, the etching comprises a XeF2 etch gas.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: March 20, 2007
    Assignee: International Business Machines Corporation
    Inventors: John Michael Cotte, Nils Deneke Hoivik, Christopher Vincent Jahnes
  • Patent number: 7187587
    Abstract: Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the output lines form an array. A number of logic cells are formed at the intersections of output lines and address lines. Each of the logic cells includes a floating gate transistor which includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposing the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5 and/or a Perovskite oxide tunnel barrier.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: March 6, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 7186647
    Abstract: The present invention relates to a method for fabricating a semiconductor device with a landing plug contact structure. The method includes the steps of: forming a plurality of gate structures on a substrate; sequentially forming a first spacer and a second spacer on sidewalls of each gate structure; forming a plurality of landing plug contacts in a predetermined regions created between the gate structures; and forming a passivation layer on a resulting substrate structure including the first and the second spacers, the landing plug contacts and the gate structures. Particularly, the passivation layer which serves to prevent hydrogen ions from diffusing into a channel region is obtained by doping an N-type dopant capable of capturing hydrogen ions. The passivation layer is also obtained by forming a nitride layer capable of preventing the diffusion of hydrogen ions.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: March 6, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung-Woo Jin
  • Patent number: 7183181
    Abstract: A method of removing an edge bead of a coated material on a substrate. The substrate is rotated, and a fluid that solvates the coated material is delivered. The delivery of the fluid is directed radially inward on the substrate at a rate of between about three millimeters per second and about twenty millimeters per second until a desired innermost fluid delivery position on the substrate is attained. Immediately upon attaining the desired innermost fluid delivery position on the substrate, the delivery of the fluid is directed radially outward off the substrate at a rate of more than zero millimeters per second and less than about four millimeters per second. The rotation of the substrate is ceased.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: February 27, 2007
    Assignee: LSI Logic Corporation
    Inventors: Xiao Li, Roger Y. B. Young, Bruce J. Whitefield
  • Patent number: 7180648
    Abstract: An electro-absorption light intensity modulator device is provided that comprises a first and a second layer disposed relative to the first layer so as to provide a light-absorbing optical confinement region. The first layer comprises a first insulator layer, and the light-absorbing optical confinement region comprises at least one quantum-confined structure. The at least one quantum-confined structure possesses dimensions such, that upon an application of an electric field in the at least one quantum-confined structure, light absorption is at least partially due to a transition of at least one carrier between a valence state and a conduction state of the at least one quantum-confined structure. A method is also provided for fabricating an electro-absorption light intensity modulator device.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: February 20, 2007
    Assignee: Massachusetts Institute of Technology
    Inventors: Carl Dohrman, Saurabh Gupta, Eugene A. Fitzgerald
  • Patent number: 7177061
    Abstract: An optical modulator comprises a first waveguide layer and a barrier layer, and a quantum well layer sandwiched between the first waveguide layer and the barrier layer, where the quantum well layer has a graded composition that varies the bandgap energy of the quantum well layer between a minimum bandgap energy and the bandgap energy of at least one of the first waveguide layer and the barrier layer.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: February 13, 2007
    Assignee: Avago Technologies Fiber IP (Singapore) Pte. Ltd.
    Inventors: David P. Bour, Jintian Zhu
  • Patent number: 7173273
    Abstract: A semiconductor laser device has an n-GaAs substrate. On the n-GaAs substrate, by turns, are an n-AlGaInP cladding layer, an AlGaInP/GaInP MQW active layer, a p-AlGaInP first cladding layer, a single layer p-AlxGa1-xAs etching stopping layer, a p-AlGaInP second cladding layer with a stripe protrusion, and a p-GaAs contact layer. The portion, other than the stripe-form protrusion, of the p-AlGaInP second cladding layer is covered with an insulating film. The refractive index of the p-AlxGa1-xAs-ESL is nearly equal to the refractive index of each of the lower, first upper, and second upper cladding layers.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: February 6, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Harumi Nishiguchi, Tetsuya Yagi, Yasuaki Yoshida
  • Patent number: 7122827
    Abstract: The present invention is directed toward a method for fabricating low-defect nanostructures of wide bandgap materials and to optoelectronic devices, such as light emitting sources and lasers, based on them. The invention utilizes nanolithographically-defined templates to form nanostructures of wide bandgap materials that are energetically unfavorable for dislocation formation. In particular, this invention provides a method for the fabrication of phosphor-less monolithic white light emitting diodes and laser diodes that can be used for general illumination and other applications.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: October 17, 2006
    Assignee: General Electric Company
    Inventors: Azar Alizadeh, Pradeep Sharma, Steven Francis LeBoeuf, Suryaprakash Ganti, Mark Philip D'Evelyn, Kenneth Roger Conway, Peter Micah Sandvik, Loucas Tsakalakos
  • Patent number: 7119358
    Abstract: The invention relates to a semiconductor structure for use in the near infrared region, preferably in the range from 1.3 to 1.6 ?m, said structure comprising an active zone consisting of a plurality of epitaxially grown alternating layers of Si and Ge, a base layer of a first conductivity type disposed on one side of said active zone, and a cladding layer of the opposite conductivity type to the base layer, the cladding layer being provided on the opposite side of said active zone from said base layer, wherein the alternating Si and Ge layers of said active zone form a superlattice so that holes are located in quantized energy levels associated with a valance band and electrons are localized in a miniband associated with the conduction band and resulting from the superlattice structure. The invention is also directed to a method of manufacturing aforementioned structure.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: October 10, 2006
    Assignee: Max-Planck-Gesellschaft zur Forderung der Wissenschaften e.V.
    Inventors: Peter Werner, Viatcheslav Egorov, Vadim Talalaev, George Cirlin, Nikolai Zakharov
  • Patent number: 7106494
    Abstract: An apparatus for controlling propagation of incident electromagnetic radiation is described, comprising a composite material having electromagnetically reactive cells of small dimension relative to a wavelength of the incident electromagnetic radiation. Each electromagnetically reactive cell comprises a metallic element and a substrate. An electron population within the substrate near the metallic element of at least one of the electromagnetically reactive cells is temporally controllable to allow temporal control of an associated effective refractive index encountered by the incident electromagnetic radiation while propagating through said composite material.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: September 12, 2006
    Assignee: Hewlett-Packard Development Company, LP.
    Inventors: Viatcheslav V. Osipov, Alexandre Bratkovski
  • Patent number: 7101444
    Abstract: A semiconductor device includes at least one defect-free epitaxial layer. At least a part of the device is manufactured by a method of fabrication of defect-free epitaxial layers on top of a surface of a first solid state material having a first thermal evaporation rate and a plurality of defects, where the surface comprises at least one defect-free surface region, and at least one surface region in a vicinity of the defects, the method including the steps of selective deposition of a second material, having a high temperature stability, on defect-free regions of the first solid state material, followed by subsequent evaporation of the regions in the vicinity of the defects, and subsequent overgrowth by a third material forming a defect-free layer.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: September 5, 2006
    Assignee: NL Nanosemiconductor GmbH
    Inventors: Vitaly Shchukin, Nikolai Ledentsov
  • Patent number: 7098471
    Abstract: Semiconductor quantum well devices and methods of making the same are described. In one aspect, a device includes a quantum well structure that includes semiconductor layers defining interleaved heavy-hole and light-hole valance band quantum wells. Each of the quantum wells includes a quantum well layer interposed between barrier layers. One of the semiconductor layers that functions as a barrier layer of one of the light-hole quantum wells also functions as the quantum well layer of one of the heavy-hole quantum wells. Another of the semiconductor layers that functions as a barrier layer of one of the heavy-hole quantum wells also functions as the quantum well layer of one of the light-hole quantum wells.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: August 29, 2006
    Assignee: Avago Technologies Fiber IP (Singapore) Pte. Ltd.
    Inventors: Tirumala R. Ranganath, Jintian Zhu
  • Patent number: 7075829
    Abstract: Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the output lines form an array. A number of logic cells are formed at the intersections of output lines and address lines. Each of the logic cells includes a floating gate transistor which includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposing the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5 and/or a Perovskite oxide tunnel barrier.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: July 11, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 7067838
    Abstract: A light-emitting apparatus employing a GaN-based semiconductor. The light-emitting apparatus comprises an n-type clad layer (124); an active layer (129) including an n-type first barrier layer (126), well layers (128), and second barrier layers (130); a p-type block layer (132); and a p-type clad layer (134). By setting the band gap energy Egb of the p-type block layer (132), the band gap energy Eg2 of the second barrier layers (130), the band gap energy Eg1 of the first barrier layer (126), and the band gap energy Egc of the n-type and the p-type clad layers such that the relationship Egb>Eg2>Eg1?Egc is satisfied; the carriers can be efficiently confined; and the intensity of the light emission can be increased.
    Type: Grant
    Filed: April 16, 2004
    Date of Patent: June 27, 2006
    Assignee: Nitride Semiconductors Co., Ltd.
    Inventors: Hisao Sato, Naoki Wada, Shiro Sakai, Masahiro Kimura
  • Patent number: 7061014
    Abstract: Disclosed is a natural-superlattice homologous single-crystal thin film, which includes a complex oxide which is epitaxially grown on either one of a ZnO epitaxial thin film formed on a single-crystal substrate, the single-crystal substrate after disappearance of the ZnO epitaxial thin film and a ZnO single crystal. The complex oxide is expressed by the formula: M1M2O3 (ZnO)m, wherein M1 is at least one selected from the group consisting of Ga, Fe, Sc, In, Lu, Yb, Tm, Er, Ho and Y, M2 is at least one selected from the group consisting of Mn, Fe, Ga, In and Al, and m is a natural number of 1 or more. A natural-superlattice homologous single-crystal thin film formed by depositing the complex oxide and subjecting the obtained layered film to a thermal anneal treatment can be used in optimal devices, electronic devices and X-ray optical devices.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: June 13, 2006
    Assignee: Japan Science and Technology Agency
    Inventors: Hideo Hosono, Hiromichi Ota, Masahiro Orita, Kazushige Ueda, Masahiro Hirano, Toshio Kamiya
  • Patent number: 7045812
    Abstract: The present invention provides a technology for increasing the spectral width of semiconductor optical amplifiers, employing different separate confinement heterostructures (SCH's) so as to form non-identical multiple quantum wells such that the semiconductor photo-electronic devices have better temperature characteristics and more reliable modulation characteristics. If such a technology is used in the fabrication of semiconductor laser with a tunable wavelength, it is possible to achieve a large range of modulated wavelength, which is very useful in optical communication.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: May 16, 2006
    Assignee: National Science Council
    Inventors: Ching Fuh Lin, Bing Ruey Wu
  • Patent number: 7038234
    Abstract: A super-lattice thermoelectric device. The device includes p-legs and n-legs, each leg having a large number of alternating layers of two materials with differing electron band gaps. The n-legs in the device are comprised of alternating layers of silicon and silicon germanium. The p-legs includes alternating layers of B4C and B9C. In preferred embodiments the layers are about 100 angstroms thick. Applicants have fabricated and tested a first Si/SiGe (n-leg) and B4C/B9C (p-leg) quantum well thermocouple. Each leg was only 11 microns thick on a 5 micron Si substrate. Nevertheless, in actual tests the thermocouple operated with an amazing efficiency of 14 percent with a Th of 250 degrees C. Thermoelectric modules made according to the present invention are useful for both cooling applications as well as electric power generation. This preferred embodiment is a thermoelectric 10×10 egg crate type module about 6 cm×6 cm×0.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: May 2, 2006
    Assignee: Hi-Z Technology, Inc.
    Inventors: Saeid Ghamaty, Norbert B. Elsner, John C. Bass
  • Patent number: 7038233
    Abstract: An InGaAlAs-based buried type laser is expected to improve properties of the device, but generates defects at a re-growth interface and is difficult to realize a long-term reliability necessary for optical communication, due to inclusion of Al in an active layer. A semiconductor optical device and an optical module including a package substrate and a semiconductor optical device mounted on the package substrate are provided, whereby there are realized the improvement of device properties and the long-term reliability through the use of an Al composition ratio-reduced tensile strained quantum well layer.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: May 2, 2006
    Assignees: Hitachi, Ltd., Opnext Japan, Inc.
    Inventors: Tomonobu Tsuchiya, Tsukuru Ohtoshi
  • Patent number: 7023011
    Abstract: A photonic device includes a silicon semiconductor based superlattice. The superlattice has a plurality of layers that form a plurality of repeating units. At least one of the layers in the repeating unit is an optically active layer with at least one species of rare earth ion.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: April 4, 2006
    Assignee: Translucent, Inc.
    Inventors: Petar B. Atanackovic, Larry R. Marshall
  • Patent number: 7019325
    Abstract: The invention concerns a superluminescent light emitting diode (SLED) comprising a semiconductor heterostructure forming a PN junction and a waveguide. The semiconductor heterostructure includes a gain region with a contact means for biasing the PN junction so as to produce light emission including stimulated emission from an active zone of the gain region, and in the active zone a plurality of quantum dot layers, each quantum dot layer made up of a plurality of quantum dots and a plurality of adjoining layers, each adjoining layer adjacent to one of said quantum dot layers. The material composition or a deposition parameter of at least two adjoining layers is different. This ensures an enhanced emission spectral width.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: March 28, 2006
    Assignee: Exalos AG
    Inventors: Lianhe Li, Andrea Fiore, Lorenzo Occhi, Christian Velez
  • Patent number: 7019333
    Abstract: A photon source comprising: a quantum dot (21) having a first confined energy level capable of being populated with an electron and a second confined energy level capable of being populated by a hole; and supply means (23) for supplying carriers to the said energy levels, wherein the supply means are configured to supply a predetermined number of carriers to at least one of the energy levels to allow recombination of a predetermined number of carriers in said quantum dot to emit at least one photon.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: March 28, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Andrew J. Shields, Richard A. Hogg
  • Patent number: 7015497
    Abstract: The present invention provides a method for forming quantum tunneling devices comprising the steps of: (1) providing a quantum well, the quantum well comprising a composite material, the composite material comprising at least a first and a second material; and (2) processing the quantum well so as to form at least one segregated quantum tunneling structure encased within a shell comprised of a material arising from processing the composite material, wherein each segregated quantum structure is substantially comprised of the first material. The present invention also comprises additional methods of formation, quantum tunneling devices, said electronic devices.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: March 21, 2006
    Assignee: The Ohio State University
    Inventor: Paul R. Berger
  • Patent number: 7012283
    Abstract: According to an aspect of the present invention, a nitride semiconductor light emitting device includes a light emitting layer (106) having a quantum well structure with quantum well layers and barrier layers laminated alternately. The well layer is formed of a nitride semiconductor containing In, and the barrier layer is formed of a nitride semiconductor layer containing As, P or Sb. According to another aspect of the present invention, a nitride semiconductor light emitting device includes a light emitting layer having a quantum well structure with quantum well layers and barrier layers laminated alternately. The well layer is formed of GaN1?x?y?zAsxPySbz (0<x+y+z?0.3), and the barrier layer is formed of a nitride semiconductor containing In.
    Type: Grant
    Filed: September 17, 2001
    Date of Patent: March 14, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yuhzoh Tsuda, Shigetoshi Ito, Masahiro Araki
  • Patent number: 7005669
    Abstract: The invention provides “engineered” nonlinear nanocomposite materials with an extremely large ?(3) and fast temporal response along with optical properties that can be precisely tuned to satisfy the requirements of a particular application (e.g., optical, thermal, mechanical, etc.). In particular, the magnitude of the linear and nonlinear index of refraction can be adjusted substantially independently of the absorption spectrum of the material. In addition, the optical characteristics can be engineered substantially independently from the mechanical and chemical characteristics, providing exceptional performance and flexibility in terms of device-incorporation and process-stability.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: February 28, 2006
    Assignee: UltraDots, Inc.
    Inventor: Howard Wing Hoon Lee
  • Patent number: 6974967
    Abstract: A quantum logic gate utilizes an inter-polarization (dipole—dipole) interaction between excitons having polarization in semiconductor quantum well structures, or a spin exchange interaction between spin polarized excitons in the semiconductor quantum well structures. Problems associated with conventional semiconductor quantum well structures are solved in that a phase relaxation time is very short because of using inter-subband electrons, and that there is no usable ultrashort optical pulse laser technology because a subband transition wavelength is in a far-infrared region and hence ultra fast control is impossible.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: December 13, 2005
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventor: Kazuhiro Komori
  • Patent number: 6960779
    Abstract: A photon source for emitting entangled photons, the source comprising: at least one quantum dot having a degenerate exciton level; and exciton creation means to create a biexciton or higher order exciton within the at least one quantum dot.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: November 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Andrew James Shields, Richard Mark Stevenson
  • Patent number: 6940087
    Abstract: Disclosed is an electron source 10 including an electron source element 10a formed on the side of one surface of an insulative substrate 1. The electron source element 10a includes a lower electrode 2, a composite nanocrystal layer 6 and a surface electrode 7. The composite nanocrystal layer 6 includes a plurality of polycrystalline silicon grains 51, a thin silicon oxide film 52 formed over the surface of each of the grains 51, a number of nanocrystalline silicons 63 residing between the adjacent grains 51, and a silicon oxide film 64 formed over the surface of each of the nanocrystalline silicons 63. The silicon oxide film 64 is an insulating film having a thickness less than the crystal grain size of the nanocrystalline silicon 63. The surface electrode 7 is formed of a carbon thin film 7a laminated on the composite nanocrystal layer 6 while being in contact therewith, and a metal thin film 7b laminated on the carbon thin film 7a.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: September 6, 2005
    Assignees: Matsushita Electric Works, Ltd.
    Inventors: Takuya Komoda, Nobuyoshi Koshida, Tsutomu Ichihara
  • Patent number: 6936838
    Abstract: Disclosed is a nitride-based semiconductor device including a first nitride semiconductor layer doped with an n type impurity, an active layer formed on the first nitride semiconductor layer, the active layer including a plurality of quantum well layers and a plurality of quantum barrier layers alternately laminated over one another, at least one of the quantum layers being doped with the n type impurity, and a nitride semiconductor layer formed over the active layer, and doped with a p type impurity. The quantum barrier layer doped with the n type impurity includes an internal layer portion doped with the n type impurity, and an anti-diffusion film arranged at an interface of the quantum barrier layer with an adjacent one of the quantum well layers, the anti-diffusion film having an n type impurity concentration lower than that of the internal layer portion.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: August 30, 2005
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Sun Woon Kim
  • Patent number: 6933548
    Abstract: A negative differential resistance device is disclosed which is particularly suited as a replacement in memory cells for conventional pull-up and load elements such as NDR diodes, passive resistors, and conventional FETs. The NDR device includes a charge trapping layer formed at or extremely near to an interface between a substrate (which can be silicon or SOI) and a gate insulation layer. The NDR device can be shut off during static operations to further reduce power dissipation.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: August 23, 2005
    Assignee: Synopsys, Inc.
    Inventor: Tsu-Jae King
  • Patent number: 6927412
    Abstract: A semiconductor light emitter includes a quantum well active layer which includes nitrogen and at least one other Group-V element, and barrier layers which are provided alongside the quantum well active layer, wherein the quantum well active layer and the barrier layers together constitute an active layer, wherein the barrier layers are formed of a Group-III-V mixed-crystal semiconductor that includes nitrogen and at least one other Group-V element, a nitrogen composition thereof being smaller than that of the quantum well active layer.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: August 9, 2005
    Assignee: Ricoh Company, Ltd.
    Inventors: Takashi Takahashi, Shunichi Sato, Morimasa Kaminishi
  • Patent number: 6924501
    Abstract: A quantum logic gate utilizes an inter-polarization (dipole-dipole) interaction between excitons having polarization in semiconductor quantum well structures, or a spin exchange interaction between spin polarized excitons in the semiconductor quantum well structures. Problems associated with conventional semiconductor quantum well structures are solved in that a phase relaxation time is very short because of using inter-subband electrons, and that there is no usable ultrashort optical pulse laser technology because a subband transition wavelength is in a far-infrared region and hence ultra fast control is impossible.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: August 2, 2005
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventor: Kazuhiro Komori
  • Patent number: 6900466
    Abstract: A semiconductor component for generating a polychromatic electromagnetic radiation has a semiconductor chip with a first semiconductor layer and a second semiconductor layer, which is provided adjacent to the first semiconductor layer and has an electroluminescent region. The electroluminescent region emits electromagnetic radiation of a first wavelength. The first semiconductor layer includes a material which, when excited with the electromagnetic radiation of the first wavelength, re-emits radiation with a second wavelength which is longer than the first wavelength.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: May 31, 2005
    Assignee: Osram GmbH
    Inventors: Detlef Hommel, Helmut Wenisch