Abstract: An electro-optic (EO) phase modulator is disclosed. The EO phase modulator includes: an insulating layer; a central optical waveguide over the insulating layer; a first region having a first type doping adjacent to a first sidewall of the central optical waveguide; a second region having a second type doping opposite to the first type doping adjacent to a second sidewall of the central optical waveguide opposite to the first sidewall; and a first dielectric layer passing through the central optical waveguide from a top surface of the central optical waveguide to a bottom surface of the central optical waveguide. A method of manufacturing the same is disclosed as well.

Abstract: A method of forming a semiconductor device includes receiving a substrate with a plurality of gate structures; forming spacers on sidewalls of the gate structures; evaluating a pitch variation to the gate structures; determining an etch recipe according to the pitch variation; performing an etch process to source/drain regions associated with the gate structures using the etch recipe, thereby forming source/drain recesses with respective depths; and performing an epitaxy growth to form source/drain features in the source/drain recesses using a semiconductor material.

Abstract: Disclosed herein are wide band gap integrated circuits, such as gallium nitride (GaN) integrated circuits, including a plurality of groups of epitaxial layers formed on an engineered substrate, and methods of making the WBG integrated circuits. The epitaxial layers have a coefficient of thermal expansion (CTE) substantially matching the CTE of the engineered substrate. Mesas, internal interconnects, and electrodes configure each group of epitaxial layers into a WBG device. External interconnects connect different WBG devices into a WBG integrated circuit. The CTE matching allows the formation of epitaxial layers with reduced dislocation density and an overall thickness of greater than 10 microns on a six-inch or larger engineered substrate. The large substrate size and thick WBG epitaxial layers allow a large number of high density WBG integrated circuits to be fabricated on a single substrate.

Abstract: This invention is directed toward a method for manufacturing a semiconductor device with a heterostructure comprises covering a semiconductor structure with a seed layer structure; forming one or more separated circularly shaped openings in the seed layer structure to expose the semiconductor structure therein, and leave the seed layer structure outside the one or more separated circularly shaped openings; forming an insulator layer thereon; etching the obtained structure to (i) expose at least a portion of the seed layer structure, such that the exposed at least portion of the seed layer structure surrounds each of the one or more separated circularly shaped openings, and (ii) optionally expose the semiconductor structure, in the one or more separated circularly shaped openings; and epitaxially growing a semiconductor layer from the exposed at least portion of the seed layer structure, firstly mainly vertically and then into each of the one or more separated circularly shaped openings until the epitaxially g

Abstract: An epitaxial substrate for electronic devices, including: a Si-based substrate; an AlN initial layer provided on the Si-based substrate; and a buffer layer provided on the AlN initial layer, wherein the roughness Sa of the surface of the AlN initial layer on the side where the buffer layer is located is 4 nm or more. As a result, an epitaxial substrate for electronic devices, in which V pits in a buffer layer structure can be suppressed and longitudinal leakage current characteristics can be improved when an electronic device is fabricated therewith, is provided.

Abstract: A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings to a first semiconductor material, and forming an inner spacer liner on sidewalls of the fin structure openings. A channel semiconductor material is epitaxially formed on a surface of the first semiconductor material filling at least a portion of the fin structure openings. The spacer material is recessed with an etch that is selective to the inner spacer liner to form a first spacer. The inner spacer liner is removed selectively to the channel semiconductor material. A gate structure on the channel semiconductor material, and a second semiconductor material is formed in contact with the channel semiconductor material.

Abstract: A semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer containing aluminum located on the first nitride semiconductor layer, one or more nitride layers containing aluminum located on the second nitride semiconductor layer, a source electrode located on the second nitride semiconductor layer, a drain electrode located on one of the second nitride semiconductor layer or the nitride layer, and a gate electrode located between the source electrode and the drain electrode. An end of the nitride layer on the source electrode side thereof is located between the gate electrode and the drain electrode.

Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.

Abstract: A package comprising an at least partially electrically conductive chip carrier, a first transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, and a second transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, wherein the first transistor chip and the second transistor chip are connected to form a half bridge, and wherein the second connection terminal of the first transistor chip is electrically coupled with the first connection terminal of the second transistor chip by a bar section of the chip carrier extending between an exterior edge region of the first transistor chip and an exterior edge region of the second transistor chip and maintaining a gap laterally spacing the first transistor chip with regard to the second transistor chip.

Abstract: A semiconductor device includes a substrate with an NMOSFET region and a PMOSFET region, a first active pattern on the NMOSFET region, a second active pattern on the PMOSFET region, a dummy pattern between the NMOSFET and PMOSFET regions, and device isolation patterns on the substrate that fill trenches between the first active pattern, the second active pattern, and the dummy pattern. Upper portions of the first and second active patterns have a fin-shaped structure protruding between the device isolation patterns. The upper portions of the first and second active patterns contain semiconductor materials, respectively, that are different from each other, and an upper portion of the dummy pattern contains an insulating material.

Abstract: Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT).

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices comprising multiple channels. In one aspect, a method of fabricating a transistor device comprises forming on the substrate a plurality of vertically repeating layer stacks each comprising a first layer, a second layer and a third layer stacked in a predetermined order, wherein each of the first, second and third layers is formed of silicon, silicon germanium or germanium and has a different germanium concentration compared to the other two of the first, second and third layers. The method additionally includes selectively removing the first layer with respect to the second and third layers from each of the layer stacks, such that a gap interposed between the second layer and the third layer is formed in each of the layer stacks.

Abstract: Bulk crystal of group III nitride having thickness greater than 1 mm with improved crystal quality, reduced lattice bowing and/or reduced crack density and methods of making. Bulk crystal has a seed crystal, a first crystalline portion grown on the first side of the seed crystal and a second crystalline portion grown on the second side of the seed crystal. Either or both crystalline portions have an electron concentration and/or an oxygen concentration similar to the seed crystal. The bulk crystal can have an additional seed crystal, with common faces (e.g. same polarity, same crystal plane) of seed crystals joined so that a first crystalline part grows on the first face of the first seed crystal and a second crystalline part grows on the first face of the second seed crystal. Each crystalline part's electron concentration and/or oxygen concentration may be similar to its corresponding seed crystal.

Abstract: An anti-fuse structure is provided that contains multiple breakdown points which result in low resistance after the anti-fuse structure is blown. The anti-fuse structure is provided using a method that is compatible with existing FinFET device processing flows without requiring any additional processing steps.

Abstract: A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.

Abstract: Safety radio devices are described herein. One method of constructing a safety radio device includes mounting a radio module on a first layer of a circuit board, fabricating an antenna on a second layer of the circuit board, and constructing a safety radio device by connecting the radio module to the antenna through an aperture formed in the second layer of the circuit board.

Abstract: A switch comprising a spin-transistor and a first control wire. The spin-transistor is configured so that when a magnetic field applied to the spin-transistor is less than a threshold value, the transistor is in a conductive state in which electric current flows through the spin-transistor. When the magnetic field applied to the spin-transistor is greater than the threshold value, the spin-transistor is in a resistive state in which the electric current flowing through the spin-transistor is substantially reduced. The first control wire is for receiving a current to affect the magnetic field applied to the spin-transistor.

Abstract: Techniques for forming a photonic integrated circuit having a facet coupler and a surface coupler are described. The photonic integrated circuit may be on a wafer, which may be diced to form an integrated device. The facet coupler may be positioned proximate to an edge of the integrated device, and the surface coupler may be positioned on a surface of the integrated device. The surface coupler may allow for evaluation and assessment of the circuit's performance, which may facilitate wafer-level testing of the circuit and diagnosis of the circuit before and after packaging.

Abstract: A semiconductor device includes a first nitride semiconductor layer, a source electrode on the first nitride semiconductor layer, a drain electrode on the first nitride semiconductor layer, a gate electrode on the first nitride semiconductor layer and between the source electrode and the drain electrode, a gate field plate electrode that is separated from the first nitride semiconductor layer, and includes one end in direct contact with the gate electrode, and the other end positioned between the gate electrode and the drain electrode, a first interlayer insulating film that is separated from the gate electrode and is between the gate field plate electrode and the first nitride semiconductor layer, and a second interlayer insulating film that is between the gate electrode and the first interlayer insulating film and has a dielectric constant higher than a dielectric constant of the first interlayer insulating film.

Abstract: A semiconductor device composed of a through-substrate-via (TSV) interconnect, and methods for forming the interconnect.

Abstract: A vertically stacked heterostructure device includes: (1) a substrate; and (2) vertically stacked layers disposed over the substrate and including (a) a source electrode including a layer of graphene; (b) a drain electrode; and (c) a semiconducting channel disposed between the source electrode and the drain electrode. During operation of the device, a current is configured to flow between the source electrode and the drain electrode through the semiconducting channel.

Abstract: A nitride semiconductor device includes: a substrate; a buffer layer formed on the substrate; a laminated body formed by two or more cycles of semiconductor layers each including a first nitride semiconductor layer, and a second nitride semiconductor layer having a larger band gap than a band gap of the first nitride semiconductor layer, the first and second nitride semiconductor layers being laminated in this order on the buffer layer; a first electrode; and a second electrode. A channel layer is formed in each of the semiconductor layers at an interface between the first nitride semiconductor layer and the second nitride semiconductor layer. A carrier concentration of the channel layer in the uppermost semiconductor layer is lower than a carrier concentration of each of the channel layers of the other semiconductor layers.

Abstract: III-N transistors with epitaxial semiconductor heterostructures having steep subthreshold slope are described. In embodiments, a III-N HFET employs a gate stack with balanced and opposing III-N polarization materials. Overall effective polarization of the opposing III-N polarization materials may be modulated by an external field, for example associated with an applied gate electrode voltage. In embodiments, polarization strength differences between the III-N materials within the gate stack are tuned by composition and/or film thickness to achieve a desired transistor threshold voltage (Vt). With polarization strengths within the gate stack balanced and opposing each other, both forward and reverse gate voltage sweeps may generate a steep sub-threshold swing in drain current as charge carriers are transferred to and from the III-N polarization layers and the III-N channel semiconductor.

Abstract: A method of forming a semiconductor structure includes providing an emitter and a collector on a surface of an insulator layer. The emitter and the collector are spaced apart and have a doping of a first conductivity type. An intrinsic base is formed between the emitter and the collector and on the insulator layer by epitaxially growing the intrinsic base from at least a vertical surface of the emitter and a vertical surface of the collector. The intrinsic base has a doping of a second conductivity type opposite to the first conductivity type, and a first heterojunction exists between the emitter and the intrinsic base and a second heterojunction exists between the collector and the intrinsic base.

Abstract: Disconnection of a base line is suppressed even when a short-side direction of a collector layer is parallel to crystal orientation [011]. A bipolar transistor includes: a collector layer that has a long-side direction and a short-side direction in a plan view, in which the short-side direction is parallel to crystal orientation [011], a cross-section perpendicular to the short-side direction has an inverted mesa shape, and a cross-section perpendicular to the long-side direction has a forward mesa shape; a base layer that is formed on the collector layer; a base electrode that is formed on the base layer; and a base line that is connected to the base electrode and that is drawn out from an end in the short-side direction of the collector layer to the outside of the collector layer in a plan view.

Abstract: According to example embodiments, a high electron mobility transistor (HEMT) includes: stack including a buffer layer, a channel layer containing a two dimensional electron gas (2DEG) channel, and a channel supply layer sequentially stacked on each other, the stack defining a first hole and a second hole that are spaced apart from each other. A first electrode, a second electrode, and third electrode are spaced apart from each other along a first surface of the channel supply layer. A first pad is on the buffer layer and extends through the first hole of the stack to the first electrode. A second pad is on the buffer layer and extends through the second hole of the stack to the second electrode. A third pad is under the stack and electrically connected to the third electrode.

Abstract: Materials, devices and methods related to below-resonance radio-frequency (RF) circulators and isolators. In some embodiments, a circulator can include a conductor having a plurality of signal ports, and one or more magnets configured to provide a magnetic field. The circulator can further include one or more ferrite disks implemented relative to the conductor and the one or more magnets so that an RF signal can be routed selectively among the signal ports due to the magnetic field. Each of the one or more ferrite disks can include synthetic garnet material having dodecahedral sites, octahedral sites and tetrahedral sites, with bismuth (Bi) occupying at least some of the dodecahedral sites, and aluminum (Al) occupying at least some of the tetrahedral sites. Such synthetic garnet material can be represented by a formula Y3-x-2y?zBixCa2y+zFe5-y-z-aVyZrzAlaO12. In some embodiments, x?1.4, y?0.7, z?0.7, and a?0.75.

Abstract: A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings to a first semiconductor material, and forming an inner spacer liner on sidewalls of the fin structure openings. A channel semiconductor material is epitaxially formed on a surface of the first semiconductor material filling at least a portion of the fin structure openings. The spacer material is recessed with an etch that is selective to the inner spacer liner to form a first spacer. The inner spacer liner is removed selectively to the channel semiconductor material. A gate structure on the channel semiconductor material, and a second semiconductor material is formed in contact with the channel semiconductor material.

Abstract: Monolithic integration of high-frequency GaN-HEMTs and GaN-Schottky diodes. The integrated HEMTs/Schottky diodes are realized using an epitaxial structure and a fabrication process which reduces fabrication cost. Since the disclosed process preferably uses self-aligned technology, both devices show extremely high-frequency performance by minimizing device parasitic resistances and capacitances. Furthermore, since the Schottky contact of diodes is formed by making a direct contact of an anode metal to the 2DEG channel the resulting structure minimizes an intrinsic junction capacitance due to the very thin contact area size. The low resistance of high-mobility 2DEG channel and a low contact resistance realized by a n+GaN ohmic regrowth layer reduce a series resistance of diodes as well as access resistance of the HEMT.

Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region. The source includes a GaN-layer coupled to an InGaN layer. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for an optical absorption based device using a semiconductor-dielectric-semiconductor structure. In one embodiment, the device may include an optical waveguide to transmit light inputted by a light source. The waveguide may include a first semiconductor layer, a second semiconductor layer disposed above the first semiconductor layer, a dielectric layer disposed between the first and second semiconductor layers, and an absorptive material layer disposed between the dielectric layer and the first or second semiconductor layer. The absorptive material layer may have a variable light absorption coefficient to allow intensity of light to be modulated through modulation of the absorption coefficient. The light may be substantially confined between the first and second semiconductor layers of the waveguide. Other embodiments may be described and/or claimed.

Abstract: A method is provided for producing an optoelectronic device, comprising the steps of providing a substrate, applying a nucleation layer on a surface of the substrate, applying and patterning a mask layer on the nucleation layer, growing a nitride semiconductor in a first growth step, wherein webs are laid which form a lateral lattice, wherein the webs have trapezoidal cross-sectional areas in places in the direction of growth, and laterally overgrowing the webs with a nitride semiconductor in a second growth step, to close spaces between the webs.

Abstract: An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.

Abstract: A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (E/G) ratio of process gases used in the first growth stage; and performing a second growth stage with a second E/G ratio of process gases used in the second growth stage different from the first E/G ratio.

Abstract: Reusable substrate bases for producing multilayer semiconductor devices are provided, as well as free-standing semiconductor devices and reusable substrate bases produced for the multilayer semiconductor devices. The reusable substrate bases comprise a Si-based substrate, a transition lattice overlayed thereon, and a sacrificial ZnO-based layer overlayed on the transition lattice. The transition lattice comprises alternating transition layers of aluminum nitride (AlN) and GaN or Al-doped GaN. The multilayer semiconductor devices comprise the aforesaid reusable substrate bases and a semiconductor stack which comprises a pair of p-n junction forming layers. Methods for producing the multilayer semiconductor devices, the reusable substrate base, as well as free standing semiconductor devices detached from the reusable substrate bases, are also provided.

Abstract: A method of manufacturing a transistor device includes forming a compound semiconductor material on a semiconductor carrier, forming a source region and a drain region spaced apart from each other in the compound semiconductor material with a channel region interposed between the source and drain regions, forming a Schottky diode integrated with the semiconductor carrier, and forming contacts extending from the source and drain regions through the compound semiconductor material and in electrical contact with the Schottky diode so that the Schottky diode is connected in parallel between the source and drain regions.

Abstract: A semiconductor structure comprises a substrate, an epitaxial layer, an active area and a termination. The substrate has a first conducting type of semiconductor material. The epitaxial layer disposed on the substrate has a first conducting type of semiconductor material. The active area is a working area of the semiconductor structure. The termination protects the active area. The termination has a junction termination extension (JTE) having a second conducting type of semiconductor material. The counter-doped area is disposed in the JTE area and has the first conducting type of semiconductor material. A dose of the first conducting type of semiconductor material in the counter-doped area increases along one direction.

Abstract: There is disclosed an organic photosensitive optoelectronic devices comprising organic photoconductive materials, which comprise singlet fission host materials doped with triplet forming materials. There is also disclosed devices made from such materials, such as an organic photovoltaic cell, a photoconductor cell, a photodetector, organic photosensors, chemical sensors, and biological sensors. Methods of fabricating such devices are also disclosed.

Abstract: After forming a first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region on recessed surfaces of a semiconductor portion that are not covered by a gate structure, at least one dielectric layer is formed to cover the first-side and the second-side epitaxial semiconductor regions and the gate structure. A second-side contact opening is formed within the at least one dielectric layer to expose an entirety of the second-side epitaxial semiconductor region. The exposed second-side epitaxial semiconductor region can be replaced by a new second-side epitaxial semiconductor region having a composition different from the first-side epitaxial semiconductor region or can be doped by additional dopants, thus creating an asymmetric first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region. Each of the first-side epitaxial semiconductor region and the second-side epitaxial semiconducting region can function as either a source or a drain for a transistor.

Abstract: A semiconductor device of this embodiment includes: a first semiconductor layer including AlXGa1-XN; a second semiconductor layer provided above the first semiconductor layer, and including undoped or n-type AlYGa1-YN; a first and second electrodes provided above the second semiconductor layer; a third semiconductor layer provided above the second semiconductor layer between the first electrode and the second electrode, is at a distance from each of the first and second electrodes, and including p-type AlZGa1-ZN; a control electrode provided above the third semiconductor layer; a fourth semiconductor layer provided above the third semiconductor layer between the first electrode and the control electrode, is at a distance from the control electrode, and including n-type AlUGa1-UN; and a fifth semiconductor layer provided above a portion of the third semiconductor layer between the control electrode and the second electrode, is at a distance from the control electrode, and including n-type AlUGa1-UN.

Abstract: A semiconductor device includes a substrate having first and second sides and a first active layer disposed over the first side of the substrate. A second active layer is disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. At least one trench extends through the first and second active layers and the two-dimensional electron gas layer and into the substrate. A conductive material lines the trench. A first electrode is disposed on the second active layer and a second electrode is disposed on the second side of the substrate.

Abstract: A diode (200) is disclosed having improved efficiency, smaller form factor, and reduced reverse biased leakage current. Schottky diodes (212) are formed on the sidewalls (210) of a mesa region (206). The mesa region (206) is a cathode of the Schottky diode (212). The current path through the mesa region (206) has a lateral and a vertical current path. The diode (200) further comprises a MOS structure (214), p-type regions (220), MOS structures (230), and p-type regions (232). MOS structure (214) with the p-type regions (220) pinch-off the lateral current path under reverse bias conditions. P-type regions (220), MOS structures (230), and p-type regions (232) each pinch-off the vertical current path under reverse bias conditions. MOS structure (214) and MOS structures (230) reduce resistance of the lateral and vertical current path under forward bias conditions. The mesa region (206) can have a uniform or non-uniform doping concentration.

Abstract: A nitride-based transistor includes a semiconductor structure, a gate electrode and a leakage current suppression structure. The semiconductor structure includes a first nitride-based semiconductor layer doped with impurities of a first conductivity type, a second nitride-based semiconductor layer doped with impurities of a second conductivity type, and a third nitride-based semiconductor layer doped with impurities of the first conductivity type. The gate electrode overlaps the second nitride-based semiconductor layer. The leakage current suppression structure is disposed along edges of the semiconductor structure. The leakage current suppression structure includes a depletion layer in at least one of the first and third nitride-based semiconductor layers.

Abstract: A plurality of gate structures are formed straddling nFET semiconductor fins and pFET semiconductor fins which extend upwards from a surface of a semiconductor substrate. A boron-doped silicon germanium alloy material is epitaxially grown from exposed surfaces of both the nFET semiconductor fins and the pFET semiconductor fins not protected by the gate structures. An anneal is then performed. During the anneal, silicon and germanium from the boron-doped silicon germanium alloy material diffuse into the nFET semiconductor fins and act as an n-type dopant forming a junction in the nFET semiconductor fins. Since boron is a Group IIIA element it does not have any adverse effect. During the same anneal, boron from the boron-doped silicon germanium alloy material will diffuse into the pFET semiconductor fins to form a junction therein.

Abstract: A flip chip type laser diode includes a substrate, a first semiconductor layer, an emitting layer, a second semiconductor layer, at least one current conducting layer, a patterned insulating layer, at least one first electrode and a second electrode. The first semiconductor layer is disposed on the substrate. The emitting layer is disposed on a part of the first semiconductor layer. The second semiconductor layer is disposed on the emitting layer and forms a ridge mesa. The current conducting layer is disposed on a part of the first semiconductor layer. The patterned insulating layer covers the first semiconductor layer, the emitting layer, a part of the second semiconductor layer and a part of the current conducting layer. The first electrode and the second electrode are disposed on areas of the current conducting layer and the second semiconductor layer which are not covered by the patterned insulating layer.

Abstract: An epitaxial-deposition composite substrate, of more than about 50 mm diameter, in which a nitride-compound semiconductor first substrate is bonded together with a second substrate of either identical or different material. The first substrate is ion-implanted, and on its nitrogen-face side is coated with a special film of thickness within a predetermined range. On a bonding side of the second substrate a special coating of thickness within the predetermined range is formed. The join created by the coated nitrogen-face side of the first substrate being bonded to the coated bonding side of the second substrate occupies at least 90% of the surface area where the two substrates meet.

Abstract: The photodiode device comprises a doped region (2) contiguous with a contact region (3) of the same conductivity type located at the substrate surface (1?), an appertaining anode or cathode connection (7, 11), a further contact region (5) of an opposite conductivity type at the substrate surface, and a further anode or cathode connection (8, 12). The contact region (3) is arranged at least on opposite sides of an active area of the substrate surface that covers the further contact region (5). A lateral pn junction (16) and an associated space charge region is formed at the substrate surface by a boundary of one of the contact regions, the boundary facing the other contact region. A field electrode (6) is arranged above the lateral pn junction, separated from the lateral pn junction by a dielectric material (10), and is provided with a further electrical connection (9, 13) separate from the anode and cathode connections.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device includes a diffusion control layer as part of an emitter epitaxial structure. The IC device may utilize a common metallization scheme to simultaneously form an emitter contact and a base contact. Other embodiments may also be described and/or claimed.

Abstract: According to one embodiment, a semiconductor wafer includes a substrate, an AlN buffer layer, a foundation layer, a first high Ga composition layer, a high Al composition layer, a low Al composition layer, an intermediate unit and a second high Ga composition layer. The first layer is provided on the foundation layer. The high Al composition layer is provided on the first layer. The low Al composition layer is provided on the high Al composition layer. The intermediate unit is provided on the low Al composition layer. The second layer is provided on the intermediate unit. The first layer has a first tensile strain and the second layer has a second tensile strain larger than the first tensile strain. Alternatively, the first layer has a first compressive strain and the second layer has a second compressive strain smaller than the first compressive strain.

Abstract: A group III nitride composite substrate includes a support substrate and a group III nitride film. A ratio st/mt of a standard deviation st of the thickness of the group III nitride film, to a mean value mt of the thickness thereof is 0.001 or more and 0.2 or less, and a ratio so/mo of a standard deviation so of an absolute value of an off angle between a main surface of the group III nitride film and a plane of a predetermined plane orientation, to a mean value mo of the absolute value of the off angle thereof is 0.005 or more and 0.6 or less. Accordingly, there is provided a low-cost and large-diameter group III nitride composite substrate including a group III nitride film having a large thickness, a small thickness variation, and a high crystal quality.