Abstract: A method of fabrication of a metal oxide semiconductor field effect transistor is disclosed. At first, a substrate on which a gate structure is formed is provided. Afterward, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a plurality of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.

Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a pre-seeding layer and a nucleation layer. The pre-seeding layer may include a first material for pre-seeding and a second material for masking so as to reduce tensile stress.

Abstract: In a transistor, a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may be positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain-inducing semiconductor alloy. For this purpose, two or more “disposable” spacer elements of different etch behavior may be used in order to define different lateral offsets at different depths of the corresponding cavities. Consequently, enhanced uniformity and, thus, reduced transistor variability may be accomplished, even for sophisticated semiconductor devices.

Abstract: Lateral collection architecture for a photodetector is achieved by depositing electrically conducting SLS layers onto a planar substrate and diffusing dopants of a carrier type opposite that of the layers through the layers at selected regions to disorder the superlattice and create diode junctions oriented transversely to the naturally enhanced lateral mobility of photogenerated charge carriers within the superlattice. The diode junctions are terminated at a top surface of the photodetector within an SLS layer of wide bandgap material to minimize unwanted currents. A related architecture disorders the superlattice of topmost SLS layers by diffusing therethrough a dopant configured as a grid and penetrating to a lower SLS layer having the same carrier type as the dopant and opposite that of the topmost layers to isolate pixels within the topmost layers. Ohmic contacts may be deposited on doped regions, pixels, and substrate to provide desired external connections.

Abstract: An (AlInGaN) based semiconductor device, comprising a first layer that is a semipolar or nonpolar nitride (AlInGaN) layer having a lattice constant that is partially or fully relaxed, deposited on a substrate or a template, wherein there are one or more dislocations at a heterointerface between the first layer and the substrate or the template; one or more strain compensated layers on the first layer, for defect reduction and stress engineering in the device, that is lattice matched to a larger lattice constant of the first layer; and one or more nonpolar or semipolar (AlInGaN) device layers on the strain compensated layers.

Abstract: A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Further, the semiconductor device and method provide for an NMOS source/drain region of a transistor within the substrate including a second strained layer in the NMOS source/drain region and a second capping layer in contact with the second strained layer.

Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

Abstract: A semiconductor device including transistors and strain layers is provided. Each transistor includes a source region and a drain region on a substrate and a gate structure on a channel region between the source region and the drain region. Lengths of the channel regions of these transistors are the same, but at least one source or drain region has a width along a channel length direction and the width is different from widths of other source or drain regions. The strain layers include first and second strain layers embedded separately at two sides of each gate structure in the substrate. A first width of each first strain layer along the channel length direction is the same, and a second width of each second strain layer along the channel length direction is the same.

Abstract: A semiconductor device comprises the following elements: an active layer comprising a quantum well structure and a buffer layer beneath the active layer adapted to form a confinement layer for charge carriers in the active layer. The buffer layer is adapted so as not to increase an overall strain in the active layer. The active layer is already strained as a result of a lattice mismatch between the active layer and the buffer layer. Strain in the buffer layer may be controlled by use of a strain control buffer layer and by appropriate choices of material and composition for the buffer layer and for a substrate on which the buffer layer is grown.

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Abstract: The present invention discloses structures to increase carrier mobility using engineered substrate technologies for a solid state device. Structures employing rare-earth compounds enable heteroepitaxy of different semiconductor materials of different orientations.

Abstract: A light emitting diode (LED) having a barrier layer with a superlattice structure is disclosed. In an LED having an active region between an GaN-based N-type compound semiconductor layer and a GaN-based P-type compound semiconductor layer, the active region comprises a well layer and a barrier layer with a superlattice structure. As the barrier layer with the superlattice structure is employed, it is possible to reduce occurrence of defects caused by lattice mismatch between the well layer and the barrier layer.

Abstract: Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.

Abstract: Semiconductor light-emitting structures are shown on engineered substrates having a graded composition. The composition of the substrate may be graded to achieve a lattice constant on which a yellow-green light-emitting semiconductor material may be disposed. In some embodiments, the structure may be substantially free of aluminum.

Abstract: A gallium nitride device substrate comprises a layer of gallium nitride containing an additional lattice parameter altering element located over a substitute substrate.

Abstract: In one embodiment, a semiconductor nanowire having a monotonically increasing width with distance from a middle portion toward adjoining semiconductor pads is provided. A semiconductor link portion having tapered end portions is lithographically patterned. During the thinning process that forms a semiconductor nanowire, the taper at the end portions of the semiconductor nanowire provides enhanced mechanical strength to prevent structural buckling or bending. In another embodiment, a semiconductor nanowire having bulge portions are formed by preventing the thinning of a semiconductor link portion at pre-selected positions. The bulge portions having a greater width than a middle portion of the semiconductor nanowire provides enhanced mechanical strength during thinning of the semiconductor link portion so that structural damage to the semiconductor nanowire is avoided during thinning.

Abstract: A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

Abstract: A light emitting device of the invention includes an electron transporting layer, a hole transporting layer provided mutually facing the electron transporting layer with a distance between the hole transporting layer and the electron transporting layer, a phosphor layer having a layer of a plurality of semiconductor fine particles sandwiched between the electron transporting layer and the hole transporting layer, a first electrode provided facing the electron transporting layer and connected electrically, and a second electrode provided facing the hole transporting layer and connected electrically: in which the semiconductor fine particles composing the phosphor layer have a p-type part and an n-type part inside of the particles and have a pn-junction in the interface of the p-type part and the n-type part and are arranged in a manner that the p type part is partially brought into contact with the hole transporting layer and at the same time, the n type part is partially brought into contact with the electron

Abstract: A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s). In this manner, the polarizations of the respective adjacent sub-layers compensate for one another.

Abstract: A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Further, the semiconductor device and method provide for an NMOS source/drain region of a transistor within the substrate including a second strained layer in the NMOS source/drain region and a second capping layer in contact with the second strained layer.

Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

Abstract: Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a first barrier layer coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier layer, the quantum well channel comprising a first material having a first lattice constant, and a source structure coupled to the quantum well channel, the source structure comprising a second material having a second lattice constant, wherein the second lattice constant is different than the first lattice constant to impart a strain on the quantum well channel. Other embodiments may be described and/or claimed.

Abstract: In the method of fabricating a quantum well structure which includes a well layer and a barrier layer, the well layer is grown at a first temperature on a sapphire substrate. The well layer comprises a group III nitride semiconductor which contains indium as a constituent. An intermediate layer is grown on the InGaN well layer while monotonically increasing the sapphire substrate temperature from the first temperature. The group III nitride semiconductor of the intermediate layer has a band gap energy larger than the band gap energy of the InGaN well layer, and a thickness of the intermediate layer is greater than 1 nm and less than 3 nm in thickness. The barrier layer is grown on the intermediate layer at a second temperature higher than the first temperature. The barrier layer comprising a group III nitride semiconductor and the group III nitride semiconductor of the barrier layer has a band gap energy larger than the band gap energy of the well layer.

Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

Abstract: The present invention provides nanowires and nanoribbons that are well suited for use in thermoelectric applications. The nanowires and nanoribbons are characterized by a periodic compositional longitudinal modulation. The nanowires are constructed using lithographic techniques from thin semiconductor membranes, or “nanomembranes.

Abstract: A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on a side adjacent the gate electrode. The stressor includes a first stressor layer having a second lattice constant substantially different from the first lattice constant; and a second stressor layer on the first stressor layer, wherein the second stressor has a third lattice constant substantially different from the first and the second lattice constants.

Abstract: A silicon on insulator (SOI) substrate is converted into a strained SOI substrate by first providing an SOI substrate having a thin silicon layer and an insulator and at least one first epitaxial relaxing layer on the SOI-substrate. Then a defect region is produced in a layer by implantation of SI ions above the silicon layer of the SOI-substrate. Finally the first layer is relaxed by a thermal treatment in an inert atmosphere to simultaneously strain the silicon layer of the SOI-substrate via dislocation mediated strain transfer and to produce the strained silicon layer directly on the insulator.

Abstract: A metamorphic buffer layer is formed on a semi-insulating substrate by an epitaxial growth method, a collector layer, a base layer, an emitter layer and an emitter cap layer are sequentially laminated on the metamorphic buffer layer, and a collector electrode is provided in contact with an upper layer of the metamorphic buffer layer. The metamorphic buffer layer is doped with an impurity, in a concentration equivalent to or higher than that in a conventional sub-collector layer, by an impurity doping process during crystal growth so that the metamorphic buffer layer will be able to play the role of guiding the collector current to the collector electrode. Since the sub-collector layer, which is often formed of a ternary mixed crystal or the like having a high thermal resistance, can be omitted, the heat generated in the semiconductor device can be rapidly released into the substrate.

Abstract: A method for fabricating a stressed MOS device in and on a semiconductor substrate is provided. The method comprises the steps of forming a gate electrode overlying the semiconductor substrate and etching a first trench and a second trench in the semiconductor substrate, the first trench and the second trench formed in alignment with the gate electrode. A stress inducing material is selectively grown in the first trench and in the second trench and conductivity determining impurity ions are implanted into the stress inducing material to form a source region in the first trench and a drain region in the second trench. To preserve the stress induced in the substrate, a layer of mechanically hard material is deposited on the stress inducing material after the step of ion implanting.

Abstract: A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

Abstract: There is provided a nitride semiconductor light emitting device including: an n-type semiconductor region; an active layer formed on the n-type semiconductor region; a p-type semiconductor region formed on the active layer; an n-electrode disposed in contact with the n-type semiconductor region; a p-electrode formed on the p-type semiconductor region; and at least one intermediate layer formed in at least one of the n-type semiconductor region and the p-type semiconductor region, the intermediate layer disposed above the n-electrode, wherein the intermediate layer is formed of a multi-layer structure where at least three layers with different band gaps from one another are deposited, wherein the multi-layer structure includes one of an AlGaN layer/GaN layer/InGaN layer stack and an InGaN layer/GaN layer/AlGaN layer stack.

Abstract: The invention relates to a single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.

Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.

Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

Abstract: Provided are a light emitting diode (LED) and a method for manufacturing the same. The LED includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The active layer includes a well layer and a barrier layer that are alternately laminated at least twice. The barrier layer has a thickness at least twice larger than a thickness of the well layer.

Abstract: A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on a side adjacent the gate electrode. The stressor includes a first stressor layer having a second lattice constant substantially different from the first lattice constant; and a second stressor layer on the first stressor layer, wherein the second stressor has a third lattice constant substantially different from the first and the second lattice constants.

Abstract: A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material, an upper gate insulating layer of crystalline rare earth insulating material, and an upper gate layer of crystalline rare earth conductive material. The upper gate layer and the upper gate electrically insulating layer are etched and a contact is deposited on the upper gate layer to define an upper gate structure. An impurity is implanted into the lower gate layer to define a lower gate area aligned with the upper gate structure. A source and drain are formed in the active layer and contacts are deposited on the source and drain, respectively.

Abstract: A first film made of SiGe is formed over a support substrate whose surface layer is made of Si. A gate electrode is formed over a partial area of the first film, and source and drain regions are formed in the surface layer of the support substrate on both sides of the gate electrode. The gate electrode and source and drain regions constitute a first field effect transistor. A first stressor internally containing compressive strain or tensile strain is formed over the first film on both sides of the gate electrode of the first field effect transistor. The first stressor forms strain in a channel region.

Abstract: A structure and a method of making the structure. The structure includes a field effect transistor including: a first and a second source/drain formed in a silicon substrate, the first and second source/drains spaced apart and separated by a channel region in the substrate; a gate dielectric on a top surface of the substrate over the channel region; and an electrically conductive gate on a top surface of the gate dielectric; and a dielectric pillar of a first dielectric material over the gate; and a dielectric layer of a second dielectric material over the first and second source/drains, sidewalls of the dielectric pillar in direct physical contact with the dielectric layer, the dielectric pillar having no internal stress or an internal stress different from an internal stress of the dielectric layer.

Abstract: A method of forming a semiconductor structure (and the resulting structure), includes straining a free-standing semiconductor, and fixing the strained, free-standing semiconductor to a substrate.

Abstract: An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.

Abstract: Embodiments provide a quantum dot active structure and a methodology for its fabrication. The quantum dot active structure includes a substrate, a plurality of alternating regions of a quantum dot active region and a strain-compensation region, and a cap layer. The strain-compensation region is formed to eliminate the compressive strain of an adjacent quantum dot active region, thus allowing quantum dot active regions to be densely-stacked. The densely-stacked quantum dot active region provides increased optical modal gain for semiconductor light emitting devices such as edge emitting lasers, vertical cavity lasers, detectors, micro-cavity emitters, optical amplifiers or modulators.

Abstract: A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Further, the semiconductor device and method provide for an NMOS source/drain region of a transistor within the substrate including a second strained layer in the NMOS source/drain region and a second capping layer in contact with the second strained layer.

Abstract: A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: A pn junction type Group III nitride semiconductor light-emitting device 10 (11) of the present invention has a light-emitting layer 2 of multiple quantum well structure in which well layers 22 and barrier layers 21 including Group III nitride semiconductors are alternately stacked periodically between an n-type clad layer 105 and a p-type clad layer 107 which are formed on a crystal substrate and which include Group III nitride semiconductors, in which one end layer 21m of the light-emitting layer 2 is closest to and opposed to the n-type clad layer, and the other end layer 21n of the light-emitting layer 2 is closest to and opposed to the p-type clad layer, both the one and the other end layers are barrier layers, and the other end layer 21n is thicker than the barrier layer of the one end layer.

Abstract: A field effect transistor (“FET”) is provided which includes an active semiconductor region including a channel region, a first source-drain region and a second source-drain region. A major surface of the active semiconductor region is divided into a mutually exclusive first portion and a second portion. A first liner applies a first stress to the first portion of the major surface, and a second liner applies a second stress to the second portion of the major surface. The first and second stresses are each selected from high tensile stress, high compressive stress and neutral stress, with the first stress being different from the second stress. The liners can help to differentiate a first operating current conducted by the first portion of the FET under one operating condition and a second operating current that is conducted by the second portion of the FET under a different operating condition.

Abstract: The method for forming a quantum dot according to the present invention comprises the step of forming an oxide in a dot-shape on the surface of a semiconductor substrate 10, the step of removing the oxide to form a concavity 16 in the position from which the oxide has been removed, and the step of growing a semiconductor layer 18 on the semiconductor substrate with the concavity formed in to form a quantum dot 20 of the semiconductor layer in the concavity. The concavity is formed in the semiconductor substrate by forming the oxide dot in the surface of the semiconductor substrate and removing the oxide, whereby the concavity can be formed precisely in a prescribed position and in a prescribed size. The quantum dot is grown in such a concavity, whereby the quantum dot can have good quality and can be formed in a prescribed position and in a prescribed size.

Abstract: An infrared focal plane array (FPA) is disclosed which utilizes a strained-layer superlattice (SLS) formed of alternating layers of InAs and InxGa1?xSb with 0?x?0.5 epitaxially grown on a GaSb substrate. The FPA avoids the use of a mesa structure to isolate each photodetector element and instead uses impurity-doped regions formed in or about each photodetector for electrical isolation. This results in a substantially-planar structure in which the SLS is unbroken across the entire width of a 2-D array of the photodetector elements which are capped with an epitaxially-grown passivation layer to reduce or eliminate surface recombination. The FPA has applications for use in the wavelength range of 3-25 ?m.

Abstract: A semiconductor includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor includes a first stressor region and a second stressor region on the first stressor region, wherein the second stressor region extends laterally closer to a channel region underlying the gate stack than the first stressor region.