Abstract: A hetero field effect transistor includes: a main semiconductor region including a first semiconductor layer and a second semiconductor layer formed thereon to allow a generation of a two-dimensional carrier gas layer of a first conductive type on a heterojunction interface therebetween; a source electrode formed on the main semiconductor region; a drain electrode formed on the main semiconductor region and separated from the source electrode; a third semiconductor layer of a second conductive type different from the first conductive type, the third semiconductor layer being formed on the second semiconductor layer and located between the source electrode and the drain electrode; and a gate electrode formed on the third semiconductor layer. A concave portion is formed in an upper surface of the second semiconductor layer at a region immediately below the gate electrode.

Abstract: A nitride semiconductor device includes: first through third nitride semiconductor layers formed in sequence over a substrate. The second nitride semiconductor layer has a band gap energy larger than that of the first nitride semiconductor layer. The third nitride semiconductor layer has an opening. A p-type fourth nitride semiconductor layer is formed so that the opening is filled therewith. A gate electrode is formed on the fourth nitride semiconductor layer.

Abstract: A semiconductor device having a silicide film above source-drain regions comprises an element isolation insulating film which is provided so as to enclose an element forming region of a semiconductor substrate whose main component is silicon and contains silicon oxide as a main component, a gate electrode which is formed above the element forming region via a gate insulating film, diffused layers which are formed in the semiconductor substrate so as to sandwich a channel region below the gate electrode, semiconductor regions which are formed so as to sandwich the channel region and diffused regions and are composed of semiconductor material whose lattice constant differs from that of silicon, a silicon nitride film which is formed between the semiconductor regions and the element isolation insulating film and above the lowest part of the semiconductor regions, and a conducting film which is formed at the surface of the semiconductor regions.

Abstract: An apparatus includes a field-effect transistor (FET). The FET includes a region of first semiconductor and a layer of second semiconductor that is located on the region of the first semiconductor. The layer and region form a semiconductor heterostructure. The FET also includes source and drain electrodes that are located on one of the region and the layer and a gate electrode located to control a conductivity of a channel portion of the semiconductor heterostructure. The channel portion is located between the source and drain electrodes. The gate electrode is located vertically over the channel portion and portions of the source and drain electrodes.

Abstract: A method for in situ formation of low defect, strained silicon and a device formed according to the method are disclosed. In one embodiment, a silicon germanium layer is formed on a substrate, and a portion of the silicon germanium layer is removed to expose a surface that is smoothed with a smoothing agent. A layer of strained silicon is formed on the silicon germanium layer. In various embodiments, the entire method is conducted in a single processing chamber, which is kept under vacuum.

Abstract: A power transistor. One embodiment provides a power transistor having a first terminal, a second terminal and a control terminal. A support layer is formed of a first material having a first bandgap. An active region is formed of a second material having a second bandgap wider than the first bandgap, and is disposed on the support layer. The active region is arranged to form part of a current path between the first and second terminal in a forward mode of operation. The active region includes at least one pn-junction.

Abstract: An MIM capacitance element (capacitance lower electrode, capacitance insulation film and capacitance upper electrode) is provided on a first insulation film on a semiconductor substrate. An interlayer insulation film is provided so as to cover the MIM capacitance element and flattened. The interlayer insulation film is provided with a first connection plug connected to the capacitance upper electrode, a first wiring layer, and a second wiring layer. A second insulation film is provided on the interlayer insulation film. The second insulation film is provided with first and second openings. A wiring pull-out portion which connects the first connection plug and the second wiring layer to each other is provided on the second insulation film.

Abstract: Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the, same conductivity type through an opening in a compound semiconductor material of the opposite conductivity type. Another embodiment discloses a transistor including multiple compound semiconductor layers where a highly doped compound semiconductor material is electrically connected to a compound semiconductor layer of the same conductivity type through an opening in a compound semiconductor layer of the opposite conductivity type. Embodiments further include metal contacts electrically connected to the highly doped compound semiconductor material. A substantially planar semiconductor device is disclosed. In embodiments, the compound semiconductor material may be silicon carbide.

Abstract: A semiconductor light-emitting device includes: a substrate; a first conductivity type layer formed on the substrate and including a plurality of group III-V nitride semiconductor layers of a first conductivity type; an active layer formed on the first conductivity type layer; and a second conductivity type layer formed on the active layer and including a group III-V nitride semiconductor layer of a second conductivity type. The first conductivity type layer includes an intermediate layer made of AlxGa1?x?yInyN (wherein 0.001?x<0.1, 0<y<1 and x+y<1).

Abstract: A nitride semiconductor laminated structure comprises: a substrate; a first p-type nitride semiconductor layer formed using an organometallic compound as a Group III element source material, a p-type impurity source material and ammonia as a Group V element source material, with the hydrogen concentration in the first p-type nitride semiconductor layer being 1×1019 cm?3 or less; and a second p-type nitride semiconductor layer on the first p-type nitride semiconductor layer by formed using an organometallic compound as a Group III element source material, a p-type impurity source material, and ammonia and a hydrazine derivatives as Group V element source materials, with the carbon concentration in the second p-type nitride semiconductor layer being 1×1018 cm?3 or less.

Abstract: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a first p-AlGaN layer, a second p-AlGaN layer and a high concentration p-GaN layer are formed in this order on a substrate. A gate electrode establishes ohmic contact with the high concentration p-GaN layer. A source electrode and a drain electrode are formed on the undoped AlGaN layer. Two-dimensional electron gas generated at the interface between the undoped AlGaN layer and the undoped GaN layer and the first and second p-AlGaN layers form a pn junction in a gate region. The second p-AlGaN layer covers a SiN film in part.

Abstract: A semiconductor device provided with an emitter layer having a narrowed base contact portion. The semiconductor device includes a collector layer arranged on a semiconductor substrate. A conductive layer is arranged on the collector layer. A silicon film is arranged on the conductive layer. An emitter electrode is arranged on the silicon film. A first film covers the side of the emitter electrode. The silicon film includes a first region contacting the emitter electrode and a second region differing from the first region. A contact surface between the first region and the emitter electrode is located at a level that is higher than that of the lower surface of the first film. At least part of the second region of the silicon film is located between the conductive layer and the first film and is in contact with the conductive layer and the first film.

Abstract: Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased.

Abstract: A field effect transistor including an i-type first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer and having a band gap energy higher in magnitude than that of the first semiconductor layer. The first semiconductor layer and second semiconductor layer are each made of a gallium nitride-based compound semiconductor layer. A gate electrode is formed on the second semiconductor layer and a second electrode is formed on the first semiconductor layer. Thus, the field effect transistor is constructed in such a manner as the first semiconductor layer and second semiconductor layer are interposed between the gate electrode and the second electrode. Thus field effect transistor is able to discharge the holes that are accumulated in the channel from the elemental structure and to improve the withstand voltage of the field effect transistor.

Abstract: A method of compensating resistivity of a near-surface region of a substrate includes epitaxially growing a buffer layer on the substrate, wherein the buffer is grown as having a dopant concentration as dependent on resistivity and conductivity of the substrate, so as to deplete residual or excess charge within the near-surface region of the substrate. The dopant profile of the buffer layer be smoothly graded, or may consist of sub-layers of different dopant concentration, to also provide a highly resistive upper portion of the buffer layer ideal for subsequent device growth. Also, the buffer layer may be doped with carbon, and aluminum may be used to getter the carbon during epitaxial growth.

Abstract: The present invention relates to a Tunnel Field Effect Transistor (TFET). which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The IFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.

Abstract: A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.

Abstract: It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform.

Abstract: The invention relates to a semiconductor device with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2), and a collector region (3), which are provided with respectively a first, a second, and a third connection conductor (4, 5, 6), while the bandgap of the base region (2) is lower than that of the collector region (3) or of the emitter region (1), for example owing to the use of a silicon-germanium alloy instead of pure silicon. Such a device is very fast, but its transistor shows a relatively low BVceo. In a device according to the invention, the emitter region (1) or the base region (2) comprises a sub-region (1B, 2B) with a reduced doping concentration, which sub-region (1B, 2B) is provided with a further connection conductor (4B, 5B) which forms a Schottky junction with the sub-region (1B, 2B). Such a device results in a transistor with a particularly high cut-off frequency fT but with no or hardly any reduction of the BVceo.

Abstract: In order to improve light-emission efficiency without degrading protection performance of a light-emitting layer structure a three p-type layer structure composed of first to third layers is provided in contact with a light-emitting layer structure. The first layer is an n-type AlGaN layer that serves as a protective layer, the third layer is a GaN:Mg layer that serves as a contact layer and the second layer is an AlGaN:Mg layer formed between these layers as an intermediate layer. The provision of the intermediate layer enables an InGaN layer to be thoroughly protected from heat during growth of layers above even if the n-type AlGaN layer is made thin, whereby the GaN:Mg layer can be brought near the light-emitting layer structure to enhance the efficiency of hole injection into the light-emitting layer structure and thus increase the light-emission efficiency.

Abstract: A strained-channel semiconductor structure and method of fabricating the same. The strained-channel semiconductor structure comprises a substrate composed of a first semiconductor material with a first natural lattice constant. A channel region is disposed in the substrate and a gate stack is disposed over the strained channel region A pair of source/drain regions are oppositely disposed in the substrate adjacent to the channel region, wherein each of the source/drain regions comprises a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant rather than the first natural lattice constant, an inner side and an outer side corresponding to the gate stack, and at least one outer sides laterally contacts the first semiconductor material of the substrate.

Abstract: The present invention provides a nitride semiconductor device comprising an active layer of a quantum well structure, a first conductive clad layer and a second conductive clad layer. The first conductive clad layer is made of the quaternary nitride semiconductor InAlGaN having a lattice constant equal to or larger than that of the active layer and includes a first nitride semiconductor layer having an energy band gap larger than that of the active layer, a second nitride semiconductor layer having an energy band gap smaller than that of the first nitride semiconductor layer and a third nitride semiconductor layer having an energy band gap larger than that of the second nitride semiconductor layer, sequentially closer to the active layer.

Abstract: According to the present invention, there is a provided a semiconductor device having, a collector contact layer made of an n-type GaAs layer; a first collector layer formed on the collector contact layer and made of an n-type GaAs layer; a second collector layer formed on the first collector layer and made of a p-type GaAs layer; a third collector layer formed on the second collector layer and made of an n-type InGaP layer; a fourth collector layer formed on the third collector layer and made of an n-type InGaP layer having an impurity concentration higher than that of the third collector layer; a fifth collector layer formed on the fourth collector layer and made of an n-type GaAs layer; a base layer formed on the fifth collector layer and made of a p-type GaAs layer; and an emitter layer formed on the base layer and made of an n-type InGaP layer.

Abstract: A semiconductor light detecting device has a light absorbing layer; and a pn junction, carriers generated by the light absorbing layer absorbing the light in a light detecting region being detected as a photoelectric current through a depletion layer provided by applying a backward voltage to the pn junction, wherein the light detecting region in the light absorbing layer is all depleted in a slate where an operating voltage is applied.

Abstract: A semiconductor device includes an AlGaN film formed on a GaN film on a substrate, a gate electrode formed on the AlGaN film, and source and drain electrodes formed on either side of the gate electrode on the AlGaN film. An n-type InxGayAl1-x-yN film is interposed between the source and drain electrodes and the AlGaN film. Alternatively, the semiconductor device includes an n-type InxGayAl1-x-yN film formed on a GaN film on a substrate, a gate electrode formed on the InxGayAl1-x-yN film, and source and drain electrodes formed on either side of the gate electrode on the InxGayAl1-x-yN film.

Abstract: According to one exemplary embodiment, a gallium arsenide heterojunction bipolar transistor comprises a collector layer and a first spacer layer situated over the collector layer, where the first spacer layer is a high-doped P+ layer. For example, the first spacer layer may comprise GaAs doped with carbon. The gallium arsenide heterojunction bipolar transistor further comprises a base layer situated over the first spacer layer. The base layer may comprise, for example, a concentration of indium, where the concentration of indium is linearly graded in the base layer. The base layer may comprise InGaAsN, for example. The gallium arsenide heterojunction bipolar transistor further comprises an emitter layer situated over the base layer. The emitter layer may comprise, for example, InGaP.

Abstract: A thin film crystal wafer with pn-junction comprising a first layer of a first conductivity type which is a 3-5 group compound semiconductor represented by a general formula: InxGayAlzP (0≦x≦1, 0≦y≦1, 0≦z≦, x+y+z=1), and the second layer of a first conductivity type which is a 3-5 group compound semiconductor represented by a general formula: InxGayAlZ,As (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1), said second layer being made above said first layer, and at a heterojunction interface formed between said first layer and said second layer, further comprising a charge compensation layer of a first conductivity type with an impurity concentration higher than that of said first and second layers.

Abstract: An enhanced extended drift heterostructure (EEDH) photodiode and method of making provide enhanced electron response. The EEDH photodiode includes adjacent first and second light absorption layers, an ohmic anode contact interfaced to the first layer and a cathode contact interfaced to the second layer. The cathode contact includes either a Schottky cathode contact or an ohmic cathode contact and a contact layer. The EEDH photodiode optionally further includes one or more of a carrier block layer interfaced to the first layer, a graded characteristic in the first layer, and a collector layer interfaced to the second layer. The first layer has a doping concentration that is greater than doping concentrations of the second layer and the optional collector layer. The first and second layers have band gap energies that facilitate light absorption. The optional layers have band gap energies that are relatively nonconducive to light absorption.

Abstract: A full-color LED display includes red, green and blue LED elements. A first substrate is used to form red and green LED elements which are then covered by a first passivation layer. A second substrate is bonded to the passviation layer and polished as a thin substrate layer. A blue LED element is fabricated on the thin substrate layer. The three LED elements are then covered by a second passivation layer to construct a full-color LED device. A full-color, high resolution and high brightness LED display is formed by a plurality of full-color LED devices arranged in rows and columns in a matrix form.

Abstract: J-FET having a first semiconductor region (2, 3), which comprises a first contact (7) with a highly doped contact layer (8) serving as a source disposed between two second contacts (9) serving as a gate on its first surface (4). The three contacts (7, 9) are each connected to a respective second semiconductor region (5, 6). The first and second semiconductor regions (2, 3, 5, 6) are of opposite conductivity types. The second semiconductor regions (5) connected to the second contacts (9) extend in the first semiconductor region (2, 3) below the second semiconductor region (6) that is connected to the first contact (7), with the result that the three second semiconductor regions (5, 6) at least partially overlap in a projection onto a horizontal plane and a channel region (11) is formed between the three second semiconductor regions (5, 6) in the first semiconductor region (2, 3).

Abstract: A light-emitting diode having an excellent high-speed response characteristic and capable of giving a large light output with a small variation of the light output during the operation is provided. In the light-emitting diode, an active layer comprising a single quantum well layer of p-type Ga0.51In0.49P, a lower barrier layer of p-type (Al0.5Ga0.5)0.51In0.49P and an upper barrier layer of p-type (Al0.5Ga0.5)0.51In0.49P is highly doped with p-type dopant (Zn, Mg, Be, C) or n-type dopant (Si, Se, Te) to produce non-radiative recombination level in the upper and lower barrier layers. Carriers injected into the quantum well layer not only recombine radiatively therein and also recombine nonradiatively at boundaries of the upper barrier layer and the lower barrier layer, remarkably increasing recombination velocity of carriers and dramatically improving the response characteristic.

Abstract: Provided is a manufacturing method of a semiconductor device which comprises forming, all over the surface of a substrate below the channel region of a MISFET, a p type impurity layer having a first peak in impurity concentration distribution and another p type impurity layer having a second peak in impurity concentration distribution, each layer having a function of preventing punch-through. Compared with a device having a punch through stopper layer of a pocket structure, the device of the present invention is suppressed in fluctuations in the threshold voltage. Moreover, with a relative increase in the controllable width of a depletion layer, a sub-threshold swing becomes small, thereby making it possible to prevent lowering of the threshold voltage and to improve a switching rate of the MISFET.

Abstract: A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.

Abstract: An MSM semiconductor circuit formed on a semi-insulating substrate that includes a set of contacts, first and second absorption layers, and a wide band gap buffer layer. The first absorption layer is formed on the semi-insulating substrate. The second absorption layer operably coupled to the set of contacts. The wide band gap buffer layer disposed between the first absorption layer and the second absorption layer.

Abstract: The present invention relates to a semiconductor device with one or more current confinement regions and to a method of manufacturing such a device, particularly buried heterostructure light emitting devices such as semiconductor lasers and light emitting diodes. The device comprises an active layer, a current conduction region, one or more current confinement regions adjacent the current conduction region. The current conduction region and current confinement region are arranged to channel an applied electric current to the active layer. The or each current confinement region includes both a metal-doped current blocking structure and a p-n junction current blocking structure. The p-n current blocking structure is between the current conduction region and the metal-doped current blocking structure.

Abstract: A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) on the germanium layer, and forming a gate electrode (e.g., titanium nitride 60) on the gate dielectric. The method may comprise forming source and drain regions 64 in the substrate on either side of the gate dielectric. The germanium layer, which is preferably epitaxially grown, generally prevents formation of a low dielectric constant layer between the gate dielectric and the semiconductor substrate. The disclosed structure comprises a germanium layer 52 disposed on a semiconductor substrate (e.g. silicon 20), a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) disposed on the germanium layer, and a gate electrode (e.g., titanium nitride 60) disposed on the gate dielectric.

Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis.

Abstract: An embodiment of the instant invention is a transistor formed on a semiconductor substrate of a first conductivity type and having an upper surface, the transistor comprising: a well region (well 204 of FIG. 1a) formed in the semiconductor substrate (layer 202 of FIG. 1a), the well region of a second conductivity type opposite that of the first conductivity type; a source region (source region 208 of FIG. 1a) formed in the well region in the semiconductor substrate, the source region of the second conductivity type; a drain region (drain 210 of FIG. 1a) formed in the semiconductor substrate and spaced away from the source region by a channel region (given by length L1+L2), the drain region of the second conductivity type; a conductive gate electrode (layer 218 of FIG. 1a) disposed over the semiconductor substrate and over the channel region; a gate insulating layer (layer 214 of FIG.

Abstract: In order to reduce a contact resistance of an electrode of a semiconductor device, a metal layer is directly formed on a source area and a drain area so as to form a source electrode and a drain electrode without providing a cap layer thereunder. Consequently, a step for removing the cap layer can be eliminated, simplifying the manufacturing process for the semiconductor device.

Abstract: Provided is a manufacturing method of a semiconductor device which comprises forming, all over the surface of a substrate below the channel region of a MISFET, a p type impurity layer having a first peak in impurity concentration distribution and another p type impurity layer having a second peak in impurity concentration distribution, each layer having a function of preventing punch-through. Compared with a device having a punch through stopper layer of a pocket structure, the device of the present invention is suppressed in fluctuations in the threshold voltage. Moreover, with a relative increase in the controllable width of a depletion layer, a sub-threshold swing becomes small, thereby making it possible to prevent lowering of the threshold voltage and to improve a switching rate of the MISFET.

Abstract: A hetero-bipolar transistor comprises: a first-conductive-type Si semiconductor substrate layer; a first Si1-xGex layer (0<x<1) formed on the first-conductive-type Si semiconductor substrate, the first Si1-xGex layer being doped with a first-conductive-type impurity; a second Si1-xGex layer formed on the first Si1-xGex layer, the second Si1-xGex layer being doped with a second-conductive-type impurity; and a Si layer formed on the second Si1-xGex layer, the Si layer being doped with the first-conductive-type impurity by a concentration higher than that of the second-conductive-type impurity.

Abstract: The present invention provides an epitaxial wafer comprising, on a p-type GaAs single-crystal substrate, a first p-type layer; a p-type cladding layer; a p-type active layer; and an n-type cladding layer, wherein the n-type cladding layer has a carrier concentration of 1×1017 to 1×1018 cm−3; a sulfur concentration of 3×1016 atoms/cm3 or less; and a thickness of 20-50 &mgr;m. The maximum silicon concentration in the portion of the p-type cladding layer within 2 &mgr;m of the interface between the p-type cladding layer and the first p-type layer is less than 1×1018 atoms/cm3; the concentration of carbon, sulfur, or oxygen in the first p-type layer is less than 1×1017 atoms/cm3; the p-type cladding layer has a thickness of 50-80 &mgr;m; the first p-type layer has a carrier concentration of 3×1017 to 1×1018 cm−3; and the n-type cladding layer contains germanium at a concentration of 3×1018 cm−3 or less.

Abstract: A soft recovery diode of the invention includes a first semiconductor layer having N type conductivity. A second N-type semiconductor layer is disposed on the first semiconductor layer and has a lower impurity concentration than the first semiconductor layer. In the surface of the second semiconductor layer opposite to the surface contacting the first semiconductor layer, a plurality of spaced-apart first metallic layers are formed. A second metallic layer is disposed on the first metallic layers and/or the exposed portions of the second semiconductor layer. The first and second metallic layers provide barriers of different heights.

Abstract: A semiconductor device with a tunnel diode (23) is particularly suitable for various applications. Such a device comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types and having doping concentrations which are so high that breakdown between them leads to conduction by means of tunnelling. A disadvantage of the known device is that the current-voltage characteristic is not yet steep enough for some applications. In a device according to the invention, the portions (2A, 3A) of the semiconductor regions (2, 3) adjoining the junction (23) comprise a mixed crystal of silicon and germanium. It is surprisingly found that the doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions (2, 3).

Abstract: The present invention is a fabrication process and structure of a negative-differential-resistance device characterized by triple negative-differential-resistance at room temperature and hexad negative-differential-resistance at a low temperature (−105° C.). The component parts are, from bottom upward, a substrate made of GaAs material, a first layer made of GaAs material, a second layer made of InGaAs (InxGa1−xAs) material, a third layer made of AlGaAs material, and a metallic coating by vaporization on the third layer. Of the three layers, the second one is a varied layer composed of our successively varied laminates. The device, by utilizing the successive carriers accumulations of step-graded InGaAs subwells and the barrier lowering effect, provides MNDR properties and good potential for multiple-valued logic circuit applications.

Abstract: At an n--n hetero-interface in a GaN-based or ZnSe-based multilayered semiconductor laser and light-emitting diode, an excessive voltage drop causing the operating voltage to increased is reduced, thereby lengthening the service life of the device. A single or plurality of n-type intermediate layers are provided in the n--n hetero-interface region where the excessive voltage drop develops. The excessive voltage drop developing at the n--n hetero-interface is decreased by setting the energy value at the edge of the conduction band of each intermediate layer to a mid-value between the energy values at the edges of the conduction bands of the n-type compound semiconductors adjoining both sides of the intermediate layer. The configuration of a GaN-based MQW laser including the intermediate layer formed on sapphire substrate is shown.

Abstract: A Gunn diode includes a layered structure including at least a cathode layer, an anode layer, and an active region interposed between the cathode and anode layers, wherein at least a portion of the active region is an AlGaAs layer.

Abstract: A gallium nitride type compound semiconductor light-emitting device of the present invention includes: a substrate; a buffer layer, formed on the substrate, having a thick region and a thin region in terms of a thickness taking a surface of the substrate as a reference level; and a semiconductor layered structure, formed on the buffer layer, at least including an undoped gallium nitride type compound semiconductor layer, a gallium nitride type compound semiconductor active layer, and a P-type gallium nitride type compound semiconductor cladding layer.

Abstract: A metal-semiconductor field effect transistor includes an AlGaAs buffer layer made of Al.sub.x Ga.sub.1-x As, wherein 0<x<0.4, and a channel layer made of an n-type doped In.sub.y Ga.sub.1-y As, wherein 0<y<0.4, having a thickness equal to or less than a critical thickness for lattice-matching with GaAs. Further, a doped AlGaAs layer is interposed between the AlGaAs buffer layer and the channel layer. The doped AlGaAs layer is made of Al.sub.x Ga.sub.1-x As, wherein 0<x<0.4, is doped with Si of a concentration of 5*10.sup.17 cm.sup.-3 or more, and has a thickness which is sufficient to provide a barrier against holes caused by a donor depletion region.

Abstract: The amplifier semiconductor element of this invention includes a field effect transistor of which a threshold voltage V.sub.th has a predetermined relationship with an operating voltage.