Abstract: An active matrix substrate includes a first TFT of a peripheral circuit and a second TFT arranged in each pixel, wherein: the first TFT is a top gate or double gate TFT that includes an upper gate electrode on a portion of a first oxide semiconductor layer with a gate insulating layer interposed therebetween; the second TFT is a bottom gate TFT that includes a second lower gate electrode arranged on the substrate side of a second oxide semiconductor layer with a lower insulating layer interposed therebetween and includes no gate electrode on the second oxide semiconductor layer; the second TFT including: an island-shaped insulator layer that is arranged on a portion of the second oxide semiconductor layer so as to overlap with at least a portion of the second lower gate electrode, as seen from a direction normal to the substrate; an upper insulating layer that is arranged on the second oxide semiconductor layer and the island-shaped insulator layer; and a source electrode that is arranged on the upper insulat

Abstract: A display panel includes an upper display substrate including a display area and a non-display area adjacent to the display area, the display area including first to third pixel areas and a light shielding area adjacent to the first to third pixel areas, a lower display substrate including first to third light emitting elements configured to emit light of a first color and overlapping the first to third pixel areas, respectively, and a plurality of spacers overlapping the display area and arranged between the upper display substrate and the lower display substrate.

Abstract: A high electron mobility transistor includes a channel layer, a barrier layer on the channel layer, source and drain contacts on the barrier layer, a gate contact between the source and drain contacts, and a multi-layer passivation structure on the upper surface of the barrier layer between the source contact and the drain contact. The multi-layer passivation structure includes a first passivation layer that comprises a charge dissipation material directly contacts the upper surface of the barrier layer and a second passivation layer comprising a different material than the first passivation layer that also directly contacts the upper surface of the barrier layer. In some embodiments, at least one recess may be formed in the upper surface of the barrier layer and the second passivation layer may be formed within the recesses.

Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate and between the source/drain regions. A first conductive structure is disposed on the gate dielectric. A ferroelectric structure is disposed on the first conductive structure. A second conductive structure is disposed on the ferroelectric structure, where both the first conductive structure and the second conductive structure have an overall electronegativity that is greater than or equal to an overall electronegativity of the ferroelectric structure.

Abstract: There are provided a memory device and a memory unit that make it possible to improve retention property of a resistance value in low-current writing. The memory device of the technology includes a first electrode, a memory layer, and a second electrode in order, in which the memory layer includes an ion source layer containing one or more transition metal elements selected from group 4, group 5, and group 6 in periodic table, one or more chalcogen elements selected from tellurium (Te), sulfur (S), and selenium (Se), and one or both of boron (B) and carbon (C), and a resistance change layer having resistance that is varied by voltage application to the first electrode and the second electrode.

Abstract: An organic light-emitting device and preparation method thereof, and a display apparatus are provided. The organic light-emitting device includes: a base substrate, an organic light-emitting element provided on the base substrate and an encapsulation structure for encapsulating the organic light-emitting element. The encapsulation structure includes a fluorescent material, and the organic light-emitting element emits a first light, and the fluorescent material is excited by the first light to generate a second light.

Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.

Abstract: To provide dummy openings having at least one of arrangement and shape determined depending on the shape of a non-effective region.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

Abstract: Concepts and technologies directed to optical networking with hybrid optical vortices are disclosed herein. Embodiments can include a system that is configured to perform operations for optical networking with hybrid optical vortices. The system can include a hybrid optical switch that can communicatively couple with another network device via one or more nanofiber communication paths. The operations can include receiving, from a first nanofiber communication path, a hybrid optical vortex that carries an internet protocol packet. The operations also can include decoupling the hybrid optical vortex to extract an optical vortex that encapsulates the internet protocol packet. The operations also can include switching the internet protocol packet to a subsequent communication path based on the optical vortex that encapsulates the internet protocol packet.

Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for blockchain-based hierarchical data storage. One of the methods includes: determining, based on a blockchain stored in a database that includes multiple levels of storage, a block number interval that includes one or more block numbers associated with data nodes to be migrated to a lower level of storage in response to the data nodes meeting a data migration condition, wherein each of the data nodes is included in a state Merkle tree and is associated with a block number of a block of the blockchain where the corresponding data node was last updated, and the lower level of storage corresponds to a storage media with lower storage cost.

Abstract: A non-volatile memory device and a method thereof that are capable of improving programming speed are introduced. The non-volatile memory device includes a memory array, a charge-pump circuit, a bias detection circuit and a memory controller is introduced. The memory array includes a plurality of memory cells; and a charge-pump circuit is configured to generate a charge-pump voltage. The bias detection circuit is coupled to the charge-pump circuit and is configured to determine whether a level of the charge-pump voltage is less than a first pre-determined threshold value. The memory controller is coupled to the bias detection circuit and is configured to pause a programming operation being performed on at least one of the plurality of memory cells when the bias detection circuit determines that the level of the charge-pump voltage is less than the first pre-determined threshold value.

Abstract: An EL device includes a display panel and an imaging element, and the display panel includes a panel substrate and an EL layer, and an imaging hole for guiding light from a subject to the imaging element is formed in the display area to straddle a plurality of scanning signal lines and a plurality of data signal lines when viewed from a direction perpendicular to a display area.

Abstract: A coplanar capacitor that incorporates teachings of the subject disclosure may include: a substrate; a voltage-tunable dielectric layer over the substrate; a plurality of bias lines over the voltage-tunable dielectric layer (wherein the bias lines are covered by an inter-level dielectric); a plurality of sidewall spacers (wherein each of the sidewall spacers is located adjacent one of the bias lines and each of the sidewall spacers spans between a respective portion of the voltage-tunable dielectric layer and a respective portion of the inter-level dielectric); and an electrode over the inter-level dielectric, and over portions of the voltage-tunable dielectric layer that are not covered by the plurality of bias lines and that are not covered by the sidewall spacers, wherein a plurality of gaps are disposed in the electrode. Other embodiments are disclosed.

Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.

Abstract: A power module includes a first power semiconductor device including a first electrode, a resin frame including first receiving portions, and a first leadframe. The first leadframe has a first main surface facing the first electrode and is electrically and mechanically connected to the first electrode. The first receiving portions face the first main surface of the first leadframe and receive part of the first leadframe. Thus, the power module has high reliability and can be miniaturized.

Abstract: A semiconductor package includes: a connection member having a first surface and a second surface opposing each other in a stacking direction of the semiconductor package and including an insulating member and a redistribution layer formed on the insulating member and having a redistribution via; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; a passivation layer disposed on the second surface of the connection member; UBM pads disposed on the passivation layer and overlapping the redistribution vias in the stacking direction; and UBM vias connecting the UBM pads to the redistribution layer through the passivation layer, not overlapping the redistribution vias with respect to the stacking direction, and having a non-circular cross section.

Abstract: An electronic device may include an edge touch screen including a main display region and an edge display region extending from the main display region each including one or more of red pixels, near infrared ray pixels, and sensor pixels for detecting light with different wavelengths; and a controller configured to, drive the edge touch screen in response to a touch input for the edge display region being maintained for a set time by instructing at least one selected red pixel of the red pixels and at least one selected near infrared ray pixel of the near infrared ray pixels corresponding to a position of the touch input to emit light, and measure biometrics based on light amounts of light of different wavelengths received from at least one selected sensor pixel of the sensor pixels corresponding to the position of the touch input.

Abstract: An optical connector assembly (OCA) includes a connector housing to maintain alignment between optical components housed within the OCA and photoelectric converters on an optoelectronic substrate (OES) assembly. The optical components include a ferrule and an optical cable. The ferrule is optically coupled to the optical cable. The OCA includes a ferrule holder to hold the ferrule within the OCA, and a spring located between the connector housing and the ferrule holder. The spring is to apply a separating force between the ferrule holder and the connector housing. The OCA includes a gasket coupled to the connector housing. The coupling of the connector housing to a socket compresses the gasket to provide a seal between the connector housing and the socket.

Abstract: Vehicle display device (10) including a display unit (50), installed in a cabin of a vehicle and having a display face oriented in a different direction from a direction of a driver (DR), configured to display an image depicting a surrounding area of the vehicle, and a mirror unit (55) installed in the cabin of the vehicle and configured to reflect some or all of an image area displayed on the display unit (50). A visible range of the surrounding area visible to the driver through an image of the display unit (50) reflected in the mirror unit (55) changes according to movement of a viewing position of the driver (DR) with respect to the mirror unit (55).

Abstract: A pixel circuit includes a first control sub-circuit, a second control sub-circuit, a current detection sub-circuit, a driving sub-circuit, and an energy storage sub-circuit. The first control sub-circuit is configured to transmit a voltage on a data voltage terminal to a first node under control of a voltage on a first scan signal terminal. The second control sub-circuit is configured to transmit the voltage on the first node to a control terminal of the driving sub-circuit under control of a voltage on a second scan signal terminal. The current detection sub-circuit is configured to output a detection current under control of the voltage on the first node and detect a current value of the detection current. The driving sub-circuit is configured to output a driving current under control of the voltage on the control terminal of the driving sub-circuit. The energy storage sub-circuit is configured to store electrical energy.

Abstract: A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.

Abstract: An optoelectronic semiconductor chip includes a semiconductor body including an n-conducting region, a p-conducting region and an active region between the n-conducting region and the p-conducting region; a first mirror containing a first metallic layer, and a p-metallization containing a second metallic layer, wherein during operation of the semiconductor chip, the first mirror is not at the same electrical potential as the p-conducting region, during operation of the semiconductor chip, the p-metallization is at the same electrical potential as the p-conducting region, and the first mirror has at least one opening through which the p-metallization is electrically conductively connected to the p-conducting region.

Abstract: An integrated-circuit buffer component includes a control-side data interface configurably coupled to first and second memory-side data interfaces via internal conductors, the first data interface having twice as many input/output (I/O) transceivers as the second data interface. In a first memory system configuration in which only the first data interface is coupled to a memory module, steering circuitry couples all the internal data conductors exclusively to the I/O transceivers of the first data interface. In a second memory system configuration in which the first and second data interfaces are coupled to respective memory modules, the steering circuitry couples a first half of the internal data conductors exclusively to the I/O transceivers of the second data interface while a second half of the internal data conductors remains exclusively coupled to half the I/O transceivers of the first data interface.

Abstract: A method of manufacturing a gallium nitride substrate, the method including forming a first buffer layer on a silicon substrate such that the first buffer layer has one or more holes therein; forming a second buffer layer on the first buffer layer such that the second buffer layer has one or more holes therein; and forming a GaN layer on the second buffer layer, wherein the one or more holes of the first buffer layer are filled by the second buffer layer.

Abstract: The present disclosure provides a DRAM cell structure. The DRAM cell structure includes a substrate, a gate structure disposed in the substrate, a source region and a drain region disposed in the substrate respectively at two sides of the gate structure, a landing pad disposed over the drain region, a plurality of carbon nanotubes disposed on the landing pad, a top electrode disposed over the plurality of carbon nanotubes, and a dielectric layer disposed between the top electrode and the plurality of carbon nanotubes.

Abstract: The present invention relates to a heat dissipation substrate, which is a composite substrate composed of two layers, and which is characterized in that a surface layer (first layer) (1) is configured of single crystal silicon and a handle substrate (second layer) (2) is configured of a material that has a higher thermal conductivity than the first layer. A heat dissipation substrate of the present invention has high heat dissipation properties.

Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) forming source regions by applying a first mask with a first and second mask layer and applying an n dopant, forming a well layer by removing such part of the first mask, which is arranged between the two source regions, and applying a p dopant, forming two channel regions by forming a third mask by performing an etching step, by which the first mask layer is farther removed at the openings than the second mask layer, and then removing the second mask layer, wherein the remaining first mask layer forms a third mask and applying a p dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers.

Abstract: A display device includes: a first pixel row including n pixels coupled to a first scan line; a second pixel row including m pixels coupled to a second scan line; a first power voltage source for supplying a first power voltage to the pixels of the first pixel row and the second pixel row through a first power voltage line; a current sensor for sensing a value of a line current flowing between the first power voltage line and a selected pixel row among the first pixel row and the second pixel row; and a timing controller for calculating a converted current value of the selected pixel row, wherein n is a natural number, and m is a natural number greater than n.

Abstract: A stack of layers providing an ohmic contact with the semiconductor, a lower metal layer of the stack is disposed in direct contact with the semiconductor; and a radiation absorption control layer disposed over the lower layer for controlling an amount of the radiant energy to be absorbed in the radiation absorption control layer during exposure of the stack to the radiation during a process used to alloy the stack with the semiconductor to form the ohmic contact.

Abstract: An optical receiver includes photodetectors each provided on a corresponding channel of multiple channels and configured to detect an optical signal at the corresponding channel, a delay adjuster circuit provided before the photodetectors and configured to adjust a delay time of an optical waveform of an incoming signal on at least one channel, and a processor that controls the delay time such that a change point of a first optical waveform of a first channel is away from a data decision timing of a second optical waveform of a second channel, using information acquired from an electrical signal produced after photo-detection.

Abstract: An integrated circuit includes a cell layer, a first metal layer, and a first conductive via. The cell layer includes first and second cells, each of which is configured to perform a circuit function. The first metal layer is above the cell layer and includes a first conductive feature that extends from the first cell into the second cell and that is configured to receive a supply voltage. A first conductive via interconnects the cell layer and the metal layer.

Abstract: Concepts and technologies directed to optical networking with hybrid optical vortices are disclosed herein. Embodiments can include a system that is configured to perform operations for optical networking with hybrid optical vortices. The system can include a hybrid optical switch that can communicatively couple with another network device via one or more nanofiber communication paths. The operations can include receiving, from a first nanofiber communication path, a hybrid optical vortex that carries an internet protocol packet. The operations also can include decoupling the hybrid optical vortex to extract an optical vortex that encapsulates the internet protocol packet. The operations also can include switching the internet protocol packet to a subsequent communication path based on the optical vortex that encapsulates the internet protocol packet.

Abstract: A coplanar capacitor that incorporates teachings of the subject disclosure may include: a substrate; a voltage-tunable dielectric layer over the substrate; a plurality of bias lines over the voltage-tunable dielectric layer (wherein the bias lines are covered by an inter-level dielectric); a plurality of sidewall spacers (wherein each of the sidewall spacers is located adjacent one of the bias lines and each of the sidewall spacers spans between a respective portion of the voltage-tunable dielectric layer and a respective portion of the inter-level dielectric); and an electrode over the inter-level dielectric, and over portions of the voltage-tunable dielectric layer that are not covered by the plurality of bias lines and that are not covered by the sidewall spacers, wherein a plurality of gaps are disposed in the electrode. Other embodiments are disclosed.

Abstract: A method for fabricating a stacked electronic device is provided. A first three-dimensional (3D) printing is performed to form a first insulating layer and a plurality of first redistribution layers (RDLs) on a first substrate. A second 3D printing is performed to form a second substrate and a plurality of through-substrate vias (TSVs) on the first insulating layer, in which the plurality of TSVs is electrically connected to the plurality of first RDLs. A third 3D printing is performed to form a second insulating layer and a plurality of second RDLs on the second substrate, in which the plurality of second RDLs is electrically connected to the plurality of TSVs. A plurality of contacts of a third substrate is bonded to the plurality of second RDLs, so that the substrate is mounted onto the second insulating layer. The disclosure also provides a stacked electronic device formed by such a method.

Abstract: A porous semiconductor layer contains anatase-type titanium oxide particles (A) which have an average primary particle size of 1 nm to 70 nm, and particles (B) obtained by coating surfaces of rutile-type titanium oxide particles, which have an average primary particle size of 100 nm to 1,000 nm, with an insulating material.

Abstract: A semiconductor device may include a substrate including a first Group IV semiconductor having a recess therein, an active layer comprising a Group III-V semiconductor within the recess, and a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor. The semiconductor device may further include an impurity and point defect blocking superlattice layer adjacent the buffer layer.

Abstract: A magnetic random-access memory (MRAM) device and a semiconductor package include a magnetic shielding layer that may suppress at least one of magnetic orientation errors and deterioration of magnetic tunnel junction (MTJ) structures due to external magnetic fields. A semiconductor device includes: a MRAM chip including a MRAM; and a magnetic shielding layer including an upper shielding layer and a via shielding layer. The upper shielding layer is on a top surface of the MRAM chip, and the via shielding layer extends from the upper shielding layer and passes through the MRAM chip.

Abstract: A detector for determining a faulty semiconductor component including a semiconductor component, a contact-via chain, which is situated laterally at a distance from the semiconductor component and which surrounds the semiconductor component in regions, a guard ring, which is situated laterally at a distance from the semiconductor component, and an evaluation unit, which is situated on the semiconductor component, wherein the evaluation unit is designed to apply an electrical voltage to the contact-via chain, in particular a permanent electrical voltage, to detect a resistance value of the contact-via chain and to produce an output signal when the resistance value of the contact-via chain exceeds a threshold value.

Abstract: There are provided a memory device and a memory unit that make it possible to improve retention property of a resistance value in low-current writing. The memory device of the technology includes a first electrode, a memory layer, and a second electrode in order, in which the memory layer includes an ion source layer containing one or more transition metal elements selected from group 4, group 5, and group 6 in periodic table, one or more chalcogen elements selected from tellurium (Te), sulfur (S), and selenium (Se), and one or both of boron (B) and carbon (C), and a resistance change layer having resistance that is varied by voltage application to the first electrode and the second electrode.

Abstract: A display device includes: a pixel electrode formed in a display area; an organic layer formed on the pixel electrode and including a light emitting layer; a counter electrode formed on the organic layer; a sealing layer formed on the counter electrode; a drive circuit formed in a picture-frame area as an area outside the display area and controlling light emission of the light emitting layer; a first test electrode formed in the picture-frame area and electrically separated from the drive circuit; and a picture-frame insulating layer formed on the first test electrode.

Abstract: To provide a voltage regulator capable of switching a voltage of an output terminal from an internal voltage to an external voltage while suppressing an increase in circuit scale. The voltage regulator includes a voltage output circuit configured to generate a constant internal voltage lower than an external voltage applied to an input terminal from the external voltage and supplying the constant internal voltage to an output terminal, a temperature sensing circuit configured to decrease an output voltage of an output node thereof according to a rise in temperature, an overheat detection circuit connected to the output node of the temperature sensing circuit and a test terminal, and a voltage detection circuit connected to the output node of the temperature sensing circuit and the test terminal.

Abstract: A transistor device is provided. The transistor device includes a substrate, a channel layer on the substrate, the channel layer including a GaN material, a barrier layer that is on the channel layer and that includes an AlGaN material, a drain electrode that is on the barrier layer in a drain region of the device, a source ohmic structure that is at least partially recessed into the barrier layer in a source region of the device, a source electrode that is on the source ohmic structure and a gate contact that is on the barrier layer and that is in a gate region of the device that is between the drain region and the source region.

Abstract: A LED package (10) for use in a lamp as well as a method for manufacturing such kind of a LED package (10) are disclosed, wherein the LED package (10) comprises at least one LED (16), an optical element (18) for guiding light emitted by the LED (16), and a cover (26) for covering, at least partially, electrical components (20, 22, 24) connectable to the LED (16). The cover (26) includes three protrusions (38) that form the highest points on the package. The protrusions (38) abut a surface in a housing for accurately positioning the LED package relative to a lens (52) in the housing. The LED package (10) may be spring-loaded. Side protrusions (28) of the cover (26) additionally help to position the package within the housing.

Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.

Abstract: A network management device retains path information of paths as a list of node identifying information to identify nodes, the path information including information on paths sharing a link regarding a relation in which one path shares a link with another path. According to the information on paths sharing a link, the network management device determines a path setup timing for a path to be the same for a group of one or more paths that do not share a same link with the path and determines a different path setup timing for a group of one or more paths that share a same link with the path than the timing for the group including the path, and executes path setup via communication devices existing on paths constituting each group of paths as per path setup timing determined for each group.

Abstract: A semiconductor device includes a trench-gate IGBT enabling the fine adjustment of a gate capacitance independent from cell performance. In a gate wiring lead-out region, a plurality of trenches is arranged spaced apart from each other in an X direction perpendicular to a Y direction. Each trench has a shape enclosed by a rectangular outer outline and a rectangular inner outline in plan view. A trench gate electrode is provided in each of the trenches so as to be electrically coupled to an extraction electrode. To obtain an adequate breakdown voltage between a collector and an emitter, the trenches are formed in a p-type floating region. An n?-type drift region is formed in a region located inside an inner outline of the trench in plan view, whereby a capacitance formed between the trench gate electrode and the n?-type drift region is used as the reverse transfer capacitance.

Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.

Abstract: A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer.