Abstract: Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop are disclosed. In one aspect, a standard cell circuit is provided that employs active devices that include corresponding gates disposed with a gate pitch. First and second voltage rails having a line width are disposed in a first metal layer. Employing the first and second voltage rails having substantially a same line width reduces the height of the standard cell circuit as compared to conventional standard cell circuits. Metal lines are disposed in a second metal layer with a metal pitch less than the gate pitch such that the number of metal lines exceeds the number of gates. Electrically coupling the first and second voltage rails to the metal shunts increases the conductive area of each voltage rail, which reduces a voltage drop across each voltage rail.

Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

Abstract: The present disclosure provides a method for manufacturing an LTPS TFT, including steps of: forming patterns of a p-Si layer and a protection layer on a base substrate, the protection layer covering the p-Si layer; performing a first ion injection operation so as to inject ions through the protection layer into the p-Si layer, thereby to form a heavily-drain-doped region; and performing an ashing operation and performing a second ion injection operation, to form a pattern of an LTPS active layer including a heavily-drain-doped region, a lightly-drain-doped region and an undoped region.

Abstract: In a MONOS memory, withstand voltage is increased between a control gate electrode over an ONO film having a charge accumulating part and a semiconductor substrate. When a silicon film is processed to form a control gate electrode, dry etching is performed for a relatively long time, thereby a recess is formed in a sidewall of the control gate electrode. Subsequently, the control gate electrode is subjected to dry oxidation treatment to form an insulating film on the sidewall of the control gate electrode including the recess, thereby an end of the bottom of the control gate electrode is separated from an end of the top of the ONO film.

Abstract: A method for manufacturing a flexible display panel includes: binding a flexible substrate with a supporting column matrix on a supporting plate, and fixing the flexible substrate with the supporting plate by a sealant in vacuum, wherein the sealant is disposed at an edge of the supporting column matrix, such that the supporting column matrix is surrounded in a sealed space formed by the sealant, the supporting plate and the flexible substrate; forming a flexible display panel on the flexible substrate; and cutting the supporting plate and the flexible display panel along the inner side of the sealant, such that the flexible display panel separating with the supporting plate. Thus, the flexible substrate can be separated from the supporting plate without damaging devices disposed on the flexible substrate.

Abstract: In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.

Abstract: An integrated high side gate driver structure for driving a power transistor. The structure includes a semiconductor substrate having a first polarity semiconductor material in which a first well diffusion including a second polarity semiconductor material is formed. An outer wall of the first well diffusion is abutted to the substrate. A second well diffusion, having first polarity semiconductor material, is arranged inside the first well diffusion such that an outer wall of the second well diffusion abuts an inner wall of the first well diffusion. The structure includes a gate driver having high side positive and negative supply voltage ports, and a driver input and output. The gate driver includes a transistor driver in the second well diffusion such that control and output terminals of the transistor driver are coupled to the driver input and output, respectively.

Abstract: A method of making a vertical transistor device includes forming a front gate and a back gate opposite a major surface of a substrate. The front gate and the back gate are symmetric and arranged on opposing sides of a channel between the front gate and the back gate. The channel extends from a drain to a source. The method includes disposing a mask to cover the front gate and removing the back gate. The method further includes replacing the back gate with a layer of insulator and another back gate stack. The another back gate stack only covers a junction between the channel and the source, and remaining portions of the back gate are the layer of insulator.

Abstract: A display device includes a first substrate having an active area, a circuit area extending outwardly from the active area, and a cell seal area extending outwardly from the circuit area, a second substrate covering the first substrate, a sealing part between the first substrate and the second substrate, the sealing part covering at least a portion of the circuit area, a wiring part in the circuit area of the first substrate and electrically connected to elements in the active area of the first substrate, the wiring part including at least one level-difference compensation part, and a stepped part between the sealing part and at least a portion of the wiring part, the at least one level-difference compensation part of the wiring part being adjacent to the stepped part.

Abstract: Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.

Abstract: Exemplary systems, methods and computer-accessible mediums can be provided that can, for example, determine a camouflaging location(s) of the logic gate(s) using a fault analysis procedure, and can camouflage the logic gate(s) at the location(s) based on the determination. The camouflaging procedure can be performed by replacing the logic gate(s) at the camouflaging location(s) with a further camouflaged gate, which can have a dummy contact(s) or a vias.

Abstract: A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.

Abstract: In an aspect of the disclosure, a MOS device for using bulk cross-coupled thin-oxide decoupling capacitor is provided. The MOS device may include a pMOS transistor and an nMOS transistor. The MOS device may include a first set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The first set of transistor body connections may couple a first voltage source to the pMOS transistor body. The first set of transistor body connections may further couple a second voltage source to the nMOS transistor body. The MOS device may include a second set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The second set of transistor body connections may couple the nMOS transistor gate to the pMOS transistor body. The second set of transistor body connections may further couple the pMOS transistor gate to the nMOS transistor body.

Abstract: Provided is an organic light-emitting display device. An organic light-emitting display device (OLED) includes: a substrate including at least three pixel regions arranged in a horizontal direction, a first electrode in each pixel region on the substrate, a bank surrounding each pixel region, and a power line in the horizontal portion at a lower side of each pixel region on the substrate, the power line being configured to supply a driving voltage to each pixel region.

Abstract: Provided is a dynamic random access memory. A plurality of isolation structures is disposed in a substrate to define a plurality of active regions arranged along a first direction. The substrate has a trench extended along the first direction and passing through the plurality of isolation structures and the plurality of active regions. A buried word line is disposed in the trench. A plurality of gate dielectric layers is disposed in the trench of the plurality of active regions to surround and cover the buried word line. A cap layer covers the buried word line. The height of the top surface of the second side of the buried word line is lower than the height of the top surface of the first side of the buried word line passing through the plurality of active regions and the plurality of isolation structures.

Abstract: A method of fabricating a CMOS logic device with SWCNTs includes forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate; forming a plurality of contacts on the substrate; and depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one NMOS transistor and at least one PMOS transistor. Each of the NMOS and PMOS transistors has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively. The gate of each PMOS transistor and the gate of each NMOS transistor are configured to alternatively receive at least one input voltage. At least one of the drain of the PMOS transistor and the drain of the NMOS transistor is configured to output an output voltage.

Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.

Abstract: Disclosed herein is a semiconductor integrated circuit device which includes a standard cell with a plurality of fins extending in a first direction and arranged in a second direction that is perpendicular to the first direction. An active fin of the fins forms part of an active transistor. A dummy fin of the fins is disposed between the active fin and an end of the standard cell.

Abstract: An integrated circuit includes a field programmable gate array including: (i) a plurality of memory cells (e.g., static memory cells) to store data, wherein each memory cell includes a first output, (ii) a multiplexer including inputs, an output and input selects, (iii) a plurality of poly-silicon conductors, each poly-silicon conductor is disposed in the substrate and connected to the first output of an associated memory cell, (iv) poly-silicon extensions, each poly-silicon extension is (a) connected to an associated poly-silicon conductor and (b) coupled to an associated input select of the multiplexer, wherein the poly-silicon extensions are disposed in the substrate and at least partially under a metal conductor, disposed above the substrate, in the field programmable gate array.

Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

Abstract: A printing element substrate includes a plurality of printing elements, a first transistor forming an electrical pathway common to the plurality of printing elements, and a plurality of second transistors for driving the plurality of printing elements independently of each other. An electrical pathway is formed between a first power node and a second power node in the order of the first transistor, one of the plurality of printing elements, and one of the plurality of second transistors. The electrical pathway connecting each of the plurality of printing elements and the first transistor includes a plurality of electrical paths.

Abstract: A layer of a mask material is deposited on a substrate. A beam of energy is scanned across the mask material in a rasterized linear pattern and in accordance with a scan pitch that is based on a pitch of conductive structure segments to be formed on the substrate. The beam of energy is defined to transform the mask material upon which the beam of energy is incident into a removable state. During scanning the beam of energy across the mask material, the beam of energy is turned on at locations where a conductive structure is to be formed on the substrate, and the beam of energy is turned off at locations where a conductive structure is not to be formed on the substrate.

Abstract: A semiconductor device and a method for fabricating the device. The method includes: forming a STI in a substrate having a nFET and a pFET region; depositing a high-k layer and a TiN layer; depositing a polycrystalline silicon layer; forming a block level litho layer; removing a portion of the polycrystalline silicon layer; removing the block level litho layer; forming a first protective layer; depositing a fill layer above the pFET region; removing the first protective layer; cutting the TiN layer and the high-k layer to expose a portion of the STI; depositing a second protective layer on the STI; removing the fill layer; removing the TiN layer above the pFET region; treating the high-k layer with a work function tuning process; removing the polycrystalline silicon layer and TiN layer; and depositing a metal layer on the high-k layer and the second protective layer.

Abstract: A layout of a semiconductor device includes a first active area, a second active area, plural gates, a first conductive layout and plural plugs. The first and the second active areas are disposed on a substrate and surrounded by a shallow trench isolation (STI). The plural gates are parallel with one another and cross the first and the second active areas. The first conductive layer covers the plural gates, and the plural gates are electrically connected to each other through the first conductive layer. The plural plugs are disposed on the first conductive layer to electrically connect the plural gates.

Abstract: A die interconnect system having a plurality of connection pads, a heat generating element thermally isolated from the die, one or more leads extending from the die to the heat generating element, each lead having a metal core with a core diameter, a dielectric layer surrounding the metal core with a dielectric thickness, and an outer metal layer attached to ground, wherein one or more leads are exposed to ambient conditions and/or are convectively or contact cooled for at least a portion of their length to minimize heat transfer from the heat generating element to the die.

Abstract: A computer implemented method and a computer program for generating a layout of a circuit block of an integrated circuit are provided. Input data is received identifying a plurality of circuit elements and interconnections required to implement the circuit block, and the method also has access to a cell library providing a plurality of standard cells, where each standard cell defines a corresponding circuit element using transistors, the transistors comprising n-type transistors and p-type transistors. A plurality of rows are formed within which to place standard cells from the cell library in order to implement the circuit block, the plurality of rows including at least one body biased row in which a body bias is to be applied in respect of either the n-type transistors or the p-type transistors provided by the standard cells placed in that body biased row.

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

Abstract: An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of functional cells between the plurality of power rails or between the plurality of ground rails or both, and a jumper connection between the vertically separated power rails or ground rails, the jumper connection within a vertically aligned gap among the plurality of functional cells. A method of mitigating IR drop and electromigration affects in an integrated circuit includes forming a plurality of power rails or ground rails, each of the power rails or ground rails on separate vertical levels of a plane of an integrated circuit layout and connecting with a jumper connection at least two power rails or two ground rails, the jumper connection within a vertically aligned gap among cells of the integrated circuit.

Abstract: Disclosed are temperature-aware integrated circuit (IC) design methods and systems, which establish a customized power delivery network (PDN) for an IC early in the design process in order to generate, in a timely manner, a final IC design layout that can be used to manufacture IC chips that will exhibit minimal hotspots. Specifically, prior to placement of library elements, an initial PDN is established and divided into sections. The library elements are placed. Then, potential hotspots associated with any of the sections are identified and a customized PDN for the IC is established to eliminate the hotspots. That is, for each section, a total power consumption amount is determined. When the total power consumption amount is greater than the threshold, a hotspot is indicated and the section is customized to eliminate the hotspot. Also disclosed is a resulting IC chip structure.

Abstract: An RF communications device may include a circuit board having a dielectric layer and conductive traces, one of the conductive traces defining a transmission line. The RF communications device may also include an RF transmitter carried by the circuit board and coupled to the transmission line, and RF switching circuits, each RF switching circuit including a substrate having a tapered proximal end coupled to the transmission line, and a distal end extending outwardly on the convex side of the transmission line. Each RF switching circuit may include a series diode, and a shunt diode coupled to the series diode, the series diode extending from the tapered proximal end and across an interior of the substrate.

Abstract: In some embodiments, a microelectromechanical system may include a semiconductor substrate, a plurality of wiring layers, and a stop. The plurality of wiring layers may be coupled to a first surface of the semiconductor substrate. The stop may be coupled to the plurality of wiring layers. In some embodiments, at least a portion of the plurality of wiring layers between the stop and the first surface of the substrate comprises an insulating material. In some embodiments, at least the portion excludes wiring within. In some embodiments, a volume of the portion may be determined by a use of the microelectromechanical system. In some embodiments, the portion may inhibit, during use, electrical failures adjacent to the stop.

Abstract: An integrated circuit includes a field programmable gate array including: (i) a plurality of memory cells (e.g., static memory cells) to store data, wherein each memory cell includes a first output, (ii) a multiplexer including inputs, an output and input selects, (iii) a plurality of poly-silicon conductors, each poly-silicon conductor is disposed in the substrate and connected to the first output of an associated memory cell, (iv) poly-silicon extensions, each poly-silicon extension is (a) connected to an associated poly-silicon conductor and (b) coupled to an associated input select of the multiplexer, wherein the poly-silicon extensions are disposed in the substrate and at least partially under a metal conductor in the field programmable gate array.

Abstract: According to an exemplary implementation, a semiconductor package includes a multi-phase power inverter having power switches and situated on a leadframe of the semiconductor package. The semiconductor package further includes a temperature sensor situated on the leadframe, where the temperature sensor is configured to generate a sensed temperature of the power switches. The semiconductor package also includes a driver circuit configured to drive the power switches of the multi-phase power inverter responsive to the sensed temperature. The temperature sensor can be on a common IC with the driver circuit. Furthermore, the semiconductor package can include an over-temperature protection circuit configured to provide over-temperature protection to the multi-phase power inverter using the sensed temperature.

Abstract: A semiconductor device includes a substrate having a fin structure, the fin structure having a height in a substantially perpendicular direction to the substrate, and having consecutive upper and lower portions along the height, the lower portion being closer to the substrate than the upper portion. The semiconductor device further includes a gate structure wrapping around a portion of the fin structure, the gate structure having a gate dielectric layer disposed around the fin structure, and a gate electrode layer disposed over the gate dielectric layer. The gate electrode layer includes a first gate metal layer formed along both sides of the lower portion of the fin structure, the first gate metal layer having a first workfunction, and a second gate metal layer formed disposed over the first gate metal layer and wrapped around the upper portion of the fin structure, the second gate metal layer having a second workfunction. The first and the second workfunctions are different.

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract: An integrated circuit 2 is formed with standard-cell power conductors 14 which are overlaid by power grid conductors 20. The power grid conductors are offset in a direction transverse to the longitudinal axis of the power grid conductors relative to their underlying standard-cell power conductor. This has the effect of increasing the conductor spacing possible to one side of the power grid conductor. Accordingly, a wider than minimum width power grid conductor may be provided which blocks only one of its adjacent track positions from being used by a routing conductor 22.

Abstract: In a particular aspect, an integrated circuit includes a first gate structure coupled to a first fin field effect transistor (FinFET) device. The integrated circuit includes a second gate structure coupled to a second FinFET device. The first gate structure and the second gate structure are separated by a dielectric region. The integrated circuit further includes a metal contact having a first surface that is in contact with the dielectric region, the first gate structure, and the second gate structure.

Abstract: A transistor device is provided that includes a substrate, a first channel region formed in a first portion of the substrate and being doped with a dopant of a first type of conductivity, a second channel region formed in a second portion of the substrate and being doped with a dopant of a second type of conductivity, a gate insulating layer formed on the first channel region and on the second channel region, a dielectric capping layer formed on the gate insulating layer, a first gate region formed on the dielectric capping layer over the first channel region, and a second gate region formed on the dielectric capping layer over the second channel region, wherein the first gate region and the second gate region are made of the same material, and wherein one of the first gate region and the second gate region comprises an ion implantation.

Abstract: The disclosure provides a standard cell. The standard cell includes a first PMOS transistor and a second PMOS transistor whose gate terminal respectively receives a first input and a second input. A drain terminal of each of the first PMOS transistor and the second PMOS transistor is coupled to a first node. The standard cell further includes a first NMOS transistor and a third NMOS transistor whose gate terminal respectively receive the first input and the second input. A drain terminal of each of the first NMOS transistor and the third NMOS transistor is coupled to the first node. The first NMOS transistor is coupled to a second NMOS transistor, and the third NMOS transistor is coupled to a fourth NMOS transistor. A gate terminal of the second NMOS transistor and the fourth NMOS transistor respectively receives the second input and the first input.

Abstract: A semiconductor device for reducing an instantaneous voltage drop is provided. The semiconductor device includes a first power line configured to provide a first power supply voltage and a first power transistor connected between the first power line and a first logic transistor. The first power transistor includes a first source or drain connected to the first power line, a gate receiving a power gating control signal, and a second source or drain connected to a first source or drain of the first logic transistor using a shared semiconductor junction.

Abstract: In one embodiment, a complementary metal-oxide-semiconductor (CMOS) logic device formed with single-walled carbon nanotubes (SWCNTs) includes: at least one p-type metal-oxide-semiconductor (PMOS) thin-film transistor (TFT) formed with the SWCNTs, and at least one n-type metal-oxide-semiconductor (NMOS) TFT formed with the SWCNTs, where each of the at least one PMOS TFT and the at least one NMOS TFT has a gate, a source and a drain. The gate of each of the at least one PMOS TFT and the gate of each of the at least one NMOS TFT is configured to alternatively receive at least one input voltage, and respectively includes a local metallic gate structure formed of a metal. At least one of the drain of the at least one PMOS TFT and the drain of the at least one NMOS TFT is configured to output an output voltage VOUT.

Abstract: A semiconductor device includes a diffusion area, a gate structure coupled to the diffusion area, and a dummy gate structure coupled to the diffusion area. The gate structure extends a first distance beyond the diffusion area, and the dummy gate structure extends a second distance beyond the diffusion area.

Abstract: A capacitive micromachined ultrasonic transducer (CMUT) is provided that includes a substrate, a bottom conductive layer disposed on a bottom surface of the substrate, a cavity disposed into a top surface of the substrate, a nonconductive layer disposed on the substrate top surface and on the cavity, a CMUT plate disposed on the nonconductive layer and across the cavity, a top conductive layer disposed on a top surface of the CMUT plate, a pressure control via that spans from the cavity to an ambient environment, and an active pressure controller connected to the pressure control via, wherein the active pressure controller is capable of actively varying a pressure differential across the CMUT plate.

Abstract: Disclosed are a method of growing a high-quality single layer graphene by using a Cu/Ni multi-layer metallic catalyst, and a graphene device using the same. The method controls and grows a high-quality single layer graphene by using the Cu/Ni multilayer metallic catalyst, in which a thickness of a nickel lower layer is fixed and a thickness of a copper upper layer is changed in a case where a graphene is grown by a CVD method. According to the method, it is possible to obtain a high-quality single layer graphene, and improve performance of a graphene application device by utilizing the high-quality single layer graphene and thus highly contribute to industrialization of the graphene application device.

Abstract: A method includes forming a plurality of fins above a substrate. A first mask layer is formed above a first subset of the fins. First portions of the fins in the first subset exposed by a first opening in the first mask layer are removed to define, for each of the fins, a first fin segment and a second fin segment, each having a cut end surface. A first liner layer is formed on at least the cut end surface of the first fin segment for each of the fins in the first subset. A second mask layer having a second opening is formed above a second subset of the plurality of fins. An etching process removes second portions of the second subset of fins exposed by the second opening. The first liner layer protects the cut end surface of at least the first fin segment during the removing.

Abstract: An integrated circuit includes a plurality of logic tiles, wherein each logic tile includes a plurality of edges and, is configurable to communicate, during operation, with at least one adjacent logic tile, and wherein a first logic tile includes: (i) a plurality of static memory cells to store data, wherein each memory cell includes a first output, (ii) a multiplexer including inputs, an output and input selects, (iii) a plurality of poly-silicon conductors, each poly-silicon conductor is disposed in the substrate and connected to the first output of an associated memory cell, (iv) poly-silicon extensions, each poly-silicon extension is (a) connected to an associated poly-silicon conductor and (b) coupled to an associated input select of the multiplexer, wherein the poly-silicon extensions are disposed in the substrate and at least partially under a metal conductor in the first logic tile.

Abstract: A semiconductor device includes a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.

Abstract: A semiconductor device includes at least one gate electrode on a substrate structure, at least one drain region doped with impurities of a first conductivity type, a first well region doped with impurities of the first conductivity type under the at least one drain region, and at least one source region doped with impurities of the first conductivity type. The device also includes a first barrier impurity region and a second barrier impurity region. The first barrier impurity region is doped with impurities of the first conductivity type and electrically insulating upper and lower portions of the substrate structure from each other. The second barrier impurity region is doped with impurities of a second conductivity type. A portion of the second barrier impurity region has an uneven shape and overlaps the at least one drain region.

Abstract: A liquid discharge substrate includes a plurality of discharge elements disposed on a substrate, a first transistor electrically connected to the plurality of discharge elements, and a plurality of second transistors. The first transistor is disposed between the plurality of discharge elements and the plurality of second transistors.