Abstract: A semiconductor design apparatus computes a consumption current in a macro cell region in the semiconductor device. A first region is defined to be a first shape and size on an upper surface on at least one end of a one-side end portion of the macro cell region based on the consumption current in the macro cell region and an allowable current per via that connects a power supply layer and the macro cell region to each other. A second region is defined as a second shape and size on the upper surface of the macro cell region based on the first region. The apparatus determines an arrangement of the macro cell region and the power supply layer based on the second region and determines the arrangement of vias in the second region based on the arrangement of the macro cell region and the power supply layer.

Abstract: A semiconductor device includes a semiconductor die, an insulative layer, a conductive feature and a shield. The insulative layer surrounds the semiconductor die, and the insulative layer has a first surface and a second surface opposite to each other. The conductive feature is extended from the first surface to be proximal to the second surface of the insulative layer, and the conductive feature has a first end exposed by the first surface of the insulative layer. The shield covers the first surface of the insulative layer and is grounded through the first end of the conductive feature exposed by the first surface of the insulative layer.

Abstract: A system and method for creating a layout for a vertical gate all around standard cell are described. Metal gate is placed all around two vertical nanowire sheets formed on a silicon substrate. A gate contact is formed on the metal gate between the two vertical nanowire sheets. Gate extension metal (GEM) is placed above the metal gate at least on the gate contact. A via for a gate is formed at a location on the GEM where a local interconnect layer is available to be used for routing a gate connection. Local metal layers are placed for connecting local routes and power connections.

Abstract: A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.

Abstract: A semiconductor memory device includes a peripheral circuit including first and second circuit blocks that are respectively disposed in second and third regions adjacent to each other in a first direction with a first region interposed therebetween, first power lines disposed in a first metal layer and connected to the first unit circuit block, second power lines disposed in the first metal layer and connected to the second unit circuit block, and bridge power lines disposed in a second metal layer in the first region and extending in a second direction intersecting with the first direction. The first power lines extend from the second region to the first region and are meshed with the bridge power lines. The second power lines extend from the third region to the first region and are meshed the bridge power lines.

Abstract: According to an aspect, a semiconductor device and an IO-cell include a plurality of first power supply lines and a plurality of second power supply lines alternately arranged in a first direction, the first and second power supply lines each being supplied with electric power in which the voltage of the electric power supplied to the first power supply is different from that supplied to the second power supply, and a third power supply line formed in a wiring layer different from a wiring layer in which the first and second power supply lines are arranged, the third power supply line being connected to adjacent first power supply lines among the plurality of first power supply lines through a via, in which all of the first, second and third power supply lines are formed so as to extend in a second direction perpendicular to the first direction.

Abstract: A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium.

Abstract: A semiconductor device including a circuit that has a reduced area is provided. Alternatively, a semiconductor device including a circuit that can have a smaller power supply voltage variation is provided. The semiconductor device includes a first transistor, a second transistor, a first power supply wiring, and a second power supply wiring. The first transistor and the second transistor are stacked. The first power supply wiring and the second power supply wiring are stacked. The second power supply wiring and the first power supply wiring at least partly overlap with each other. The second power supply wiring and the first power supply wiring are substantially parallel to each other. A source electrode of the first transistor is electrically connected to the first power supply wiring. A source electrode of the second transistor is electrically connected to the second power supply wiring. The second transistor is an n-channel transistor, and a channel formation region is formed using an oxide semiconductor.

Abstract: A semiconductor integrated circuit comprising: a first macro cell including a first power line in a first wiring layer; a second macro cell adjacent to the first macro cell, the second macro cell including a second power line in the first wiring layer; a first connection part in the first wiring layer, the first connection part electrically connecting the first power line with the second power line; and a third power line in a second wiring layer different from the first wiring layer, the third power line electrically connected to the first power line; wherein the second power line is electrically connected to the third power line through the first connection part.

Abstract: The present invention provides an integrated circuit. The integrated circuit comprises: a plurality of core power sources; and a plurality of core power domains, coupled to the core power sources, respectively; wherein the core power domains are overlapped with each other.

Abstract: Disclosed herein is a configuration for ensuring sufficient power supply ability and ESD protection capability for I/O cells in a semiconductor integrated circuit device, without increasing its circuit area. In two I/O cell rows, a pair of I/O cells for supplying a power supply potential or ground potential are connected together via a common power supply interconnect. The I/O cells are arranged so as to overlap with each other in a first direction in which the I/O cells are arranged. The common power supply interconnect extends in a second direction perpendicular to the first direction, and is connected to first pads that are located closest in the first direction to the common power supply interconnect.

Abstract: One of objects is to provide a semiconductor device with stable electric characteristics, in which an oxide semiconductor is used. The semiconductor device includes a thin film transistor including an oxide semiconductor layer, and a silicon oxide layer over the thin film transistor. The thin film transistor includes a gate electrode layer, a gate insulating layer whose thickness is equal to or larger than 100 nm and equal to or smaller than 350 nm, the oxide semiconductor layer, a source electrode layer and a drain electrode layer. In the thin film transistor, the difference of the threshold voltage value is 1 V or less between before and after performance of a measurement in which the voltage of 30 V or ?30 V is applied to the gate electrode layer at a temperature of 85° C. for 12 hours.

Abstract: A switch cell structure includes a switch cell of a first type, which includes a master switch cell and a plurality of slave switch cells. The master switch cell includes a buffer having an input and an output and a transistor having a gate coupled to the output of the buffer. The slave switch cell includes a respective signal line having an input and output and a transistor having a gate coupled to the signal line, the signal lines of the slave switch cells are coupled to one another, with the output of one coupled to the input of another of the signal lines. The output of the buffer of the master switch cell is coupled to an input of one of the signal lines of slave switch cells to drive the plurality of slave switch cells.

Abstract: A method includes the operation below. Groups, indicating layout patterns of interconnection layers, are assigned to a circuit, to determine layout constraints of the circuit. Layout patterns are extracted from a layout design for the circuit. The layout patterns are compared with the layout constraints. Data, indicating the layout design, for fabrication of the circuit are generated in a condition that the layout patterns meet the layout constraints.

Abstract: A method for structure design including detecting, by a processor, a tip-to-tip (T2T) structure design violation for a metal layer above (Ma) a via (Vx) at a tip of the Ma for a design file layout for the structure. Upon detection of the T2T structure design violation, retargeting, by the processor, of the Vx based on adjusting of both the Ma and a metal layer (Mb) below the Vx that connects the Ma through the Vx for the design file layout of the structure to improve performance of the structure based on fixing metal tip or metal ending across cell boundaries.

Abstract: The present disclosure provides techniques for creating a symmetrical ball grid array pattern for an integrated circuit package. The ball grid array includes a symmetrical pattern of circuit connection points, wherein the symmetrical pattern is derived from a base hexagonal pattern that is repeated in at least one or more sections of the ball grid array.

Abstract: An integrated circuit includes a gate electrode and spacers along sidewalls of the gate electrode. The integrated circuit further includes a source/drain (S/D) region adjacent to the gate electrode. The S/D region includes a diffusion barrier structure at least partially in a recess of the substrate. The diffusion barrier structure includes an epitaxial layer having a first region and a second region. The first region is thinner than the second region, and the first region is misaligned with respect to the sidewalls of the gate electrode. The S/D region includes a doped silicon-containing structure over the diffusion barrier structure. The first region of the diffusion barrier structure is configured to partially prevent dopants of the doped silicon-containing structure from diffusing into the substrate. The second region of the diffusion barrier structure is configured to substantially completely prevent the dopants of the doped silicon-containing structure from diffusing into the substrate.

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a logic region having a logic device disposed over a substrate and including a first metal gate disposed over a first high-k gate dielectric layer and an embedded memory region disposed adjacent to the logic region. The embedded memory region has a split gate flash memory cell including a select gate and a control gate. The control gate or the select gate is a metal gate separated from the substrate by a second high-k gate dielectric layer. By having HKMG structures in both the logic region and the memory region, IC performance is improved and further scaling becomes possible in emerging technology nodes.

Abstract: A method includes providing a starting interconnect structure for semiconductor device(s), the starting interconnect structure including a first metallization layer with a first power rail. The method further includes forming a second metallization layer over the first metallization layer with a second power rail, and directly electrically connecting the first power rail and the second power rail, the directly electrically connecting including forming metal-filled vias between the first power rail and the second power rail. The method further includes forming additional metallization layer(s) over the second metallization layer with additional power rail(s), and directly electrically connecting each of the additional power rail(s) to a power rail of a metallization layer directly below.

Abstract: The present disclosure relates to an integrated chip having a dual power rail structure. In some embodiments, the integrated chip has a first metal interconnect layer having a lower metal wire extending in a first direction. A second metal interconnect layer has a plurality of connection pins coupled to the lower metal wire by way of a first via layer and extending over the lower metal wire in a second direction perpendicular to the first direction. A third metal interconnect layer has an upper metal wire extending over the lower metal wire and the connection pins in the first direction. The upper metal wire is coupled to the connection pins by way of a second via layer arranged over the first via layer. Connecting the connection pins to the lower and upper metal wires reduces current density in connections to the connection pins, thereby reducing electromigration and/or IR issues.

Abstract: The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.

Abstract: A semiconductor device includes: a virtual power line extended in a first direction; an n-well extended in the first direction, wherein the virtual power line and the n-well are disposed in a row; a first power gate switch cell disposed in the n-well; a second power gate switch cell disposed in the n-well, wherein the first and second power gate switch cells are first type cells; and a third power gate switch cell disposed in the n-well between the first and second power gate switch cells, wherein the third power gate switch cell is a second type cell different from the first type cells.

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.

Abstract: A semiconductor device includes a substrate, a first transistor gated by an inverted voltage level of a first input signal to pull up a first node, a second transistor gated by a voltage level of a second input signal to pull down the first node, a third transistor gated by an inverted voltage level of the second input signal to pull up the first node, a fourth transistor gated by a voltage level of the first input signal to pull down the first node, a fifth transistor gated by the voltage level of the second input signal to pull down a second node, a sixth transistor gated by the inverted voltage level of the first input signal to pull up the second node, a seventh transistor gated by the voltage level of the first input signal to pull down the second node, and an eighth transistor gated by the inverted voltage level of the second input signal to pull up the second node.

Abstract: A solid-state imaging device includes: a first electrode formed above a semiconductor substrate; a photoelectric conversion film formed on the first electrode and for converting light into signal charges; a second electrode formed on the photoelectric conversion film; a charge accumulation region electrically connected to the first electrode and for accumulating the signal charges converted from the light by the photoelectric conversion film; a reset gate electrode for resetting the charge accumulation region; an amplification transistor for amplifying the signal charges accumulated in the charge accumulation region; and a contact plug in direct contact with the charge accumulation region, comprising a semiconductor material, and for electrically connecting to each other the first electrode and the charge accumulation region.

Abstract: A system and method of layout design for an integrated circuit and integrated circuit, the method includes positioning all conductive traces of a first mask pattern, in a first direction, wherein the conductive traces of the first mask pattern are in a first conductive layer. The method also includes positioning all conductive traces of a second mask pattern, in the first direction, wherein the conductive traces of the second mask pattern are in the first conductive layer, and the second mask pattern is offset from the first mask pattern in a second direction different from the first direction.

Abstract: An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as gates and contacts, which have alternating line and space configurations in SRAM cells. Strap rows of the SRAM containing well ties and/or substrate taps which have SRAM cells on two opposite sides are configured so that the alternating line and space configurations are continuous across the regions containing the well ties and substrate taps.

Abstract: Approaches herein provide model-based generation of dummy features used during processing of a semiconductor device (e.g., during a self-aligned via process). Specifically, at least one approach includes: generating a set of dummy features in proximity to a set of target features in a mask layout, evaluating a proximity of the set of dummy features to a metal layer of the semiconductor device, and removing a portion of the set of dummy features that is present within an established critical distance between the set of dummy features and the metal layer. Target design printability is further enhanced during photolithography by performing one or more of the following: merging two or more dummy features of the set of dummy features, and increasing a distance between adjacent dummy features of the set of dummy features by modifying a geometry of one or more of the set of dummy features.

Abstract: A method of includes determining a first set of width bias values of an i-th set of layout patterns of an original layout according a first type width variation. The original layout has N sets of layout patterns corresponding to N masks, where the i-th set of layout patterns has an i-th mask assignment corresponding to an i-th mask of the N masks. The order index i is an integer from 1 to N, and N is an integer and greater than 1. A second set of width bias values of the i-th set of layout patterns of the original layout is determined according to a second type width variation. The modified layout is generated based on the first and second sets of width bias values of the i-th set of layout patterns.

Abstract: A device is disclosed that includes a first transistor, a second transistor, and a first PODE device. The second transistor is electrically coupled to the first transistor. The first PODE device is adjacent to a drain/source region of the second transistor. A control end of the first PODE device is electrically coupled to a drain/source end of the second transistor.

Abstract: Embodiments of the present invention provide a method for self-aligned metal cuts in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. Spacers are formed on each Mx+1 sacrificial line. The gap between the spacers is used to determine the location and thickness of cuts to the Mx metal lines. This ensures that the Mx metal line cuts do not encroach on vias that interconnect the Mx and Mx+1 levels. It also allows for reduced limits in terms of via enclosure rules, which enables increased circuit density.

Abstract: Systems and methods are directed to contacts for an infrared detector. For example, an infrared imaging device includes a substrate having a first metal layer and an infrared detector array coupled to the substrate via a plurality of contacts. Each contact includes for an embodiment a plurality of metal studs each having a first end and a second end and each disposed between the first metal layer and a second metal layer, wherein the first end of each metal stud is disposed on a portion of the first metal layer that is at least partially on the surface of the substrate.

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.

Abstract: Disclosed is a chip substrate. The chip substrate includes: conductive portions laminated in one direction to constitute the chip substrate; insulation portions alternately laminated with the conductive portions to electrically isolate the conductive portions; a cavity formed at a predetermined depth in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate; and a groove portion disposed outside the cavity in a spaced-apart relationship with the cavity and formed at a predetermined depth in a recessed shape. According to the present invention, an adhesive agent is applied in a groove portion formed in advance. It is therefore possible to prevent the adhesive agent from being exposed to the light emitted from optical elements and to prevent the adhesive agent from being denatured. This makes it possible to enhance the reliability of lens bonding. Furthermore, there is no need to use an expensive resistant adhesive agent.

Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device comprising an asymmetrically placed metal formation. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first metal formation is placed asymmetrically about a first cell boundary of the functional cell for providing additional space for routing.

Abstract: Integrated circuits and methods for manufacturing the same are provided. A method for producing an integrated circuit includes forming a first active dummy gate, a second active dummy gate, and an inactive gate overlying a substrate. The first active dummy gate is replaced with a first metal gate, where replacing the first active dummy gate includes planarizing the first metal gate, the second active dummy gate, and the inactive gate. The second active dummy gate is replaced with a second replacement metal after the first active dummy gate was replaced, where the inactive gate remains overlying the substrate.

Abstract: A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium.

Abstract: A method of forming a manufacture includes forming a trench in a doped layer; and forming a gate dielectric layer along sidewalls of an upper portion of the trench. The method further includes forming a first conductive feature along sidewalls of the gate dielectric layer, wherein the first conductive feature has a first depth in the trench. The method further includes forming an insulating layer covering the first conductive feature and the first insulating layer. The method further includes forming a second conductive feature along sidewalls of the second insulating layer, wherein the second conductive feature has a second depth in the trench different from the first depth.

Abstract: A flexible display device includes a flexible display panel including: a plastic film; a pixel circuit on the plastic film; a light emitting element; and an inorganic layer. Openings are in the inorganic layer along a cutting line for cutting the flexible display panel.

Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.

Abstract: Power gating logic detects a transition of a component of a processing device into an idle state. In response to detecting the transition, the entry/exit power gating logic selectively implements one or more entry prediction techniques for power gating the component based on estimates of reliability of the entry prediction techniques. The entry/exit power gating logic also selectively implements one or more exit prediction techniques for exiting the power gated state based on estimates of reliability of the exit prediction techniques.

Abstract: A pixel circuit includes a switching transistor whose conduction is controlled by a drive signal supplied to the control terminal, a drive wiring adapted to propagate the drive signal, and a data wiring adapted to propagate a data signal. A multi-layered wiring structure is used so that a second wiring layer is formed on a layer different from that on which a first wiring layer is formed.

Abstract: A Static Random Access Memory (SRAM) cell includes a first pull-up transistor and a second pull-up transistor, and a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor. A conductive feature includes a first leg having a first longitudinal direction, wherein the first leg interconnects a drain of the first pull-up transistor and a drain of the first pull-down transistor. The conductive feature further includes a second leg having a second extending direction. The first longitudinal direction and the second extending direction are un-perpendicular and un-parallel to each other. The second leg interconnects the drain of the first pull-up transistor and a gate of the second pull-up transistor.

Abstract: An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and second ROM cells. The strap cell includes second portions of the first and second gate structures. The first gate structure is physically separated from the second gate structure.

Abstract: A system for designing an integrated circuit includes at least one processor and at least one memory including computer program code for one or more programs. The at least one memory and the computer program code are configured to, with the at least one processor, cause the system to receive a proposed device array layout from a device array design module. The device array design module is configured to generate the proposed device array layout free from a set of system design rule constraints. The system is also caused to revise a schematic of the integrated circuit including the proposed device array layout. The system is further caused to determine whether the revised schematic violates one or more system design rule constraints.

Abstract: Cell layouts for a memory cell, such as for ternary content addressable memory (TCAM), are disclosed. Some cell layouts include a well strap structure. A cell layout may include a p-doped well, an n-doped well, and a p-doped well sequentially along a layout. Another cell layout may include a p-doped well, an n-doped well, a p-doped well, and an n-doped well sequentially along a layout. A well strap structure may be in a p-doped well or an n-doped well. Various metallization layers having a mesh may be used with a memory cell layout. In some disclosed examples, a first metallization layer may have one, two, or four ground traces, and a second metallization layer may have two ground traces. These various ground traces may be electrically coupled together to form a mesh.

Abstract: According to one embodiment, a chip is described comprising a plurality of supply lines delimiting a plurality of cell areas and a gate comprising a first transistor and a second transistor, wherein the first transistor is located in a first cell area of the plurality of cell areas and the second transistor is located in a second cell area of the plurality of cell areas such that a supply line of the plurality of supply lines lies between the first cell area and the second cell area.

Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first passivation layer overlying the plurality of IMD layers and the first conductive layers; at least a first power/ground mesh wiring line in a first aluminum layer overlying the first Insulating layer; and at least a second power/ground mesh wiring line in a second aluminum layer overlying the first aluminum layer.

Abstract: Disclosed herein is a semiconductor device includes: a plurality of first power supply wirings provided on a first wiring layer and extending in a first direction; a plurality of second power supply wirings provided on a second wiring layer different from the first wiring layer and extending in a second direction intersecting the first direction; a signal wiring provided on the second wiring layer and extending in the second direction; and a plurality of through-hole conductors each electrically connecting an associated one of the first power supply wirings to an associated one of the second power supply wirings. At least a part of the first power supply wirings have a notch in a portion intersecting the signal wiring.

Abstract: First, second, and third power wirings and plurality of first signal wirings are formed on the upper layer of a semiconductor substrate, and at least one second signal wiring is formed on the upper layer of the plurality of first signal wirings. First and second power wirings are mutually separated in the cell height direction and extended in the cell width direction. Third power wiring extends between the first and second power wirings in the cell width direction. The plurality of first signal wirings are separated from first, second, and third power wirings, and electrically connected to at least one of the plurality of circuit elements. At least one second signal wiring extends in the cell width direction, and electrically connected to at least one of the plurality of circuit elements and the plurality of first signal wirings.