Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, an end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, a charge storage material layer located between the plurality of control gate electrodes and the semiconductor channel, a tunnel dielectric located between the charge storage material layer and the semiconductor channel, and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. Each of the plurality of control gate electrodes are located at least partially in an opening in the clam-shaped blocking dielectric, and a plurality of discrete cover oxide segments embedded in part of a thickness of the charge storage material layer and located between the blocking dielectric and the charge storage material layer.

Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.

Abstract: This semiconductor device (100A) includes: a substrate (1); a gate electrode (3) and a first transparent electrode (2) which are formed on the substrate (1); a first insulating layer (4) formed over the gate electrode (3) and the first transparent electrode (2); an oxide semiconductor layer (5) formed on the first insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); and a second transparent electrode (7) electrically connected to the drain electrode (6d). At least a portion of the first transparent electrode (2) overlaps with the second transparent electrode (7) with the first insulating layer (4) interposed between them, and the oxide semiconductor layer (5) and the second transparent electrode (7) are formed out of the same oxide film.

Abstract: An integrated circuit and an operating method for the same are provided. The integrated circuit comprises a stacked structure and a conductive structure. The stacked structure comprises a conductive strip. The conductive structure is disposed above the stacked structure and electrically connected to the conductive strip. The conductive structure and the conductive strip have various gap distances between corresponding points of different pairs according to a basic axis.

Abstract: An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.

Abstract: An integrated semiconductor device having a stabilization function includes a substrate layer, an insulating layer, ground plane layer formed between the substrate layer and the insulating layer and a signal plane layer formed on a surface of the insulating layer facing away from the substrate layer. An n-port, e.g. a transistor, is formed within the substrate layer on a first side of the substrate layer. A via hole is formed through the insulating layer. A resistor is formed within the ground plane layer.

Abstract: According to one embodiment, a semiconductor is provided with a MOS transistor and 1st to 5th signal lines. The MOS transistor has a gate finger structure with gate terminals. The 1st line is formed parallel to a gate width direction at each of ends of gate terminals and connected to one end of one gate terminal. The 2nd line connected to the 1st line is formed perpendicular to the direction outside an active region. The 3rd line with a smaller line width than a gate width is formed perpendicular to the direction and connected to each drain on the active region. The 4th line connected to a source is formed parallel to the direction. The 5th line connected to the 4th line is formed such that the 5th line does not overlap the 2nd line.

Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Abstract: A junction box, comprising a multi-layer circuit board, wherein the circuit board (6) comprises: a plurality of dielectric layers, each having conducting track on a side and arranged one on top of another to form the multi-layered circuit board; power circuitry (4) mounted on the circuit board; signal processing circuitry (5) mounted on the circuit board; and a power input for inputting electrical power into the circuitry on the circuit board, wherein the electrical power is transferred through conducting track (12) arranged to be on an inner dielectric layer, the conducting track on the inner dielectric layer being thicker than the conducting track arranged on the outer dielectric layers, and wherein the power circuitry is arranged on one region of the circuit board and the signal processing circuitry is arranged on another region of the circuit board, the two regions being thermally isolated by a thermal dam (9).

Abstract: Semiconductor structures including an etch stop material between a substrate and a stack of alternating insulating materials and first conductive materials, wherein the etch stop material comprises an amorphous aluminum oxide on the substrate and a crystalline aluminum oxide on the amorphous aluminum oxide; a channel material extending through the stack; and a second conductive material between the channel material and at least one of the first conductive materials in the stack of alternating insulating materials and first conductive materials, wherein the second conductive material is not between the channel material and the etch stop material. Also disclosed are methods of fabricating such semiconductor structures.

Abstract: A solid-state imaging device comprising a semiconductor substrate; a logic circuit region having a first gate electrode; a pixel region having a plurality of pixel units, each which includes at least one second gate electrode; a first gate insulating film forming between the first gate electrode in the logic circuit region and the semiconductor substrate; a second gate insulating film forming between the second gate electrode in the pixel region and the semiconductor substrate; a first insulating layer covering the first gate electrode and the second gate electrode; and an offset spacer on a sidewall of the first gate electrode being formed by etch back of the first insulating layer on the first gate electrode.

Abstract: In one embodiment, a semiconductor device includes a substrate, and one or more logic circuit regions disposed on the substrate, and including a plurality of logic circuit elements. The device further includes a memory region disposed on the substrate, including a plurality of memory cells, and having a shape to surround each of the one or more logic circuit regions.

Abstract: In aspects of the invention, an n-type epitaxial layer that forms an n? type drift layer is formed on the upper surface of an n-type semiconductor substrate formed by being doped with a high concentration of antimony. A p-type anode layer is formed on a surface of the n? type drift layer. An n-type contact layer is formed with an impurity concentration in the same region as the impurity concentration of the n-type cathode layer, or higher than the impurity concentration of the n-type cathode layer, on the lower surface of the n-type cathode layer. A cathode electrode is formed so as to be in contact with the n-type contact layer. The n-type contact layer is doped with phosphorus and, without allowing complete recrystallization using a low temperature heat treatment of 500° C. or less, lattice defects are allowed to remain.

Abstract: A semiconductor device includes a logic circuit and an active element circuit. The logic circuit is provided with semiconductor elements formed in a semiconductor substrate. The active element circuit is provided with transistors formed using semiconductor layers formed over a diffusion insulating film formed above a semiconductor substrate. The active element circuit is controlled by the logic circuit.

Abstract: Embodiments described herein provide approaches for improving a standard cell connection for circuit routing. Specifically, provided is an IC device having a plurality of cells, a first metal layer (M1) pin coupled to a contact bar extending from a first cell of the plurality of cells, and a second metal layer (M2) wire coupled to the contact bar, wherein the contact bar extends across at least one power rail. By extending the contact bar into an open area between the plurality of cells to couple the M1 pin and the M2 wire, routing efficiency and chip scaling are improved.

Abstract: A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.

Abstract: A container is provided for heating items, such as contents of the container. The container has a compartment for storing an air-activated material for heating those contents. The compartment is formed between a first web of material and a second web of material, where the first web includes a first film layer laminated to a second film layer via an adhesive layer. The second film layer includes a plurality of score lines that define plugs, such that when the first film layer or a portion thereof is peeled away from the second film layer, the plugs are separated and displaced from the second film layer to create openings in the second film layer that allow air to enter the compartment. When the air contacts the air-activated material to activate the material, an exothermic reaction takes place that serves to produce heat, such as to heat the contents of the container.

Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes a first plurality of circuit elements where a first portion of the first plurality of circuit elements has defects. The second layer includes a second plurality of circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second plurality of circuit elements for mitigating the defects.

Abstract: Methods for forming a DSA pre-patterned semiconductor transistor layout and the resulting devices are disclosed. Embodiments may include forming a pre-patterned transistor layout by directed self-assembly (DSA), forming a metal layer over the DSA pre-patterned transistor layout, including: forming a plurality of horizontal metal lines; and forming a plurality of vertical metal segments discontinuous from and between adjacent horizontal metal lines; and forming one or more bridging dots each connecting one of the plurality of horizontal metal lines to one of the plurality of vertical metal segments, wherein locations of the bridging dots determine logic functions of resulting transistor cells.

Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.

Abstract: A multi-field effect transistor (FET) device includes a first FET device arranged on a substrate, the first FET device including a first active region and a second active region, a second FET device arranged on the substrate, the second FET device including a first active region and a second active region, and a first conductive interconnect electrically connecting the first active region of the first FET device to the first active region of the second FET device, the first conductive interconnect having a first cross sectional area proximate to the first active region of the first FET device that is greater than a second cross sectional area proximate to the first active region of the second FET device.

Abstract: To form an interconnect conductor structure, a stack of pads, coupled to respective active layers of a circuit, is formed. Rows of interlayer conductors are formed to extend in an X direction in contact with landing areas on corresponding pads in the stack. Adjacent rows are separated from one another in a Y direction generally perpendicular to the X direction. The interlayer conductors in a row have a first pitch in the X direction. The interlayer conductors in adjacent rows are offset in the X direction by an amount less than the first pitch. Interconnect conductors are formed over and in contact with interlayer conductors. The interconnect conductors extend in the Y direction and have a second pitch less than the first pitch.

Abstract: A semiconductor device may include a semiconductor layer including at least one unit device, a first interconnection on the semiconductor layer and electrically connected to the at least one unit device, a diffusion barrier layer on the first interconnection, an intermetallic dielectric layer on the diffusion barrier layer, a plug in a first region of the intermetallic dielectric layer and passing through the diffusion barrier layer so that a bottom surface thereof contacts the first interconnection, and a first dummy plug in a second region of the intermetallic dielectric layer, passing through the diffusion barrier layer, and disposed apart from the first interconnection so that a bottom surface of the first dummy plug does not contact the first interconnection.

Abstract: There is provided a wiring material including a core layer made of metal and a clad layer made of metal and a fiber in which the core layer is copper or an alloy containing copper and the clad layer is formed of copper or the alloy containing copper and the fiber having a thermal expansion coefficient lower than that of copper, the wiring material having a stacked structure in which at least one surface of the core layer is closely adhered to the clad layer, and the fiber in the clad layer is arranged so as to be parallel to the surface of the core layer.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first metal layer on a carrier; forming an insulation layer directly on the first metal layer; exposing a portion of the first metal layer for directly attaching to a die interconnect connecting to an integrated circuit; forming a second metal layer directly on the insulation layer opposite the side of the insulation layer exposed by removing the carrier; and forming a protective layer directly on the insulation layer and the second metal layer, the protective layer exposing a portion of the second metal layer for directly attaching an external interconnect.

Abstract: A capacitor structure includes first and second sets of electrodes and a plurality of line plugs. The first set of electrodes has a first electrode and a second electrode formed in a first metallization layer among a plurality of metallization layers, wherein the first electrode and the second electrode are separated by an insulation material. The second set of electrodes has a third electrode and a fourth electrode formed in a second metallization layer among the plurality of metallization layers, wherein the third electrode and the fourth electrode are separated by the insulation material. The line plugs connect the second set of electrodes to the first set of electrodes.

Abstract: Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.

Abstract: A method for forming a contact structure includes forming a stack of alternating active layers and insulating layers. The stack includes first and second sub stacks each with active layers separated by insulating layers. The active layers of each sub stack include an upper boundary active layer. A sub stack insulating layer is formed between the first and second sub stacks with an etching time different from the etching times of the insulating layers for a given etching process. The upper boundary active layers are accessed, after which the remainder of the active layers are accessed to create a stairstep structure of landing areas on the active layers. Interlayer conductors are formed to extend to the landing areas, the interlayer conductors separated from one another by insulating material.

Abstract: An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.

Abstract: A test pattern of a semiconductor device includes a plurality of active regions defined in a semiconductor substrate and arranged in parallel with each other, a plurality of gate patterns formed over the plurality of active regions, a plurality of gate contacts formed over the plurality of gate patterns, first junction contacts formed over respective end portions of odd-numbered active regions among the plurality of active regions, second junction contacts formed over respective end portions of even-numbered active regions among the plurality of active regions, and a contact pad configured to couple the first junction contacts and the plurality of gate contacts.

Abstract: To decrease the burden of digital processing, provided is an AD conversion apparatus comprising a pattern generating section that, for each target bit specified one bit at a time moving downward in the output data, generates a pattern signal having a pulse width or number of pulses corresponding to a weighting of the target bit; an integrating section that integrates the pattern signals according to a judgment value for judging a value of the target bit each time a pattern signal is generated, and outputs a reference signal obtained by accumulating the integrated value of each pattern signal; a comparing section that, each time generation of a pattern signal is finished, compares the input signal to the reference signal; and an output section that outputs the output data to have values corresponding to the comparison results obtained after each generation of a pattern signal corresponding to a bit is finished.

Abstract: A power metal-oxide-semiconductor (MOS) field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die, A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material, A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to the grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.

Abstract: Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer Arrays and methods of operation are described.

Abstract: A three-dimensional semiconductor device comprises active patterns arranged two-dimensionally on a substrate, electrodes arranged three-dimensionally between the active patterns, and memory regions arranged three-dimensionally at intersecting points defined by the active patterns and the electrodes. Each of the active patterns is used as a common current path for an electrical connection to two different memory regions that are formed at the same height from the substrate.

Abstract: A device includes an array of a plurality of memory cells, at least one N-well contact area and at least one P-well contact area. The memory cells are arranged in a plurality of rows and a plurality of columns. Each column includes an N-well region and at least one P-well region. The N-well and P-well regions extend between a first end of the column and a second end of the column. Each N-well contact area electrically contacts at least one of the N-well regions, wherein the N-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column. Each P-well contact area electrically contacts at least one of the P-well regions, wherein the P-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column.

Abstract: The present invention discloses a three-dimensional writable printed memory (3D-wP). It comprises at least a printed memory array and a writable memory array. The printed memory array stores contents data, which are recorded with a printing means; the writable memory array stores custom data, which are recorded with a writing means. The writing means is preferably direct-write lithography. To maintain manufacturing throughput, the total amount of custom data should be less than 1% of the total amount of content data.

Abstract: When a first wiring and/or a second wiring is formed, a connection portion is formed in the first wiring and/or the second wiring which covers a part of a lower electrode layer outside the memory cell array. An etching suppressing portion is formed above the connection portion. A contact hole is formed in which a portion under the etching suppressing portion reaches up to a connection potion, and the other portion reaches up to the lower electrode layer by performing etching to a laminated body in a range including the etching suppressing portion. The laminated body includes the insulating layer, the first wiring, a memory cell layer, the second wiring, and the etching suppressing portion. The contact layer is formed by burying a conductive material in the contact hole.

Abstract: Described is a method for adjusting an operating temperature of MOS power components composed of a plurality of identical individual cells and a component for carrying out the method. As a characteristic feature, the gate electrode network (4) of the active chip region is subdivided into several gate electrode network sectors (B1, B2, B3) which are electrically isolated from one another by means of isolating points and to each of which a different gate voltage is fed via corresponding contacts.

Abstract: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.

Abstract: An organic light emitting diode (OLED) display includes a substrate where a plurality of pixels are formed, a first pixel defining layer on the substrate, the first pixel defining layer dividing the plurality of pixels, a connection wire on the first pixel defining layer, the connection wire electrically connecting two adjacent pixels, and a second pixel defining layer on the first pixel defining layer, the second pixel defining layer covering the connection wire.

Abstract: According to one embodiment, a first back surface of a first substrate and a second front surface of a second substrate are jointed together so as to connect a first conductor with a second conductor. The first conductor includes a portion having a diameter equal to that of a first gap formed above a first metal layer in a range between the first metal layer and a first front surface, and a portion having a diameter greater than that of the first gap and smaller than an outer diameter of the first metal layer in a range between the first metal layer and the first back surface. A first insulating layer has a gap formed above the first metal layer, the gap being greater than the first gap and smaller than the outer diameter of the first metal layer.

Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Abstract: A flash memory is disclosed. A core array stores data. A peripheral circuit accesses the data stored in the core array to generate read data. A off-chip driver (OCD) processes the read data to generate output data. An interconnect structure is electrically connected to the core array, the peripheral circuit, and the OCD and includes three conductive layers. The conductive layers are electrically connected to each other. An uppermost conductive layer is formed over the interconnect structure, electrically connected to the interconnect structure, and includes a first power pad and first power tracks. The first power pad is electrically connected to a power pin via a first bonding wire to receive an operation voltage. The first power tracks are electrically connected between the first power pad and the interconnect structure to transmit the operation voltage to at least one of the core array, the peripheral circuit and the OCD.

Abstract: A switching circuit comprises a first transistor and a second transistor formed in an active area of semiconductor substrate. The source and drain regions of the transistors are electrically connected to respective source wires and drain wires through a plurality of intermediate metal layers stacked above the transistor. Electrical connections between different layers are made with a plurality of vias. To improve switching performance, the intermediate wires are disposed such that intermediate wires electrically connected to the transistor source regions are not directly beneath the drain wires. Similarly, intermediate wires electrically connected to drain regions are arranged not to be directly underneath source wires.

Abstract: An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor.

Abstract: A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Conductive features are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected. However, the first PMOS and second NMOS transistor devices are physically separate within the gate electrode level region. The gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected. However, the second PMOS and first NMOS transistor devices are physically separate within the gate electrode level region.

Abstract: An SRAM cell of a semiconductor device includes a load transistor, a driver transistor and an access transistor. First source/drains of the load, driver and access transistors are connected to a node. A power line, a ground line and a bit line are electrically connected to second source/drains of the load transistor, the driver transistor and the access transistor. The power line, the ground line and the bit line are disposed at substantially the same level to extend in a first direction. A word line is electrically connected to a gate of the access transistor to extend in a second direction perpendicular to the first direction. The word line is disposed at a different level from the level of the power line, the ground line and the bit line.

Abstract: A first wiring (1) has a bending portion (2), a first wiring region (1a) extending from the bending portion (2) in the X direction, and a second wiring region (1b) extending from the bending portion (2) in the Y direction. A via (3) is formed under the wiring (1). The via (3) is formed so as not to overlap with a region of the bending portion (2) in the first wiring region (1a). The length of the via (3) in the X direction (x) is longer than the length thereof in the Y direction (y) and both ends of the via (3) in the Y direction overlap with both ends of the first wiring region (1a) in the Y direction.

Abstract: A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Conductive features are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected in part by a first conductor within a first interconnect level. The gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected in part by a second conductor within the first interconnect level. The first PMOS, second PMOS, first NMOS, and second NMOS transistor devices define a cross-coupled transistor configuration having commonly oriented gate electrodes.

Abstract: A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n?3)-th (n is a positive integer) and (4n?2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n?1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.