Responsive To Non-electrical External Signal (e.g., Imager) Patents (Class 257/222)
  • Publication number: 20110226936
    Abstract: Pixels, imagers and related fabrication methods are described. The described methods result in cross-talk reduction in imagers and related devices by generating depletion regions. The devices can also be used with electronic circuits for imaging applications.
    Type: Application
    Filed: March 18, 2010
    Publication date: September 22, 2011
    Inventors: Bedabrata PAIN, Thomas J. Cunningham
  • Patent number: 8013336
    Abstract: A solid-state imaging device of a three-transistor pixel configuration having no selection transistor has a problem of a non-selection hot carrier white point, which is specific to this apparatus. A bias current during a non-reading period of pixels is made to flow to a pixel associated with an immediately previous selection pixel, for example, the immediately previous selection pixel itself. As a result, dark current only for one line occurs in each pixel, and the dark current for one line itself can be reduced markedly. Consequently, defective pixels due to non-selection hot carrier white points can be virtually eliminated.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: September 6, 2011
    Assignee: Sony Corporation
    Inventor: Keiji Mabuchi
  • Patent number: 8008690
    Abstract: An amorphous-silicon thin film transistor and a shift resister shift resister having the amorphous-silicon TFT include a first conductive region, a second conductive region and a third conductive region. The first conductive region is formed on a first plane spaced apart from a substrate by a first distance. The second conductive region is formed on a second plane spaced apart from the substrate by a second distance. The second conductive region includes a body conductive region and two hand conductive regions elongated from both ends of the body conductive region to form an U-shape. The third conductive region is formed on the second plane. The third conductive region includes an elongated portion. The elongated portion is disposed between the two hand conductive regions of the second conductive region. The amorphous-silicon TFT and the shift resister having the amorphous TFT reduce a parasitic capacitance between the gate electrode and drain electrode.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: August 30, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Hwan Moon, Back-Won Lee
  • Patent number: 8004020
    Abstract: A solid-state image capturing device includes a plurality of electrode pads for inputting and outputting a signal or voltage from and to the outside, a plurality of photoelectric conversion elements, a planarization film for planarizing the difference in the level on the surface above the plurality of photoelectric conversion elements, a microlens for focusing incident light on each of the plurality of photoelectric conversion elements, and a protection film provided above the microlens and the planarization film, the planarization film and the protection film above the plurality of electrode pads being removed as an opening, where the protection film has a protection film removing area that at least includes an area removed across all or a corner portion of the opening and the image capturing area.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: August 23, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Takayuki Kawasaki
  • Patent number: 8004019
    Abstract: P type semiconductor well regions 8 and 9 for device separation are provided in an upper and lower two layer structure in conformity with the position of a high sensitivity type photodiode PD, and the first P type semiconductor well region 8 at the upper layer is provided in the state of being closer to the pixel side than an end portion of a LOCOS layer 1A, for limiting a dark current generated at the end portion of the LOCOS layer 1A. In addition, the second P type semiconductor well region 9 at the lower layer is formed in a narrow region receding from the photodiode PD, so that the depletion layer of the photodiode PD is prevented from being obstructed, and the depletion is secured in a sufficiently broad region, whereby enhancement of the sensitivity of the photodiode PD can be achieved.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: August 23, 2011
    Assignee: Sony Corporation
    Inventors: Hiroaki Fujita, Ryoji Suzuki, Nobuo Nakamura, Yasushi Maruyama
  • Publication number: 20110198481
    Abstract: An image sensor and a method of operating the image sensor are provided. At least one pixel of the image sensor includes a detection portion including a plurality of doping areas having different pinning voltages, and a demodulation portion to receive an electron from the detection portion, and to demodulate the received electron.
    Type: Application
    Filed: February 8, 2011
    Publication date: August 18, 2011
    Applicant: SAMSUNG ELECTRONICS Co., LTD.
    Inventors: Seong Jin Kim, Sang Woo Han
  • Patent number: 7999340
    Abstract: An apparatus and method for forming optical black pixels having uniformly low dark current. Optical Black opacity is increased without having to increase Ti/TiN layer thickness. A hybrid approach is utilized combining a Ti/TiN OB layer in conjunction with in-pixel metal stubs that further occlude the focal radius of each pixel's incoming light beam. Additional metal layers can be used to increase the opacity into the infrared region.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: August 16, 2011
    Assignee: AltaSens, Inc.
    Inventors: Giuseppe Rossi, Lester Kozlowski, Henry Lin, John Richardson, Gregory Chow, Gaurang Patel
  • Patent number: 7999292
    Abstract: An image sensor can be formed of a first substrate having a readout circuitry, an interlayer dielectric, and lower lines, and a second substrate having a photodiode. The first substrate comprises a pixel portion and a peripheral portion. The readout circuitry is formed on the pixel portion. The interlayer dielectric is formed on the pixel portion and the peripheral portion. The lower lines pass through the interlayer dielectric to electrically connect with the readout circuitry and the peripheral portion. The photodiode is bonded to the first substrate and etched to correspond to the pixel portion. A transparent electrode is formed on the interlayer dielectric on which the photodiode is formed such that the transparent electrode can be connected with the photodiode and the lower line in the peripheral portion. A first passivation layer can be formed on the transparent electrode. In one embodiment, the first passivation layer includes a trench exposing a portion of the transparent electrode.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: August 16, 2011
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Joon Hwang
  • Publication number: 20110193137
    Abstract: A solid-state imaging device includes: a photoelectric converting section comprising a photo-diode; a charge storage section; a charge transfer section; a first control gate section provided between the photoelectric converting section and the charge storage section to control transfer of a signal charge from the photoelectric converting section to the charge storage section; and a second control gate section provided between the charge storage section and the charge transfer section to control transfer of the signal charge from the charge storage section to the charge transfer section. The charge storage section includes: a first region formed on a side near to the first control gate section; and a second region formed on a side near to the second control gate section and configured to have a channel potential increased more than that of the first region. The second region is configured to hold the signal charge in a pinning condition.
    Type: Application
    Filed: February 9, 2011
    Publication date: August 11, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Ryoichi GOTO
  • Patent number: 7994546
    Abstract: The invention provides a method for forming a sodium ion selective electrode, including: (a) providing a conductive substrate; (b) forming a conductive wire which extends from the conductive substrate for external contact; and (c) forming a sodium ion sensing film on the conductive substrate, wherein the method for forming the conductive substrate includes: providing a substrate; and forming a conductive layer on the substrate.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: August 9, 2011
    Assignee: National Yunlin University of Science and Technology
    Inventors: Jung-Chuan Chou, Ya-Ping Huang, Chien-Cheng Chen
  • Publication number: 20110168873
    Abstract: Disclosed are a pinned photodiode having and electrically controllable pinning layer and an image sensor including the pinned photodiode. A predetermined voltage is applied to the pinning layer for the depletion duration of the photodiode in the image sensor, so that stable surface pinning is acquired and the uniform surface pinning is achieved between pixels.
    Type: Application
    Filed: August 19, 2009
    Publication date: July 14, 2011
    Applicant: CROSSTEK CAPITAL, LLC
    Inventor: Man Lyun Ha
  • Publication number: 20110169993
    Abstract: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of less than about 0.4 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V.
    Type: Application
    Filed: March 21, 2011
    Publication date: July 14, 2011
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventor: Howard E. Rhodes
  • Publication number: 20110156104
    Abstract: A solid-state imaging device including a semiconductor substrate, a photoelectric conversion portion interposed between a lower electrode and an upper electrode, a contact plug formed so as to connect the lower electrode and the semiconductor substrate in order to read signal charges generated in the photoelectric conversion portion to the semiconductor substrate side, a vertical type transmitting path configured by sequentially laminating a connection portion for electrically connecting the contact plug to the semiconductor substrate, a charge accumulation layer for accumulating the signal charges read to the connection portion, and a potential barrier layer configuring a potential barrier between the connection portion and the charge accumulation layer in a vertical direction of the semiconductor substrate, and a charge reading portion configured to read the signal charges accumulated in the charge accumulation layer to the circuit forming surface side of the semiconductor substrate.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 30, 2011
    Applicant: SONY CORPORATION
    Inventor: Tetsuji Yamaguchi
  • Publication number: 20110156105
    Abstract: A sensor includes a substrate, a floating diffusion node in the substrate, a photodiode in the substrate laterally spaced apart from the floating diffusion region and a transfer transistor coupling the photodiode and the floating diffusion region. The sensor further includes a photodiode control electrode disposed on the photodiode and configured to control a carrier distribution of the photodiode responsive to a control signal applied thereto. The floating diffusion region may have a first conductivity type, the photodiode may include a first semiconductor region of a second conductivity type disposed on a second semiconductor region of the first conductivity type, and the photodiode control electrode may be disposed on the first semiconductor region. The photodiode may be configured to receive incident light from a side of the substrate opposite the photodiode control electrode.
    Type: Application
    Filed: March 7, 2011
    Publication date: June 30, 2011
    Inventors: Yi-tae Kim, Jung-chak Ahn
  • Patent number: 7964451
    Abstract: A first oxide film (102) is formed on a semiconductor substrate (101). A first nitride film (103) is formed on first gate electrode formation regions of the first oxide film (102). A plurality of first gate electrodes (104) are provided on the first nitride film (103) so as to be spaced apart from one another with a predetermined distance therebetween. A second oxide film (105) covers upper part and side walls of each of the first gate electrodes (104). A sidewall spacer (106) of a third oxide film is buried in an overhang portion generated on each side wall of each of the first gate electrodes (104) covered by the second oxide film (105). A second nitride film (107) covers the second oxide film (105), the sidewall spacer (106) and part of the first oxide film (102) located between the first gate electrodes (104). A plurality of second gate electrodes (108) are formed on at least part of the second nitride film (107) located between adjacent two of the first gate electrodes (104).
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: June 21, 2011
    Assignee: Panasonic Corporation
    Inventors: Naoto Niisoe, Kazuhisa Hirata, Tohru Yamada
  • Patent number: 7964898
    Abstract: The present invention provides a back illuminated photodetector having a sufficiently small package as well as being capable of suppressing the scattering of to-be-detected light and method for manufacturing the same. A back illuminated photodiode 1 comprises an N-type semiconductor substrate 10, a P+-type impurity semiconductor region 11, a recessed portion 12, and a window plate 13. In the surface layer on the upper surface S1 side of the N-type semiconductor substrate 10 is formed the P+-type impurity semiconductor region 11. In the rear surface S2 of the N-type semiconductor substrate 10 and in an area opposite the P+-type impurity semiconductor region 11 is formed the recessed portion 12 that functions as an incident part for to-be-detected light. Also, the window plate 13 is bonded to the outer edge portion 14 of the recessed portion 12. The window plate 13 covers the recessed portion 12 and seals the rear surface S2 of the N-type semiconductor substrate 10.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: June 21, 2011
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Katsumi Shibayama
  • Publication number: 20110140177
    Abstract: According to one embodiment, a solid-state imaging device includes a semiconductor region, a first diffusion layer, a second diffusion layer, a third diffusion layer, an insulating film, a potential layer, and a read electrode. The semiconductor region includes first and second surfaces. The first diffusion layer is formed in the first surface. The first diffusion layer's concentration is a maximum value in a position at a first depth. The charge accumulation layer has a second depth. The second diffusion layer contacts the first diffusion layer. The third diffusion layer is formed in a position which faces the second diffusion layer in respect to the first diffusion layer. The insulating film is formed on the first surface. The potential layer is formed on the insulating film and has a predetermined potential. The read electrode is formed on the insulating film.
    Type: Application
    Filed: September 17, 2010
    Publication date: June 16, 2011
    Inventor: Hirofumi YAMASHITA
  • Patent number: 7960762
    Abstract: It is an object to provide a CCD solid-state image sensor, in which an area of a read channel is reduced and a rate of a surface area of a light receiving portion (photodiode) to an area of one pixel is increased.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: June 14, 2011
    Assignee: Unisantis Electronics (Japan) Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20110134299
    Abstract: A CCD-type solid-state imaging device includes: light receiving devices arranged in vertical and horizontal directions; vertical transfer parts arranged along vertical rows of the arranged light receiving devices, reading out charge accumulated in the adjacent light receiving devices, and transferring the read out charge in the vertical direction; a horizontal transfer part supplied with the charge transferred in the vertical transfer parts and transferring the supplied charge in the horizontal direction; an output part outputting the charge transferred in the vertical transfer parts; an input terminal for readout and transfer clocks that command readout of the charge from the light receiving devices and transfer of the read out charge in the vertical transfer parts; a resistor connected between the input terminal and a clock supply part of the vertical transfer parts; and a switch part connected to the resistor in parallel and switching between the charge readout and the charge transfer in the vertical trans
    Type: Application
    Filed: November 30, 2010
    Publication date: June 9, 2011
    Applicant: Sony Corporation
    Inventors: Yuya Kani, Katsumi Yamagishi
  • Patent number: 7955924
    Abstract: Example embodiments disclose an image sensor capable of preventing or reducing image lag and a method of manufacturing the same. Example methods may include forming a gate insulating film and a gate conductive film doped with a first-conductive-type dopant on a semiconductor substrate; forming a transfer gate pattern by patterning the gate insulating film and the gate conductive film; and fabricating a transfer gate electrode by forming a first-conductive-type photodiode in the semiconductor substrate adjacent to one region of the transfer gate pattern, by forming a second-conductive-type photodiode on the first-conductive-type photodiode, and by forming a first-conductive-type floating diffusion region in the semiconductor substrate adjacent to the other region of the transfer gate pattern.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: June 7, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-ho Song, Chan Park, Young-hoon Park, Sang-il Jung, Jong-wook Hong, Keo-sung Park, Eun-soo Kim, Won-je Park, Jin-Hyeong Park, Dae-cheol Seong, Won-jeong Lee, Pu-ra Kim
  • Patent number: 7936035
    Abstract: A photoelectric conversion element comprises: a pair of electrodes; and an organic photoelectric conversion layer between the pair of electrodes, wherein one of the electrodes is a first electrode that collects electrons generated in the organic photoelectric conversion layer; the other one of the electrodes is a second electrode that collects holes generated in the organic photoelectric conversion layer; and the photoelectric conversion element further comprises a hole blocking layer that comprises silicon oxide and inhibits injection of holes into the organic photoelectric conversion layer from the first electrode while applying a bias voltage between the electrodes, the hole blocking layer being disposed between the first electrode and the organic photoelectric conversion layer, and an oxygen/silicon composition ratio of the silicon oxide is 0.5 or greater and 1.2 or less.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: May 3, 2011
    Assignee: FUJIFILM Corporation
    Inventors: Yoshiki Maehara, Takashi Goto, Kiyohiko Tsutsumi, Kyohei Ogawa, Takashi Komiyama, Takeshi Senga, Takehiro Kasahara
  • Publication number: 20110089311
    Abstract: An image sensor provides high scalability and reduced image lag. The sensor includes a first imaging pixel that has a first photodiode region formed in a substrate of the image sensor. The sensor also includes a first vertical transfer transistor coupled to the first photodiode region. The first vertical transfer transistor can be used to establish an active channel. The active channel typically extends along the length of the first vertical transfer transistor and couples the first photodiode region to a floating diffusion.
    Type: Application
    Filed: October 20, 2009
    Publication date: April 21, 2011
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Vincent Venezia, Hsin-Chih Tai, Duli Mao, Howard E. Rhodes
  • Publication number: 20110089471
    Abstract: A demodulation pixel improves the charge transport speed and sensitivity by exploiting two effects of charge transport in silicon in order to achieve the before-mentioned optimization. The first one is a transport method based on the CCD gate principle. However, this is not limited to CCD technology, but can be realized also in CMOS technology. The charge transport in a surface or even a buried channel close to the surface is highly efficient in terms of speed, sensitivity and low trapping noise. In addition, by activating a majority carrier current flowing through the substrate, another drift field is generated below the depleted CCD channel. This drift field is located deeply in the substrate, acting as an efficient separator for deeply photo-generated electron-hole pairs. Thus, another large amount of minority carriers is transported to the diffusion nodes at high speed and detected.
    Type: Application
    Filed: August 16, 2010
    Publication date: April 21, 2011
    Applicant: MESA IMAGING AG
    Inventors: Bernhard Buettgen, Jonas Felber, Michael Lehmann, Thierry Oggier
  • Patent number: 7919827
    Abstract: A method and device is disclosed for reducing noises in CMOS image sensors. An improved CMOS image sensor includes a light sensing structure surrounded by a support feature section. An active section of the light sensing structure is covered by no more than optically transparent materials. A light blocking portion includes a black light filter layer and an opaque layer covering the support feature section. The light blocking portion may also cover a peripheral portion of the light sensing structure. The method for forming the CMOS image sensors includes using film patterning and etching processes to selectively form the opaque layer where the light blocking portion is desired but not over the active section.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: April 5, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tien-Chi Wu, Tsung-Yi Lin
  • Publication number: 20110068251
    Abstract: A solid-state image sensor includes: four or more photoelectric conversion units having spectral sensitivity characteristics different from one another; an amplifier unit disposed in correspondence to each group of photoelectric conversion units among N groups (N represents an integer less than a quantity of the four or more photoelectric conversion units and equal to or greater than one), the four or more photoelectric conversion units being divided into the N groups; and transfer units, each disposed in correspondence to one of the four or more photoelectric conversion units, which transfer a signal generated at the photoelectric conversion unit to the amplifier unit disposed for the group to which the photoelectric conversion unit belongs.
    Type: Application
    Filed: August 6, 2010
    Publication date: March 24, 2011
    Applicant: NIKON CORPORATION
    Inventor: Tadashi NARUI
  • Patent number: 7910964
    Abstract: A part of a semiconductor layer directly under a light-receiving gate electrode functions as a charge generation region, and electrons generated in the charge generation region are injected into a part of a surface buried region directly above the charge generation region. The surface buried region directly under a first transfer gate electrode functions as a first transfer channel, and the surface buried region directly under a second transfer gate electrode functions as a second transfer channel. Signal charges are alternately transferred to an n-type first floating drain region and a second floating drain region through the first and second floating transfer channels.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: March 22, 2011
    Assignees: National University Corporation Shizuoka University, Sharp Kabushiki Kaisha
    Inventors: Shoji Kawahito, Mitsuru Homma
  • Patent number: 7906826
    Abstract: A CMOS image sensor with a many million pixel count. Applicants have developed techniques for combining its continuous layer photodiode CMOS sensor technology with CMOS integrated circuit lithography stitching techniques to provide digital cameras with an almost unlimited number of pixels. A preferred CMOS stitching technique exploits the precise alignment accuracy of CMOS stepper processes by using specialized mask sets to repeatedly produce a single pixel array pattern many times on a single silicon wafer with no pixel array discontinuities. The single array patterns are stitched together lithographically to form a pixel array of many million pixels. A continuous multilayer photodiode layer is deposited over the top of the many million pixel array to provide a many million pixel sensor with a fill factor of 100 percent or substantially 100 percent.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: March 15, 2011
    Assignee: e-Phocus
    Inventors: Peter Martin, Paul Johnson, Chris Sexton
  • Patent number: 7897928
    Abstract: A pixel is formed in a semiconductor substrate (S) with a plane surface for use in a photodetector. It comprises an active region for converting incident light (In) into charge carriers, photogates (PGL, PGM, PGR) for generating a lateral electric potential (?(x)) across the active region, and an integration gate (IG) for storing charge carriers generated in the active region and a dump site (Ddiff). The pixel further comprises separation-enhancing means (SL) for additionally enhancing charge separation in the active region and charge transport from the active region to the integration gate (IG). The separation-enhancing means (SL) are for instance a shield layer designed such that for a given lateral electric potential (?(x)), the incident light (In) does not impinge on the section from which the charge carriers would not be transported to the integration gate (IG).
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: March 1, 2011
    Assignee: MESA Imaging AG
    Inventors: Rolf Kaufmann, Thierry Oggier, Simon Neukom, Michael Lehmann
  • Patent number: 7888161
    Abstract: A method for producing a solid-state imaging device, which including: a photoelectric conversion section; a charge transfer section having a charge transfer electrode; and an antireflection film covering a light-receiving region in the photoelectric conversion section, wherein forming the antireflection film includes: forming a sidewall on a lateral wall of the charge transfer electrode after forming the charge transfer electrode; forming an antireflection film on a substrate surface where the sidewall is formed; forming a resist on the antireflection film; melting and flattening the resist to expose the antireflection film on the charge transfer electrode; removing the antireflection film by using the resist as the mask; removing the sidewall; covering the charge transfer electrode with an insulating film; and forming a light-shielding film that reaches a level lower than the top surface of the antireflection film, and that surrounds the periphery of the antireflection film.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: February 15, 2011
    Assignee: Fujifilm Corporation
    Inventor: Takanori Sato
  • Publication number: 20110031378
    Abstract: Provided is an electromagnetic wave reception device capable of being downsized and directly and simply (at least at a room temperature) detecting electromagnetic waves in a wider bandwidth including the terahertz range. The electromagnetic wave reception device that obtains charges according to an electric field of the electromagnetic waves incident on a semiconductor substrate includes: a high charge-density region provided on the semiconductor substrate and having a first charge density; a conductive region covering the high charge-density region via an insulation region; and a low charge-density region provided adjacent to the high charge-density region on the semiconductor substrate and having a second charge density lower than the first charge density, wherein the low charge-density region is connected to a charge detecting circuit that is not illustrated.
    Type: Application
    Filed: April 13, 2009
    Publication date: February 10, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Yutaka Hirose
  • Patent number: 7880259
    Abstract: A solid-state image sensor capable of improving detection sensitivity for an output signal is provided. This solid-state image sensor comprises a first gate electrode formed on a semiconductor substrate, a first impurity region formed on the semiconductor substrate at a first distance from the first gate electrode for receiving the signal charges and a second gate electrode formed at a second distance from the first impurity region for discharging unnecessary signal charges after extraction of a voltage signal from the first impurity region. The first distance between the first impurity region and the first gate electrode is larger than the second distance between the first impurity region and the second gate electrode.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: February 1, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Takayuki Kaida
  • Publication number: 20110018037
    Abstract: Provided is a solid-state imaging device including: a photodiode which converts an optical signal to signal charges; a transfer gate which transfers the signal charges from the photodiode; an impurity diffusion layer to which the signal charges are transferred by the transfer gate; and a MOS transistor of which a gate is connected to the impurity diffusion layer. The impurity diffusion layer has a first conduction type semiconductor layer and a second conduction type semiconductor layer which is formed in the first conduction type semiconductor layer and under an end portion of the transfer gate.
    Type: Application
    Filed: July 19, 2010
    Publication date: January 27, 2011
    Applicant: SONY CORPORATION
    Inventors: Hiroyuki Ohri, Yasunori Sogoh
  • Patent number: 7875491
    Abstract: A complementary metal-oxide-semiconductor image sensor may include: a semiconductor substrate; a photodiode formed on a first portion of the semiconductor substrate; a transfer gate formed on the semiconductor substrate, near the photodiode, to transfer optical charges accumulated in the photodiode; a floating diffusion area formed on a second portion of the semiconductor substrate, on an opposite side of the transfer gate from the photodiode, to accommodate the optical charges; and/or a channel area formed under the transfer gate and contacting a side of the photodiode to transfer the optical charges. The transfer gate may be formed, at least in part, of transparent material. A method of manufacturing a complimentary metal-oxide-semiconductor image sensor may include: forming the photodiode; forming the floating diffusion area, separate from the photodiode; and/or forming the transfer gate, near the photodiode, to transfer optical charges accumulated in the photodiode.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: January 25, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo-cheol Park, Jung-hyeon Kim, Jun-young Lee
  • Publication number: 20100327325
    Abstract: A charge transfer device formed in a semiconductor substrate and including an array of electrodes distributed in rows and columns, wherein: each electrode is formed in a cavity with insulated walls formed of a groove which generally extends in the row direction, having a first end closer to an upper row and a second end closer to a lower row; and the electrodes of two adjacent rows are symmetrical with respect to a plane orthogonal to the sensor and comprising the direction of a row.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 30, 2010
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Fran├žois Roy
  • Patent number: 7859032
    Abstract: During an exposure time period (long accumulation time period) of a low shutter speed shooting mode, a second reference voltage Vss2, which is different from a first reference voltage Vss1 (a ground voltage) corresponding to a reference voltage of a peripheral circuit, is applied to a well (5) where a photoelectric converter section (2) and a drain region (4) are formed, whereby generation of dark electrons at a portion of a surface of the well (5) below a gate electrode (6) is suppressed. A polarity of the second reference voltage Vss2 is positive in the case where a conductivity type of the well (5) is a P-type, and is negative in the case of an N-type.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: December 28, 2010
    Assignee: Panasonic Corporation
    Inventors: Makoto Inagaki, Yoshiyuki Matsunaga
  • Patent number: 7842979
    Abstract: A solid-state imaging device includes an N-type semiconductor substrate, an N-type impurity region provided in the surficial portion of the N-type semiconductor substrate, a photo-electric conversion unit formed in the N-type impurity region, a charge accumulation unit formed in the N-type impurity region so as to contact with the photo-electric conversion unit, and temporarily accumulating charge generated in the photo-electric conversion unit, a charge hold region (barrier unit) formed in the N-type impurity region so as to contact with the charge accumulation unit, and allowing the charge accumulation unit to accumulate the charge, and a charge accumulating electrode provided to the charge accumulation unit. The charge accumulation unit and the charge hold region are formed to be N?-type.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: November 30, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hiroyoshi Kudou, Satoshi Uchiya, Junichi Yamamoto, Fumiaki Futamura
  • Patent number: 7842978
    Abstract: An n-type region as a charge storage region of a photodiode is buried in a substrate. The interface between silicon and a silicon oxide film is covered with a high concentration p-layer and a lower concentration p-layer is formed only in the portion immediately below a floating electrode for signal extraction. Electrons generated by light are stored in the charge storage region, thereby changing the potential of the portion of the p-layer at the surface of the semiconductor region. The change is transmitted through a thin insulating film to the floating electrode by capacitive coupling and read out by a buffer transistor. Initialization of charges is executed by adding a positive high voltage to the gate electrode of a first transfer transistor such that the electrons stored in the charge storage region are transferred to the n+ region and generation of reset noise is protected.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: November 30, 2010
    Assignee: National University Corporation Shizuoka University
    Inventor: Shoji Kawahito
  • Publication number: 20100290028
    Abstract: A light detecting device includes a well region, a first holding region disposed in a surface portion of the well region, a second holding region and a third holding region disposed in a surface portion of the first holding region, an insulating layer disposed on the second holding region and the third holding region, a first electrode disposed on the second holding region through the insulating layer, and the second electrode disposed on the third holding region through the insulating layer. The first holding region is configured to hold a first carrier generated in the well region. Each of the second holding region and the third holding region is configured to hold a second carrier generated in the well region. The first carrier is one of an electron and a hole, and the second carrier is the other one of the electron and the hole.
    Type: Application
    Filed: May 12, 2010
    Publication date: November 18, 2010
    Applicant: DENSO CORPORATION
    Inventors: Yoshihide TACHINO, Ryoichi SUGAWARA
  • Publication number: 20100282944
    Abstract: A solid state imaging device includes: a light receiving section performing photoelectric conversion; a transfer register formed in a semiconductor base; a transfer electrode formed of a semiconductor layer on the transfer register; a charge transfer section which formed of the transfer register and the transfer electrode and transferring a signal charge accumulated in the light receiving section; a bus line electrically connected to a portion of the transfer electrode to supply a driving pulse to the transfer electrode and formed of a metal layer; and a barrier metal layer formed near an interface between the transfer electrode and the bus line in a contact section that connects the transfer electrode and the bus line with each other and having a work function of the size between a work function of the semiconductor layer of the transfer electrode and a work function of the metal layer of the bus line.
    Type: Application
    Filed: April 20, 2010
    Publication date: November 11, 2010
    Applicant: SONY CORPORATION
    Inventor: Fuminobu Saiho
  • Publication number: 20100283086
    Abstract: Disclosed is a metal optical filter capable of a photo-lithography process and an image sensor including the same, and more particularly, a metal optical filter capable of a photo-lithography process, which can quite freely adjust the transmission band and transmittance thereof, even with a small number of metal layers, and simultaneously, can be actually applied in a CMOS process because it is possible to achieve nanoscale patterning by the photo-lithography process, and an image sensor including the metal optical filter. The metal optical filter capable of a photo-lithography process includes a plurality of metal rods arranged in parallel with each other at an equal nanoscale interval; and an insulation material formed between the plurality of metal rods and on upper and lower surfaces of the plurality of metal rods, wherein the metal rod is formed to comprise an upper Ti layer, an Al layer, and a lower TiN layer.
    Type: Application
    Filed: May 6, 2010
    Publication date: November 11, 2010
    Applicant: SILICONFILE TECHNOLOGIES INC.
    Inventors: Byoung-Su LEE, Shin KIM, Sang-Shin LEE, Yeo-Taek YOON
  • Patent number: 7829921
    Abstract: An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e. one-sided) active area extension region on one side of the transistor gate opposite the photoconversion device, while other transistors can have normal symmetrical (i.e, two-sided) active area extension regions (e.g., lightly doped drains) with resulting high performance and short gate lengths. The asymmetrical active area extension region of the transistor associated with the photodiode can serve to reduce dark current at the photoconversion device. The punch-through problem normally cured by a lightly doped drain is fixed at the transistor associated with the photoconversion device by adding a Vt adjustment implant and/or increasing its gate length.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: November 9, 2010
    Assignee: Aptina Imaging Corporation
    Inventor: Howard E. Rhodes
  • Publication number: 20100258847
    Abstract: A six-phase charge coupled device (CCD) pixel includes a pixel pair, with each pixel having two adjacent control gates overlying corresponding variable potential wells, where voltages applied to the control gates enable charge to be accumulated into and transferred out of the wells. A clear window region overlies a fixed potential gradient region, decreasing in potential away from the control gates. This region enables a wide band of photons to be sensed by the photosensitive silicon of the CCD. The decreasing potential levels facilitate high charge transfer efficiency (i.e., high CTE) from pixel to pixel via the control or transfer gates. By applying particular voltages to the control gates, charge can be quickly and efficiently transferred between pixels.
    Type: Application
    Filed: May 14, 2010
    Publication date: October 14, 2010
    Applicant: IMAGERLABS INC.
    Inventor: Mark Wadsworth
  • Patent number: 7808018
    Abstract: A solid-state imaging apparatus includes a pixel array comprising a plurality of light receiving elements disposed in a charge transfer direction, the plurality of light receiving elements converting a light signal into an electric signal, a first charge transfer unit and a second charge transfer unit arranged on each side of the pixel array and transferring a signal charge input from the pixel array in the charge transfer direction, a first floating diffusion region connected to the first charge transfer unit, a second floating diffusion region connected to the second charge transfer unit, a wiring layer connecting the first floating diffusion region with the second floating diffusion region, and an output circuit connected to the wiring layer and output a signal voltage in accordance with a potential of the first floating diffusion region and the second floating diffusion region.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: October 5, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Akira Uemura
  • Patent number: 7804151
    Abstract: Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: September 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brennan J. Brown, James R. Elliott, Alvin J. Joseph, Edward J. Nowak
  • Patent number: 7799654
    Abstract: An image sensor device includes a semiconductor substrate and a plurality of pixels on the substrate. An etch-stop layer is formed over the pixels and has a thickness less than about 600 Angstroms. The image sensor device further includes an interlayer dielectric (ILD) overlying the etch stop layer. The etch-stop layer has a refractive index less than about 2 and an extinction coefficient less than about 0.1.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: September 21, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Chih Hsieh, Chung-Yi Yu, Tsung-Hsun Huang, Tzu-Hsuan Hsu, Chia-Shiung Tsai
  • Publication number: 20100230728
    Abstract: A noise generated by a constitution of widening an incident aperture of light of a photoelectric conversion element is reduced. In a manufacturing method of a photoelectric conversion device, first electroconductor arranged in a first hole arranged in the first interlayer insulation layer electrically connects a first semiconductor region to a gate electrode of an amplifying MOS transistor not through wirings included in a wiring layer. Moreover, a second electroconductor electrically connects a second semiconductor region different from the first semiconductor region to a wiring. In a constitution of that second electroconductor, a third electroconductor arranged in a second hole arranged in the first interlayer insulation layer and a fourth electroconductor arranged in a third hole arranged in the second interlayer insulation layer are stacked and electrically connected to each other.
    Type: Application
    Filed: May 21, 2010
    Publication date: September 16, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Takashi Okagawa, Hiroaki Naruse, Hiroshi Yuzurihara, Shigeru Nishimura, Takeshi Aoki, Yuya Fujino
  • Patent number: 7795649
    Abstract: Microfeature workpieces having microlenses and methods of forming microlenses on microfeature workpieces are disclosed herein. In one embodiment, a method for forming microlenses includes forming a plurality of shaping members on a microfeature workpiece between adjacent pixels, reflowing the shaping members to form a shaping structure between adjacent pixels, depositing lens material onto the workpiece, removing selected portions of the lens material adjacent to the shaping structure such that discrete masses of lens material are located over corresponding pixels, and heating the workpiece to reflow the discrete masses of lens material and form a plurality of microlenses.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: September 14, 2010
    Assignee: Aptina Imaging Corporation
    Inventors: Ulrich C. Boettiger, Jin Li
  • Patent number: 7795654
    Abstract: In the solid-state imaging device of the present invention having a photoelectric conversion section and a charge transfer section equipped with a charge transfer electrode for transferring an electric charge generated in the photoelectric conversion section, the charge transfer electrode has an alternate arrangement of a first layer electrode comprising a first conductive film and a second layer electrode comprising a second conductive film, and the first layer electrode and the second layer electrode are separated by insulation with an interelectrode insulating film having a two-layer structure comprising a sidewall insulating film consisting of a first insulating layer formed by a CVD method to cover the lateral wall of the first layer electrode and a second insulating film.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: September 14, 2010
    Assignee: Fujifilm Corporation
    Inventor: Maki Saito
  • Patent number: 7795698
    Abstract: An image pickup apparatus having plural light receiving areas arranged two-dimensionally, and vertical and horizontal scanning circuits composed of plural unit circuit stages arranged in the vertical and horizontal directions, respectively. The vertical and horizontal scanning circuits are arranged in spaces between the light receiving areas, wherein for unit circuit groups each constituted by two unit circuits of the horizontal or vertical scanning circuits, the unit circuit groups are arranged at a constant pitch.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: September 14, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tomoyuki Noda
  • Patent number: 7786515
    Abstract: A solid-state imaging device including: a semiconductor substrate on which an imaging region having a light receiving section is formed; and a predetermined layer formed on the semiconductor substrate by planarization processing using liquid containing a metal element, wherein at least a first diffusion protection film is formed between the light receiving section and the predetermined layer.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: August 31, 2010
    Assignee: Sony Corporation
    Inventor: Shinya Watanabe